Claims
- 1. A data processing system comprising:
- a data processing unit;
- a system data bus coupled to the data processing unit; said system data bus having a width being a longword which is a multiple of a shortword length;
- a system address bus coupled to said data processing unit:
- said data processing unit comprising:
- a shortword memory means comprising a first storage location for storing descriptor shortwords and a second storage location for storing message shortwords;
- means for passing shortwords between the first storage location of the shortword memory means and the system data bus individually without concatenating;
- means for concatenating and deconcatenating shortwords passing between the second storage location of the shortword memory means and the system data bus to match the longword length and the shortword length, respectively;
- internal address storage means, coupled to an internal address bus, including a first and second registers for storing addresses of shortwords in the first and second storage locations of said shortword memory means, respectively;
- internal address processing means for passing addresses therefrom to said system address bus, the internal address processing means comprising:
- a multiplexer with its two data inputs coupled to said internal address bus and fed from the internal address storage means with said shortword addresses, said multiplexer is controlled by a bit from the internal address storage means.
Priority Claims (1)
Number |
Date |
Country |
Kind |
922813 |
Nov 1992 |
IEX |
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Parent Case Info
This application is a continuation of application Ser. No. 08/130,327, filed Oct. 1, 1993, now abandoned.
US Referenced Citations (7)
Non-Patent Literature Citations (1)
Entry |
Dictionary of Computers, Information Processing & Telecommunications 2nd Edition, Jerry M. Rosenberg, John Wiley & Sons, New York 1984. |
Continuations (1)
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Number |
Date |
Country |
Parent |
130327 |
Oct 1993 |
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