Claims
- 1. A data processor comprising:a serial interface unit including a control signal terminal and a data input/output terminal; a memory unit connected to the serial interface unit and having a first area and a second area; and a processing unit; wherein when said serial interface unit receives a first control request signal at said control signal terminal, said serial interface unit receives a first program for debugging executed by the processing unit from said data input/output terminal, wherein said memory unit stores said first program to said second area and stores a second program which is to be subjected to a debugging operation by the first program to said first area, and wherein said processing unit branches a first predetermined address in the first area corresponding to receiving a second signal from said serial interface unit.
- 2. A data processor according to claim 1 further comprising:an interrupt control unit connected to said serial interface unit and said processing unit; wherein said interrupt control unit sends an interrupt request signal to said processing unit when said processing unit executes a second predetermined address in said first area in said memory unit or said serial interface unit receives a third control request signal; wherein said processing unit branches a third predetermined address in said second area in said memory unit, said processing unit executes said first program and sends predetermined data to said serial interface unit; and wherein said serial interface unit outputs said predetermined data to said data input/output terminal.
- 3. A data processor according to claim 1, wherein the second data is received from the data input/output terminal of said serial interface unit after receiving the first program and is then sent from the serial interface unit to the first area in the memory unit.
- 4. A data processing system comprising:a control unit; a data processor including: a serial interface unit for connecting to said control unit and having a control signal terminal and a data input/output terminal, a processing unit, and a memory unit including a first area and a second area; wherein said serial interface unit receives a first control signal at said control signal terminal from said control unit, receives first data corresponding to a first program at said data input/output terminal, the first program being used for debugging, and sends said first data to said second area in the memory unit; wherein said memory unit stores said first data and stores second data after storing said first data, said second data being executable and usable by the processing unit; wherein said processing unit executes said second data and stores a third data to said memory unit controlled by said first data; and wherein said serial interface unit receives a second control signal from said control unit to said control signal terminal, receives said third data from said memory unit and sends said third data from said data input/output terminal to said control unit.
Priority Claims (1)
Number |
Date |
Country |
Kind |
8-138111 |
May 1996 |
JP |
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Parent Case Info
This is a continuation application of U.S. Ser. No. 08/864,970, filed May 29, 1997 now U.S. Pat. No. 5,961,641.
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Continuations (1)
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Number |
Date |
Country |
Parent |
08/864970 |
May 1997 |
US |
Child |
09/335693 |
|
US |