Claims
- 1. A data processor, comprising:
- paired data transmission paths, each of the data transmission paths having at least one data holding mechanism in a plurality of stages controllable by a control circuit according to a handshaking transfer control;
- a function portion for processing authorized data from said paired data transmission paths; and
- processing arbitrating means for determining authorization and inhibition of processing by said function portion of data from said paired data transmission paths in accordance with an order of generation of a processing request such that there is no memory access contention in response to processing requests generated in parallel, thereby allowing arbitration for a plurality of processing requests generated asynchronously and in parallel such that there is no contention of processing, said processing arbitrating means including,
- state storing means for storing and determining sequential generation of processing requests from at least one of two different data holding mechanisms of a same one of said paired data transmission paths and two different data holding mechanisms of different ones of said paired data transmission paths, and
- authorization output means for outputting a signal indicating authorization of access of said function portion to each of said data holding mechanisms, sequentially, based upon the sequential determination of processing requests by said state storing means, and for outputting a signal inhibiting access of said function portion to each other of said data holding mechanisms.
Priority Claims (5)
Number |
Date |
Country |
Kind |
62-265734 |
Oct 1987 |
JPX |
|
62-265735 |
Oct 1987 |
JPX |
|
62-265736 |
Oct 1987 |
JPX |
|
62-265737 |
Oct 1987 |
JPX |
|
62-265741 |
Oct 1987 |
JPX |
|
Parent Case Info
This application is a continuation of application Ser. No. 07/922,746, filed on Jul. 31, 1992, now abandoned, which is a Rule 1.60 divisional of Ser. No. 07/779,805, filed Oct. 21, 1991, now the U.S. Pat. No. 5,317,756, which is a Rule 1.60 divisional of Ser. No. 07/260,061, now the U.S. Pat. No. 5,113,339, filed on Oct. 20, 1988.
US Referenced Citations (15)
Non-Patent Literature Citations (2)
Entry |
Technical Report of the Institute of Electronic and Communication Engineers of Japan (1983) SSD 83-78, pp. 45-52. |
Article entitled "A Hardware Pattern Matching Algorithn On a data Flow", Pramanik et al., The Computer Journal, vol. 28, No. 3, 1985. |
Divisions (2)
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Number |
Date |
Country |
Parent |
779805 |
Oct 1991 |
|
Parent |
260061 |
Oct 1988 |
|
Continuations (1)
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Number |
Date |
Country |
Parent |
922746 |
Jul 1992 |
|