Garner et al. "The Scalable Processor Architecture (SPARC)" IEEE 1988, pp. 278-283. |
Halstead, Jr. et al. "MASA: A Multi-Threaded Processor Architecture for Parallel Symbolic Computing" IEEE 1988, pp. 443-451. |
Miller, D. R., et al. "Exploiting Large Register Sets," Microprocessors and Microsystems, vol. 14, No. 6, Jul./Aug. 1990, pp. 333-340 (English). |
Dehnert, James C., et al. "Overlapped Loop Support in the Cydra 5," Computer Architecture News, vol. 17, No. 2, Apr. 1989, pp. 26-38. (English). |
Hennessy, J. L. and D. A. Patterson, Computer Architecture: A Quantitative Approach, Morgan Kaufmann Publishers, Inc., 1990, pp. 314-318 and 450-454. (in English) (items 2 and 3 on the Information Disclosure Statement). |