Claims
- 1. A store queue for use in a data processor with a memory cache, the memory cache storing a subset of data stored in a memory storage system, the data processor executing a plurality of store instructions, each one of the plurality of store instructions writing one of a plurality of data to a location in the memory storage system, the store queue comprising:
- a write first-in-first-out ("FIFO") queue comprising a plurality of entries, each one of the plurality of entries storing one of a plurality of store instructions executed by the data processor;
- means for maintaining a valid state or an invalid state of each one of the plurality of the entries; and
- control circuitry coupled to the write FIFO queue, the control circuitry comprising a first pointer, a second pointer, and a third pointer, the first pointer, the second pointer, and the third pointer indexing an entry in the write FIFO queue,
- the control circuitry storing each one of the plurality of store instructions in the entry indexed by the first pointer, the control circuitry incrementing the first pointer responsive to storing each one of the plurality of store instructions in the write FIFO queue,
- the control circuitry incrementing the second pointer responsive to presenting the one of the plurality of store instructions stored in the one of the plurality of entries indexed by the second pointer to the memory cache, the control circuitry invalidating the one of the plurality of entries indexed by the second pointer if the data accessed is present in the memory cache, the control circuitry continuing to present ones of the plurality of store instructions to the memory cache after a miss to the memory cache,
- the control circuitry incrementing the third pointer responsive (1) to presenting the one of the plurality of store instructions stored in the one of the plurality of entries indexed by the third pointer to the memory system, or (2) to determining that the one of the plurality of store instructions stored in the one of the plurality of entries indexed by the third pointer is in the invalid state and thereby not presenting the one to the memory system.
- 2. The store queue of claim 1 further comprising:
- a read first-in-first-out ("FIFO") queue comprising a plurality of entries, each one of the plurality of entries storing one of a plurality of load instructions; and
- wherein the control circuitry further comprises a head pointer and a tail pointer indexing an entry in the read FIFO queue, the control circuitry storing each one of the plurality of load instructions in the entry indexed by the tail pointer, the control circuitry incrementing the tail pointer responsive to storing each one of the plurality of load instructions, and the control circuitry incrementing the head pointer responsive to presenting the one of the plurality of load instructions stored in the one of the plurality of entries indexed by the head pointer to the memory cache.
- 3. The store queue of claim 2 wherein the control circuitry further comprises a fourth pointer indexing an entry in the FIFO queue, the control circuitry (1) storing data associated with one of the plurality of store instructions in the entry indexed by the fourth pointer and (2) incrementing the fourth pointer.
- 4. The store queue of claim 3 wherein the control circuitry stores data associated with one of the plurality of store instructions in the entry indexed by the fourth pointer when all instructions preceding the store instruction indexed by the fourth pointer have completed.
- 5. The store queue of claim, 1 wherein the control circuitry further comprises a fourth pointer indexing an entry in the FIFO queue, the control circuitry (1) storing data associated with one of the plurality of store instructions in the entry indexed by the fourth pointer and (2) incrementing the fourth pointer.
- 6. The store queue of claim 5 wherein the control circuitry stores data associated with one of the plurality of store instructions in the entry indexed by the fourth pointer when all instructions preceding the store instruction indexed by the fourth pointer have completed.
Parent Case Info
This application is a continuation of prior application Ser. No. 08/252,473, filed on Jun. 1, 1994, entitled "DATA PROCESSOR WITH UNIFIED STORE QUEUE AND METHOD OF OPERATION", (original title) now abandoned.
US Referenced Citations (13)
Continuations (1)
|
Number |
Date |
Country |
Parent |
252473 |
Jun 1994 |
|