Not Applicable
Not Applicable
Not Applicable
1. Field of the Invention
The present invention relates to an optimal configuration for a compression/expansion processing memory and recording/reproduction buffer memory associated with a recording apparatus or a reproduction apparatus that compresses data, and records the data on a recording medium, and that can reproduce and expand data from the recording medium. The present invention further provides a method for carrying out such operations.
2. Description of the Related Art
Apparatus for compressing and recording data to a recording medium include audio recorders, electronic still cameras, and video cameras. Because these devices are small, light, and can record information for a long period of time, they are becoming widely disseminated.
A problem with portable devices is that the devices become unable to record to or reproduce from a recording medium because of vibration or the like. Use of a recording medium which requires tracking control, such as a hard disk drive or optical disc as the recording medium, is particularly affected: tracking is thrown off due to vibrations and the device easily enters a state where recording and reproduction are not possible. One approach for resolving this problem is disclosed in Japanese Patent Laid-open Publication No. H08-307811, wherein recording data are temporarily placed in memory, and then read from memory and recorded to the recording medium. When vibrations are detected, the reading from memory and recording to the recording medium are stopped. In addition, a recording and reproduction apparatus requires memory for holding the intermediate data necessary in compression and expansion processing. A related technology is disclosed in Japanese Patent Laid-open Publication No. H11-146246, wherein the intermediate data for compression processing and the data to be recorded to the recording medium are both held in one memory.
In the above conventional art, technology wherein one memory holds both the intermediate data for compression processing and the data for recording is disclosed, however the efficient, cost-effective allocation of memory capacity is not provided. In effect, the allocation of a memory of fixed capacity to each of the intermediate data and recording data worsens cost-effectiveness in relation to capacity. The conventional art concerns an electronic still camera, and has the object of not losing a shot, but little consideration is given to memory capacity becoming insufficient and image quality deteriorating.
The present invention provides a recording or reproduction apparatus with superior cost-effectiveness and an efficient configuration of the memory for holding data for recording and reproduction processing. To achieve this functionality, a data recording apparatus according to the present invention comprises: a data compressor which compresses input data; a data recorder which records compressed data to a recording medium; a memory which holds first data which undergoes compression, and second data, which is recorded to the recording medium; and a memory controller which controls the size of the regions in the memory for holding the first data and second data.
To compress input data, the data compressor comprises a standard compression mode for compression processing using a plurality of intermediate data, and a simple compression mode for performing the compression process using part of the intermediate data. The memory controller sets the first data region in memory according to the mode of the data compressor and sets the remaining region of the memory as the second data region. When the data compressor is operating in the standard compression mode and the data recorder becomes unable to record, the data compressor automatically switches to the simple compression mode.
The standard compression mode is a high-image-quality processing mode for performing noise reduction processing or dynamic range expansion processing using the correlation with image data of the consecutive video frames or consecutive video fields, for example. The simple compression mode is a mode which omits the correlation with image data of consecutive video frames or video fields.
A data reproduction apparatus according to a preferred embodiment of the present invention includes: a data reproducer which reproduces compressed data from a recording medium; a data expander which expands reproduced data; memory which holds first data reproduced from the recording medium and second data which undergoes expansion processing; and a memory controller which controls the size of the region in memory for holding the first and second data. Also, in the data recording method relating to the present invention, first data, which undergo compression, and second data, which are recorded to the recording medium, are held in memory, and the sizes of the regions in memory for holding the first and second data are controlled according to the recording data quality level. Alternatively, the sizes of the regions in memory for holding the first and second data are controlled according to whether recording is possible. Furthermore, in the data reproduction method relating to the present invention, first data, which are reproduced from the recording medium, and second data, which undergo expansion, are held in memory, and the sizes of the regions in memory for holding the first and second data are controlled according to the reproduction data quality level. Alternatively, the sizes of the regions in memory for holding the first and second data are controlled according to whether reproduction is possible.
These and other features and advantages of the present invention will become readily apparent from the following detailed description taken in conjunction with the accompanying drawings, wherein:
The preferred embodiments of the present invention are explained below with reference to the drawings.
This circuit includes the following: a camera processing circuit 5a and a display processing circuit 5b, a compression processing circuit 6a, an expansion processing circuit 6b, a recording control circuit 7a, a reproduction control circuit 7b, a data time division multiplexing circuit 8, an address generating circuit 9 for camera processing and display processing, an address generating circuit 10 for compression and expansion processing, an address generating circuit 11 for recording and reproduction control, an address time division multiplexing circuit 12, a ring buffer minimum address setting circuit 13, a ring buffer maximum address setting circuit 14, and a compression and expansion mode switching circuit 15.
The operation of the apparatus shown in
Compression processing circuit 6a compresses the image data, for which preprocessing is completed, using an encoding scheme such as MPEG2. In MPEG2, it is necessary to perform a reordering process for the image to undergo bidirectional prediction, and to hold the reference pictures used in prediction]. Image data are held as intermediate data in memory 1 and used for this process.
Recording control circuit 7a temporarily stores compressed data in memory 1 and intermittently reads and sends the data to disk drive 3. The data sent are recorded on the disk which is the recording medium in disk drive 3. When the disk drive 3 cannot record because of factors such as vibrations, the reading and sending of data from memory 1 are stopped.
The time division multiplexing circuit 8 shown in
Address generating circuit 11 for recording/reproduction control generates an address between the address shown by the ring buffer minimum address setting circuit 13 and the address shown by the ring buffer maximum address setting circuit 14. The address shown by ring buffer minimum address setting circuit 13 is the primary address 22a of the memory region, excluding compression/expansion image memory region 20 and FNR, WDR image memory region 21. The address shown by read buffer maximum address setting circuit 14 matches the address 22e of memory 1.
The switching of the compression mode is explained next.
The switching of the compression mode is carried out according to a command from compression/expansion mode changing circuit 15 shown in
The automatic switching of the compression mode is explained next. Address generating circuit 11 for recording/reproduction control calculates how much data is currently stored in recording/reproduction ring buffer region 22. If the disk drive remains in a state where recording is not possible for a long period as an effect of vibrations or the like continuing for a long time, the amount of data stored in recording/reproduction ring buffer region 22 increases and the memory region quickly becomes full. When this type of situation arises in the standard compression mode shown in
Another embodiment of compression mode switching is explained next.
Moreover,
By switching between the states in
The operation of the apparatus shown in
Display processing circuit 5b converts expanded image data to a video signal in a format corresponding to display 4. At this time, image post-processing such as noise reduction using the correlation with the image data from the preceding frame or the preceding field is carried out. Image data of one frame or one field is stored in memory 1 and used for this purpose. Display 4 displays the video signal after image processing.
The address map in memory 1 is now as shown in
Expansion mode switching is explained next. The address map for the simple expansion mode is as shown in
As a result, the memory capacity for temporarily holding reproduction data can be expanded to the maximum size according to the picture quality level of the reproduction data. Memory can therefore be used efficiently and the situation wherein data quality is sacrificed due to a lack of memory can be avoided.
The automatic switching of the expansion mode is explained next. Address generating circuit 11 for recording/reproduction control calculates how much data is currently stored in recording/reproduction ring buffer region 22. When disk drive 3 remains in a state where reproduction is not possible for a long period as an effect of vibrations or the like continuing for a long time, the amount of data stored in recording/reproduction ring buffer region 22 decreases and the memory region is quickly emptied. When this type of situation arises in the standard expansion mode shown in
This circuit includes the following: video preprocessing circuit 5c, compression processing circuit 6a, recording control circuit 7a, data time division multiplexing circuit 8, address generating circuit 9 for video preprocessing, address generating circuit 10 for compression processing, address generating circuit 11 for recording control, address time division multiplexing circuit 12, ring buffer minimum address setting circuit 13, ring buffer maximum address setting circuit 14, and compression mode changing circuit 15a.
The operation of the apparatus shown in
Compression processing circuit 6a compresses the image data, for which preprocessing is completed, using an encoding scheme such as MPEG2. In MPEG2, it is necessary to perform a reordering process for the image (picture) to undergo bidirectional prediction, and to hold reference pictures used in prediction. Image data are held as intermediate data in memory 1 and used for this reordering process.
Recording control circuit 7a temporarily stores compressed data in memory 1 and intermittently reads and sends the data to disk drive 3. The data sent are recorded to the disk which is the recording medium in disk drive 3. When disk drive 3 cannot record because of factors such as vibrations, the reading and sending of data from memory 1 are stopped.
The address map in memory 1 has the space allocation shown in
The time division multiplexing circuit 8 shown in
Address generating circuit 11 for recording control generates an address between the address shown by ring buffer minimum address setting circuit 13 and the address shown by ring buffer maximum address setting circuit 14. The address shown by ring buffer minimum address setting circuit 13 is the primary address 22a of the region, excluding compression image memory region 20 and the FNR image memory region 21. The address shown by read buffer maximum address setting circuit 14 matches the address 22e of memory 1.
Compression mode switching is explained next. The address map in memory 1 is as shown in
The switching of the compression mode is carried out according to a command from compression mode changing circuit 15a shown in
As a result, the memory capacity for temporarily holding recording data can be expanded to the maximum level according to the quality level (picture quality) of the recording data. Memory can therefore be used efficiently and the situation wherein data quality is sacrificed due to a lack of memory can be avoided.
The automatic switching of the compression mode is explained next. Address generating circuit 11 for recording control calculates how much data is currently stored in recording ring buffer region 22. When the disk drive remains in a state where recording is not possible for a long period as an effect of vibrations or the like continuing for a long time, the amount of data stored in recording ring buffer region 22 increases and the memory region quickly becomes full. When this type of situation arises in the standard compression mode shown in
Although not shown, a switch to manually choose whether to perform this switching automatically can be provided and the user can employ this as well. Furthermore, a display portion showing whether the current operating mode is the standard mode or simple mode also can be provided.
Another embodiment for compression mode switching is explained next.
Meanwhile,
By switching between the states in
This circuit includes the following: display processing circuit 5b, expansion processing circuit 6b, reproduction control circuit 7b, data time division multiplexing circuit 8, address generating circuit 9 for display processing, address generating circuit 10 for expansion processing, address generating circuit 11 for reproduction control, address time division multiplexing circuit 12, ring buffer minimum address setting circuit 13, ring buffer maximum address setting circuit 14, and expansion mode changing circuit 15b.
The operation of the apparatus shown in
Display processing circuit 5b converts expanded image data to a video signal in a format corresponding to display 4. At this time, image post-processing such as noise reduction, using the correlation with the image data from the previous frame or the previous field, is carried out. Image data of one frame or one field is stored in memory 1 and used for this purpose. Display 4 displays the video signal after image processing.
The address map in memory 1 has the space allocation shown in
Expansion mode switching is explained next. The address map for the simple expansion mode is as shown in
As a result, the memory capacity for temporarily holding reproduction data can be expanded to the maximum level according to the quality level (picture quality) of the reproduction data. Memory can therefore be used efficiently and the situation wherein data quality is sacrificed due to a lack of memory can be avoided.
The automatic switching of the expansion mode is explained next. Address generating circuit 11 for reproduction control calculates how much data is currently stored in reproduction ring buffer region 22. When disk drive 3 remains in a state where reproduction is not possible for a long period as an effect of vibrations or the like continuing for a long time, the amount of data stored in reproduction ring buffer region 22 decreases and the memory region is quickly emptied. When this type of situation arises in the standard expansion mode shown in
In addition, a switch to manually chose whether to perform this switching automatically can be provided and the user can employ this as well. Furthermore, a display portion showing whether the current operating mode is the standard mode or simple mode can also be provided. An anomaly in the reproduction state can be identified by looking at the data occupancy in reproduction ring buffer region 22, or by looking at how often data are not returned from disk drive 3 because of reproduction is impossible.
In the embodiments discussed above, audio signals were not described. The compression of audio data, however, and the multiplexing of compressed image data and compressed audio data are performed by compression/expansion processing circuit 6a, 6b, and the multiplexed data are stored in recording /reproduction ring buffer region 22. As a result, images with sound can be recorded in exactly the same way as images without sound. During reproduction, the multiplexed data are stored in recording/reproduction ring buffer region 22 and the separation of compressed image data and compressed audio data, and the expansion of audio data are carried out in compression/expansion processing circuit 6a, 6b. As a result, images with sound can be reproduced. In the above-mentioned embodiments, memory 1 for storing compressed (or expanded) data and recording (or reproduction) data is a single shared memory, but the present invention can also apply when there are multiple memories. Furthermore, the present invention can also be applied to an imaging apparatus containing an imaging device or display, as well as to a recording or reproduction apparatus.
With the present invention, it becomes possible to provide a recording or reproduction apparatus with superior cost-effectiveness and an efficient configuration of the regions in memory for storing data for recording/reproduction processing.
The invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. The present embodiment is therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being defined by the appended claims rather than by the foregoing description and the range of equivalency of the claims are therefore intended to be included in that delineation.
Number | Date | Country | Kind |
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2002-004051 | Jan 2002 | JP | national |
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Number | Date | Country | |
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20030133542 A1 | Jul 2003 | US |