Patent Application
20100260033
Embodiments of the present invention are directed to erasable MEMS seek-scan probe (SSP) memories and, more particularly, to ferroelectric films used as storage mediums in such devices.
Conventional solid state memories employ microelectronic circuit elements for each memory bit. Since one or more electronic circuit elements are required for each memory bit (e.g., one to four transistors per bit), these devices can consume considerable chip “real estate” to store a bit of information, which limits the density of a memory chip. The primary memory element in these devices is typically a floating gate field effect transistor device that holds a charge on the gate of field effect transistor to store each memory bit. Typical memory applications include dynamic random access memory (DRAM), static random access memory (SRAM), erasable programmable read only memory (EPROM), and electrically erasable programmable read only memory (EEPROM).
A different type of solid state memory commonly known as a phase-change memory uses a phase-change material as the data storage mechanism and offers significant advantages in both cost and performance over conventional memories based on charge storage. Phase change memories use phase change materials—in other words, materials that can be electrically switched between two or more phases having different electrical characteristics such as resistance. One type of memory element, for example, uses a phase change material that can be electrically switched between a generally amorphous phase and a generally crystalline local order, or between different detectable phases of local order across the entire spectrum between completely amorphous and completely crystalline phases.
The phase-change memory can be written to, and read from, by applying current pulses that have the appropriate magnitude and duration and that cause the needed voltages across and current through the volume of phase-change material. A selected cell in a phase-change memory can be programmed into a selected state by raising a cell voltage and a cell current for the selected cell to programming threshold levels that are characteristic of the phase-change material. The voltage and current are then typically lowered to quiescent levels (e.g. essentially zero voltage and current) that are below the programming threshold levels of the phase-change material. This process can be performed by the application of, for example, a reset pulse and a set pulse which can program the cell into two different logic states. In both of these pulses, the cell voltage and cell current are caused to rise at least as high as certain threshold voltage and current levels needed to program the cell.
Next, to read the programmed cell, a read pulse can be applied to measure the relative resistance of the cell material, without changing its phase. Thus, the read pulse typically provides a much smaller magnitude of cell current and cell voltage than either the reset pulse or the set pulse.
These electrical memory devices typically do not use field effect transistor devices, but comprise, in the electrical context, a monolithic body of thin film material. As a result, very little chip real estate is required to store a bit of information, thereby providing for inherently high density memory chips. The phase change materials are also truly non-volatile in that, when set in either a crystalline, semi-crystalline, amorphous, or semi-amorphous phase representing a resistance value, that value is retained until reset as that value represents a physical phase of the material (e.g., crystalline or amorphous).
The foregoing and a better understanding of the present invention may become apparent from the following detailed description of arrangements and example embodiments and the claims when read in connection with the accompanying drawings, all forming a part of the disclosure of this invention. While the foregoing and following written and illustrated disclosure focuses on disclosing arrangements and example embodiments of the invention, it should be clearly understood that the same is by way of illustration and example only and the invention is not limited thereto.
Reference throughout this specification to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, the appearances of the phrases “in one embodiment” or “in an embodiment” in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.
Data storage devices based on scanning probe microscopy (SPM) techniques have been widely studied as future ultra-high density (>1 Tbit/in2) systems. Ferroelectric thin films have been proposed as a promising recording media by controlling the spontaneous polarization directions corresponding to the data bits. The recording density could be ultra high because the thickness of 180° domain wall in ferroelectric material is in few lattices (1-2 nm). However, the domain stability, such as data retention and imprint, is a challenge for this material to be used in real products.
Experimentally, we have observed that there is an internal build-in bias field (BBF) in as-grown ferroelectric thin films, such as PZT (Lead-Zirconate-Titanate). Experimentation and simulation show that the data retention (or imprint) of written nano-domains are degraded by the built-in-bias field (BBF). For example, when down polarization domains are written in PZT films with as-grown positive BBF (up polarization), the written down domains shrink in size, driven by the BBF. In addition, the shrinking rate increases with increasing BBF. This phenomenon presents the retention (or imprint) problem for the real world application. Embodiments described herein involve methods to minimize the BBF of as-grown PZT films by controlling the composition and strain gradient in the media film.
Referring now to
As far as the probable origins of BBF, experimentally its been observed that there is a built-in-bias field (BBF) of the as-grown ferroelectric thin films, such as PZT. The origins of the BFF may be coming from a number of sources. For example from trapped charges at the interfaces or within the films. BBF may also come from aligned defect dipoles or from asymmetric electrodes (without top electrode) and therefore asymmetric electrical boundary conditions as shown in
For the first two causes noted above, trapped charges and defect dipoles, they may be minimized by optimized ferroelectric film growth. However, for the asymmetric electrodes dues to asymmetric film stack of the device, this may not me resolved by optimizing the film growth process.
Embodiments of the invention comprise using composition or other gradients through the film thickness to compensate for bias field due to asymmetric electrodes. Referring to
The PZT ferroelectric film layer 506 may comprise a composition gradient and/or strain gradient which may be used to create a polarization gradient. This has been discussed in, for example in Misirlioglu et al, Applied Physics Letters, 86, 192910 (2005) and in Journal Applied Physics, 76, 4305 (1994), both herein incorporated by reference. By growing the ferroelectric films with stress and composition gradients this generates polarization gradients (Pfg, internal field), which may cancel the bias field due to the asymmetric electrodes (Pae). Thus, the retention (or imprint) may be improved with minimized BBF.
The above description of illustrated embodiments of the invention, including what is described in the Abstract, is not intended to be exhaustive or to limit the invention to the precise forms disclosed. While specific embodiments of, and examples for, the invention are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the invention, as those skilled in the relevant art will recognize.
These modifications can be made to the invention in light of the above detailed description. The terms used in the following claims should not be construed to limit the invention to the specific embodiments disclosed in the specification and the claims. Rather, the scope of the invention is to be determined entirely by the following claims, which are to be construed in accordance with established doctrines of claim interpretation.
