Patent Application
20080170685
Embodiments of the present invention relate generally to memory storage devices; and, more particularly embodiments of the present invention relate to data scrambling circuits of memory storage devices.
As is known, many varieties of memory storage devices (e.g. disk drives), such as magnetic disk drives are used to provide data storage for a host device, either directly, or through a network such as a storage area network (SAN) or network attached storage (NAS). Typical host devices include stand alone computer systems such as a desktop or laptop computer, enterprise storage devices such as servers, storage arrays such as a redundant array of independent disks (RAID) arrays, storage routers, storage switches and storage directors, and other consumer devices such as video game systems and digital video recorders. These devices provide high storage capacity in a cost effective manner.
The structure and operation of hard disk drives is generally known. Hard disk drives include, generally, a case, a hard disk having magnetically alterable properties, and a read/write mechanism including Read/Write (RW) heads operable to write data to the hard disk by locally alerting the magnetic properties of the hard disk and to read data from the hard disk by reading local magnetic properties of the hard disk. The hard disk may include multiple platters, each platter being a planar disk.
All information stored on the hard disk is recorded in tracks, which are concentric circles organized on the surface of the platters.
Since each track typically holds many thousands of bytes of data, the tracks are further divided into smaller units called sectors. This reduces the amount of space wasted by small files. Each sector holds 512 bytes of user data, plus as many as a few dozen additional bytes used for internal drive control and for error detection and correction.
Within such hard disk drives (HDDs), disk drive controllers control the various processes associated with the read/write of data to the physical media. These disk drive controllers may comprise digital logic devices that include both a processor and memory device wherein the memory device is separate from the digital logic device. This memory may serve as the read write (RW) buffer in a HDD controller. In this architecture data is written to and read from the external memory device. This requires drivers to drive the external pins that are used to couple the digital logic device to the memory device. As a large number of memory bits may be driven simultaneously, the switching of the memory bits can result in high instantaneous currents which may create electromagnetic interference (EMI) problems associated with these current spikes. These current spikes and EMI problems may be exacerbated by the non-random nature of much of the data written to and read from the memory device. The repetitive data simultaneously changing may result in an overall amplification of the EMI signature at high frequencies.
During a write, the interface circuit switching may result in increased EMI signatures associated with the write. Similarly on a read, the pins of a memory device, when the data is patterned, may result in increased EMI signature as well. This simultaneous switching in addition to creating an EMI problem also may draw a large amount of current instantaneously. These may result in a ground bounce or a voltage droop. In addition to a current or EMI problem, security problem exists wherein it may be possible to read the data from the pins of either the digital logic device used to drive the external memory device or the memory device itself. As the amount and frequency of data read and written to memory increase, the potential for the above identified problems (i.e. EMI, current spikes and security risks) increase.
Embodiments of the present invention are directed to systems and methods that are further described in the following description and claims. Advantages and features of embodiments of the present invention may become apparent from the description, accompanying drawings and claims.
For a more complete understanding of the present invention and the advantages thereof, reference is now made to the following description taken in conjunction with the accompanying drawings in which like reference numerals indicate like features and wherein:
Preferred embodiments of the present invention are illustrated in the FIGs., like numerals being used to refer to like and corresponding parts of the various drawings.
Embodiments of the present invention provide a data scrambling circuit. The data scrambling circuit includes an integrated circuit having a digital logic device and an interface circuit coupled to the digital logic device. Also included is an external memory coupled to output pins on the interface circuit. The digital logic device communicates patterned data to the interface circuit. The interface circuit then scrambles the patterned data to produce a pseudo random output to be stored within the external memory and unscrambled a pseudo random signal from the external memory to produce unscrambled data to be read by the digital logic device.
Disk drive unit 100 further includes one or more read/write heads 104 that are coupled to arm 106 that is moved by actuator 108 over the surface of the disk 102 either by translation, rotation or both. A disk controller 130 is included for controlling the read and write operations to and from the drive, for controlling the speed of the servo motor and the motion of actuator 108, and for providing an interface to and from the host device. Embedded trace systems within disk controller 130 will be discussed with reference to
Disk controller 130 further includes a processing module 132 and memory module 134. Processing module 132 can be implemented using one or more microprocessors, micro-controllers, digital signal processors (DSPs), microcomputers, central processing units (CPUs), field programmable gate arrays (FPGAs), programmable logic devices (PLAs), state machines, logic circuits, analog circuits, digital circuits, and/or any devices that manipulates signal (analog and/or digital) based on operational instructions that are stored in memory module 134. When processing module 132 is implemented with two or more devices, each device can perform the same steps, processes or functions in order to provide fault tolerance or redundancy. Alternatively, the function, steps and processes performed by processing module 132 can be split between different devices to provide greater computational speed and/or efficiency.
Memory module 134 may be a single memory device or a plurality of memory devices. Such a memory device may be a read-only memory (ROM), random access memory (RAM), volatile memory, non-volatile memory, static random access memory (SRAM), dynamic random access memory (DRAM), flash memory, cache memory, and/or any device that stores digital information. Note that when the processing module 132 implements one or more of its functions via a state machine, analog circuitry, digital circuitry, and/or logic circuitry, the memory module 134 storing the corresponding operational instructions may be embedded within, or external to, the circuitry comprising the state machine, analog circuitry, digital circuitry, and/or logic circuitry. Further note that, the memory module 134 stores, and the processing module 132 executes, operational instructions that can correspond to one or more of the steps or a process, method and/or function illustrated herein.
Disk controller 130 includes a plurality of modules, in particular, device controllers 105, processing timing generator 110, processing module 132, memory module 134, write channel 120, read channel 140, disk formatter 125, and host interface 150 that are interconnected via bus 136. Each of these modules can be implemented in hardware, firmware, software or a combination thereof, in accordance with the broad scope of the present invention. While the particular bus architecture is shown in
In one possible embodiment, one or more (possible all) modules of disk controller 130 are implemented as embedded systems within a system on a chip (SOC) integrated circuit. In such a possible embodiment, this SOC integrated circuit includes a digital portion that can include additional modules such as protocol converters, linear block code encoding and decoding modules, etc., and an analog portion that includes device controllers 105 and optionally additional modules, such as a power supply, etc. In an alternative embodiment, the various functions and features of disk controller 130 are implemented in a plurality of integrated circuit devices that communicate and combine to perform the functionality of disk controller 130. To monitor the operations of these modules, embedded trace systems may be implemented within the integrated circuit.
In a possible embodiment, wireless communication device 53 is capable of communicating via a wireless telephone network such as a cellular, personal communications service (PCS), general packet radio service (GPRS), global system for mobile communications (GSM), and integrated digital enhanced network (iDEN) or other wireless communications network capable of sending and receiving telephone calls. Further, wireless communication device 53 is capable of communicating via the Internet to access email, download content, access websites, and provide steaming audio and/or video programming. In this fashion, wireless communication device 53 can place and receive telephone calls, text messages such as emails, short message service (SMS) messages, pages and other data messages that can include attachments such as documents, audio files, video files, images and other graphics.
A data scrambling circuit is provided by embodiments of the present invention. The data scrambling circuit provides an integrated circuit having a digital logic device and an interface circuit coupled to the digital logic device. Also included is an external memory coupled to output pins on the interface circuit. The digital logic device communicates patterned data to the interface circuit. The interface circuit then scrambles the patterned data to produce a pseudo random output to be stored within the external memory and unscrambles a pseudo random signal from the external memory to produce unscrambled data to be read by the digital logic device.
Such a data scrambling circuit may be employed where large amounts of high frequency patterned data are written to and from external memory such as within a hard disk controller or a graphics controller. Data scrambling circuit 150 includes a digital logic device 152, interface circuitry 154 and memory external memory device 156. The digital logic device provides addresses with which to read and write patterned data such as that seen in a hard disk drive controller or graphics controller to the interface circuitry which will be described in further detail with reference to
A digital logic device has a set of pins 158 to connect to an external memory device such as a DRAM and SRAM. The data scrambling circuit exists in the logic device on the data path between the internal interface circuit and the pins. Internal functions request memory read and write accesses through the interface circuit. Each access request can be for a single location or a sequential set of locations. The (beginning) address of the access is presented to the data scrambling circuit for a seeding function.
In the case of a read, the digital logic device again will specify address 172 of the pseudo random signal to be read from external memory device 156. Interface logic will read pseudo random signal 176 from external memory using address 172. Again, a pseudo random signal is seen on the pins 158 which again results in reduced EMI concerns, security concerns, voltage droop and current spikes. The interface logic will output the pseudo random signal 178 to modify circuitry 166 which may use the pseudo random counter generated using address 172 to produce unscrambled data 180 which is then read by the digital logic device.
Data scrambling circuit 150 reduces electromagnetic interference (EMI) generated by an external memory device 156 interfaced to digital logic device 152. The scrambling circuit uses each memory access (beginning) address as a seed for an effective yet repeatable scrambling function.
The (beginning) address of the access to/from the memory device is used as a seed into the scrambling function. The function output is then used to modify write data before it reaches the interface outputs (and thus the memory device). Each data value within a set is modified by a new, distinct value from the scrambling function. The read data from the memory device is modified in a similar fashion by the same scrambling function with an inverse effect to obtain the un-scrambled data.
The scrambling function can be as simple or complex as desired by the system requirements. To effectively reduce EMI the data presented at the device pins should be close to random despite inherent fixed pattern-generated frequencies. A pseudo-random counter seeded by the address is the preferred implementation of the scrambling function. The counter output is XOR'ed with the data to perform the modification function for writes and reads.
Scrambling the data within the interface circuit may use a scrambling function to produce the pseudo random output. This scrambling function may be seeded using an address of data to the external memory. The scrambling function typically will produce a pseudo random counter which may be XOR'ed with the data to be written to external memory in order to produce the pseudo random output. Additionally the address of the data may be scrambled as well. This scrambling function may employ a cyclic redundancy check (CRC) algorithm or linear feedback shift register (LFSR) or other like means known to those having skill in the art to reduce a pseudo random output from a substantially patterned data.
An unscrambling function similar to the scramble function may be used to produce the unscrambled data from this pseudo random signal. This unscrambling function may be seeded using an address of the pseudo random signal within the external memory. This unscrambling function may produce a pseudo random encounter which may be XOR'ed with the pseudo random signal to produce the unscrambled data. This allows the pseudo random signal or output stored in an external memory such as DRAM or SRAM to be provided to the digital logic device with benefits as previously discussed.
In summary, the present invention provides a data scrambling circuit. The data scrambling circuit includes an integrated circuit having a digital logic device and an interface circuit coupled to the digital logic device. Also included is an external memory coupled to output pins on the interface circuit. The digital logic device communicates patterned data to the interface circuit. The interface circuit then scrambles the patterned data to produce a pseudo random output to be stored within the external memory and unscrambled a pseudo random signal from the external memory to produce unscrambled data to be read by the digital logic device.
As one of average skill in the art will appreciate, the term “substantially” or “approximately”, as may be used herein, provides an industry-accepted tolerance to its corresponding term. Such an industry-accepted tolerance ranges from less than one percent to twenty percent and corresponds to, but is not limited to, component values, integrated circuit process variations, temperature variations, rise and fall times, and/or thermal noise. As one of average skill in the art will further appreciate, the term “operably coupled”, as may be used herein, includes direct coupling and indirect coupling via another component, element, circuit, or module where, for indirect coupling, the intervening component, element, circuit, or module does not modify the information of a signal but may adjust its current level, voltage level, and/or power level. As one of average skill in the art will also appreciate, inferred coupling (i.e., where one element is coupled to another element by inference) includes direct and indirect coupling between two elements in the same manner as “operably coupled”. As one of average skill in the art will further appreciate, the term “compares favorably”, as may be used herein, indicates that a comparison between two or more elements, items, signals, etc., provides a desired relationship. For example, when the desired relationship is that signal 1 has a greater magnitude than signal 2, a favorable comparison may be achieved when the magnitude of signal 1 is greater than that of signal 2 or when the magnitude of signal 2 is less than that of signal 1.
Although the present invention is described in detail, it should be understood that various changes, substitutions and alterations can be made hereto without departing from the spirit and scope of the invention as described by the appended claims.
This application claims priority to and incorporates by reference in its entirety for all purposes U.S. Provisional Application No. 60/885,019 filed on 16 Jan. 2007 entitled “DATA SCRAMBLING CIRCUIT”.
| Number | Date | Country | |
|---|---|---|---|
| 60885019 | Jan 2007 | US |
