Patent Grant
11049469
The following disclosure relates to a data signal line drive circuit of a liquid crystal display device, and particularly relates to a data signal line drive circuit of a liquid crystal display device including memory circuits in pixel circuits.
In recent years, liquid crystal display devices provided with memory circuits in pixel circuits have been developed in order to reduce power consumption. Such a liquid crystal display device is referred to as “memory liquid crystal” or the like. In general, in the memory liquid crystal, one bit of data can be held for each pixel, and in a case where an image of the same content or an image with a little change is displayed for a long period of time, image display is performed by using the data held in the memory circuit. In the memory liquid crystal, once the data is written to the memory circuit, the contents of the data written to the memory circuit are then held until rewritten. Thus, little power is consumed in periods other than the periods before and after the contents of the image change. Therefore, low power consumption can be achieved by the memory liquid crystal.
Incidentally, a circuit that supplies a data signal to a pixel circuit in the memory liquid crystal is referred to as a “binary driver”.
The binary driver is constituted with a shift register 910 including 100 unit circuits 91 (1) to 91 (100), a first latch portion 920 constituted with 100 first latch circuits 92 (1) to 92 (100), and a second latch portion 930 constituted with 100 second latch circuits 93 (1) to 93 (100). Note that
Each of the first latch circuits 92 includes 16 unit latch circuits corresponding to the 16 source bus lines, respectively. Similarly, each of the second latch circuits 93 includes 16 unit latch circuits corresponding to the 16 source bus lines, respectively. The unit latch circuits employ D latch circuits, referred to as “pass-through latches”, “gated D latches” and the like. The unit latch circuit captures a data signal, based on an enable signal EN and outputs the captured data signal. Note that, hereinafter, a signal provided as an enable signal EN to the first latch circuit 92 is referred to as a “first latch signal”, and a signal provided as an enable signal EN to the second latch circuit 93 is referred to as a “second latch signal”.
Each of the unit circuits 91 in the shift register 910 operates based on a binary start pulse signal BSP and two-phased binary clock signals BCK and BCKB. The output signal LTEN from each of the unit circuits 91 is provided as a set signal S to the unit circuit 91 at the next stage, and is provided as the first latch signal described above to the corresponding first latch circuit 92. Each of the first latch circuits 92 captures a data signal DATA transmitted from the outside, based on the first latch signal, and outputs the captured data signal. Each of the second latch circuits 93 captures the data signal output from the corresponding first latch circuit 92, based on the second latch signal and outputs the captured data signal to a corresponding source bus line. Note that, as can be understood from
After the pulse generation of the binary start pulse signal BSP, in a case where the binary clock signal BCK rises first, the output signal LTEN (1) from the unit circuit 91 (1) at the first stage is set to the high level. As a result, the first latch circuit 92 (1) at the first stage captures the data signal DATA transmitted from the outside. Next, in a case where the binary clock signal BCKB rises, the output signal LTEN (2) from the unit circuit 91 (2) at the second stage is set to the high level. As a result, the first latch circuit 92 (2) at the second stage captures the data signal DATA transmitted from the outside. In this way, in each of the first latch circuits 92, the data signal DATA is captured based on the output signal LIEN from the corresponding unit circuit 91. Then, in a case where the output signal LTEN (100) from the unit circuit 91 (100) at the 100-th stage is set to the high level, the data signal DATA has been captured by all of the first latch circuits 92 (1) to 92 (100). In such a state, the second latch signal EN2 is set to the high level at the time point tx. As described above, this second latch signal EN2 is provided in common to all of the second latch circuits 93 (1) to 93 (100). In this way, the capturing of the data signal in all of the second latch circuits 93 (1) to 93 (100) is performed in unison. Then, the data signal SL is output in unison to all of the source bus lines. In this regard, the source bus lines are connected to the pixel circuits and the wiring line capacity is large, and a number of source bus lines are disposed in a display portion. Thus, by the data signals being output in unison to all the source bus lines, a large current flows, resulting in a voltage drop (drop in power supply voltage) (see a section labeled with the reference signs 98 and 99 in
A technique for reducing the effect of voltage drop as described above is disclosed in JP 2010-122509 A. Specifically, it is described that a delay circuit (see FIG. 3 and FIG. 5 of JP 2010-122509 A) is provided so as to generate time differences in the data capturing timing between a plurality of second latch groups in a case where data is captured by the plurality of second latch groups. However, it is difficult to generate a large time difference in data capturing timing by this technique. Thus, before the power supply returns from a voltage drop occurred due to capturing of data in a certain second latch group, capturing of data in a next second latch group may be performed in some cases. In this case, the voltage drop will occur again before the power supply returns, so the effect of reducing the effect of the voltage drop is less effective. Although it is possible to increase the time difference in data capturing timing by increasing the number of inverters that constitute the delay circuit, the increase in the number of inverters causes an increase in circuit size. As the number of inverters increases, the effect of process variation increases, which makes control difficult.
Therefore, an object of the following disclosure is to realize a binary driver (data signal line drive circuit) that can effectively reduce the effect of voltage drop while suppressing an increase in circuit size.
(1) A data signal line drive circuit according to some embodiments of the disclosure is a data signal line drive circuit including:
a shift register including a plurality of unit circuits connected in series;
a first latch portion including a plurality of first latch circuits configured to operate based on two power supply voltages; and
a second latch portion including a plurality of second latch circuits configured to operate based on two power supply voltages, the data signal line drive circuit being configured to output data signals to a plurality of data signal lines,
wherein each of the plurality of first latch circuits captures a data signal transmitted from outside, based on a first latch signal, and outputs the captured data signal,
each of the plurality of second latch circuits captures a data signal output from a corresponding first latch circuit, based on a second latch signal, and outputs the captured data signal to a corresponding data signal line,
each of the plurality of first latch circuits is provided with a shift pulse output from a corresponding unit circuit as the first latch signal, and
first latch signals provided to (k+1)-th and subsequent first latch circuits are given as the second latch signal to a k-th second latch circuit, as capturing of data signals at the second latch portion is split into two or more timings, with k as a natural number.
According to such a configuration, the capturing of the data signals (data signals output from the first latch portion) in the second latch portion is performed by dividing into two or more timings instead of being performed in unison. In other words, the output timings of the data signals to the plurality of data signal lines are distributed. As a result, the size of the voltage drop caused by the output of the data signals to the data signal lines is significantly smaller than in the related art. Because no delay circuit is provided in the data signal line drive circuit, the time difference of the capturing timings of the data signals can be increased without increasing the circuit size. In the configuration described above, a data signal line drive circuit is realized that can effectively reduce the effect of voltage drop while suppressing an increase in circuit size.
(2) A data signal line drive circuit according to some embodiments of the disclosure includes the configuration of (1) described above,
wherein a first latch signal provided to a (k+p)-th first latch circuit is provided as the second latch signal to the k-th second latch circuit, with p as a particular natural number.
(3) A data signal line drive circuit according to some embodiments of the disclosure includes the configuration of (1) described above,
wherein a same signal is provided as the second latch signal to continuous q second latch circuits, with q as an integer greater than or equal to 2.
(4) A data signal line drive circuit according to some embodiments of the disclosure includes the configuration of (1) described above,
wherein the data signals represent binary data.
(5) A liquid crystal display device according to some embodiments of the disclosure includes:
a plurality of pixel circuits including memory circuits configure to hold data, based on the data signals;
a plurality of data signal lines configured to supply the data signals to the plurality of pixel circuits; and
a data signal line drive circuit according to any configuration of (1) to (4) described above.
These and other objects, features, aspects, and advantages of the disclosure will become more apparent from the following detailed description of the disclosure with reference to the accompanying drawings.
The disclosure will be described with reference to the accompanying drawings, wherein like numbers reference like elements.
Embodiments will be described below with reference to the accompanying drawings. The liquid crystal display device described in each of the following embodiments is a liquid crystal display device called the “memory liquid crystal” described above.
As illustrated in
The gate driver 20 drives the gate bus lines GL (1) to GL (i), based on a gate control signal GCTL transmitted from the outside. The gate control signal GCTL includes a gate start pulse signal and a gate clock signal. The operation of the gate driver 20 typically applies active scanning signals sequentially one at a time to the i gate bus lines GL, in each vertical scanning period. The binary driver 30 receives a binary control signal BCTL and a data signal DATA transmitted from the outside, and applies the data signal to the j source bus lines SL (1) to SL (j). The detailed configuration and operation of the binary driver 30 will be described later. Note that the gate control signal GCTL and the binary control signal BCTL may be generated by a timing generator in the liquid crystal display device 1.
As described above, by the data signal being applied to each of the source bus lines SL (1) to SL (j), and the scanning signal being applied to each of the gate bus lines GL (1) to GL (i), an image is displayed to the display portion 10. Note that in the following, the data signal applied to the source bus lines is also denoted by the reference sign SL, and the scanning signal applied to the gate bus lines is also denoted by reference sign GL.
The switch 110 is a n-channel type transistor. The switch 110 is in the on state in a case where the scanning signal GL is at the high level. In a case where the switch 110 is in the on state, the source bus line SL and the node 125 in the memory circuit 120 are electrically connected via the switch 110. In the configuration described above, in a case where the scanning signal GL is at the high level, the potential of the data signal SL is provided to the node 125.
The memory circuit 120 is constituted by a CMOS inverter 120a including a p-channel type transistor 121 and an re-channel type transistor 122, and a CMOS inverter 120b including a p-channel type transistor 123 and an n-channel type transistor 124. For the CMOS inverter 120a, the input terminal is connected to the node 126, and the output terminal is connected to the node 125. For the CMOS inverter 120b, the input terminal is connected to the node 125, and the output terminal is connected to the node 126. In the configuration described above, the memory circuit 120 functions to hold a value (logic value) based on the potential provided to the node 125 in a case where the switch 110 is in the on state until the next time the switch 110 is in the on state.
The liquid crystal drive voltage application circuit 130 is constituted by a CMOS switch 130a including a p-channel type transistor 131 and an n-channel type transistor 132, and a CMOS switch 130b including an n-channel type transistor 133 and a p-channel type transistor 134. The CMOS switch 130a is in the on state in a case where the potential of the node 125 is at the high level and the potential of the node 126 is at the low level. In a case where the CMOS switch 130a is in the on state, a white display voltage VA is provided to the pixel electrode 142. The CMOS switch 130b is in the on state in a case where the potential of the node 125 is at the low level and the potential of the node 126 is at the high level. In a case where the CMOS switch 130b is in the on state, a black display voltage VB is provided to the pixel electrode 142.
The display element portion 140 is constituted by a liquid crystal 141, a pixel electrode 142, and a common electrode 143. A voltage is applied to the liquid crystal, based on the voltage applied to the pixel electrode 142 and the voltage applied to the common electrode 143, and the liquid crystal application voltage is reflected in the display state of the pixel.
According to the pixel circuit 100 configured as described above, in a case where the scanning signal GL applied to the corresponding gate bus line is at the high level, the binary data is held in the memory circuit 120, based on the potential of the data signal SL that is being applied to the corresponding source bus line (see
Note that a CMOS switch including a p-channel type transistor and an n-channel type transistor may be provided instead of an n-channel type transistor as the switch 110. An n-channel type transistor may be provided instead of the CMOS switch 130a, and an n-channel type transistor may be provided instead of the CMOS switch 130b.
Here, a configuration of one stage of the shift register 310 (the configuration of the unit circuit 31) will be described with reference to
As can be seen from
In the unit circuit 31, in a case where the set signal S is set to the high level while the reset signal R is maintained at the low level, the potential of the node 515 is set to the low level while the switch 530 is off. As a result, the potential of the node 525 is set to the high level. Here, for the clocked inverter 540, the input terminal is connected to the node 546, and the output terminal is connected to the node 547. For the CMOS inverter 550, the input terminal is connected to the node 547, and the output terminal is connected to the node 546. In the configuration described above, during the period in which the reset signal R is maintained at the low level, the potential of the node 525 is held by the clocked inverter 540 and the CMOS inverter 550. In a case where the clock CK is at the high level in this state, the output signal from the NAND circuit 560 is set to the low level. At this time, the clock CKB is at the low level, and the output signal from the NOR circuit 570 is at the high level. Then, the output signal from the inverter 580 is set to the low level, and the output signal from the inverter 590 is set to the high level. In this way, the output signal OUT from the unit circuit 31 is set to the high level.
In the unit circuit 31, in a case where the reset signal R is set to the high level while the set signal S is maintained at the low level, the n-channel type transistors 522 and 530 are in the on state and the p-channel type transistor 521 is in the off state, so the potential of the node 525 is set to the low level. At this time, because the potential of the node 547 is also set to the low level, the output signal from the NAND circuit 560 is set to the high level regardless of whether the clock CK is at the high level or the low level. As a result, the output signal from the NOR circuit 570 is set to the low level regardless of whether the clock CKB is at the high level or the low level. Then, the output signal from the inverter 580 is set to the high level, and the output signal from the inverter 590 is set to the low level. In this way, the output signal OUT from the unit circuit 31 is set to the low level.
In the configuration described above, in each of the unit circuits 31, after the set signal S is set to the high level, the output signal LTEN is set to the high level, based on the clocks CK and CKB (i.e., the shift pulse is outputted). Then, the output signal LTEN is set to the low level by the reset signal R being at the high level.
Since the unit circuit 31 operates as described above, the output signal LTEN from the unit circuit 31 is set to the high level stage by stage, based on the binary clock signals BCK and BCKB, after the generation of the pulse of the binary start pulse signal BSP. That is, the high-level output signal LTEN output from each of the unit circuits 31 is sequentially transferred as a shift pulse from the first stage to the final stage. The output signal LTEN from each of the unit circuits 31 is provided to the unit circuits 31 at the next stage and the previous stage, is provided as a first latch signal to the corresponding first latch circuit 32, and is provided as a second latch signal to the second latch circuit 33 in two prior stages. In this way, the first latch circuit 32 as well as the second latch circuit 33 are operated based on the output signal LTEN from the unit circuit 31 constituting the shift register 310.
With respect to the constituent elements illustrated in
Incidentally, the portion denoted by reference sign 4 in
The unit latch circuit 60 in the first latch circuit 32 is provided with a data signal DATA transmitted from the outside as an input signal IN, and is provided with a first latch signal as an enable signal EN. The unit latch circuit 60 in the second latch circuit 33 is provided with a data signal output from the corresponding unit latch circuit 60 in the first latch circuit 32 as an input signal IN, and is provided with a second latch signal as an enable signal EN. Note that the input signal IN to the unit latch circuit 60 is one bit of data (i.e., binary data).
The enable signal EN input to the unit latch circuit 60 is provided to the gate terminal of the n-channel type transistor 621. As illustrated in
For the clocked inverter 630, the input terminal is connected to the node 662, and the output terminal is connected to the node 661. For the CMOS inverter 640, the input terminal is connected to the node 661, and the output terminal is connected to the node 662. In a case where the enable signal EN is at the low level, both the p-channel type transistor 631 and the n-channel type transistor 634 are set to the on state, and in a case where the enable signal EN is at the high level, both the p-channel type transistor 631 and the n-channel type transistor 634 are set to the off state. In the configuration described above, the value of the input signal IN input to the unit latch circuit 60 in a case where the enable signal EN is at the high level is then held by the clocked inverter 630 and the CMOS inverter 640 over a period until the next time the enable signal EN is set to the high level. Incidentally, in a case where the input signal IN is at the high level, the potential of the node 661 is set to the high level, and the output signal OUT is also set to the high level. On the other hand, in a case where the input signal IN is at the low level, the potential of the node 661 is set to the low level, and the output signal OUT is also set to the low level.
Because the unit latch circuit 60 operates as described above, the first latch circuit 32 captures and outputs the data signal, based on the first latch signal, and the second latch circuit 33 captures and outputs the data signal, based on the second latch signal.
After the pulse generation of the binary start pulse signal BSP, in a case where the binary clock signal BCK rises first, the output signal LIEN (1) from the unit circuit 31 (1) at the first stage is set to the high level. The output signal LIEN (1) is provided to the first latch circuit 32 (1) at the first stage as the first latch signal L1 (1) in. As a result, the first latch circuit 32 (1) at the first stage captures the data signal DATA transmitted from the outside. Next, in a case where the binary clock signal BCKB rises, the output signal LIEN (2) from the unit circuit 31 (2) at the second stage is set to the high level. The output signal LIEN (2) is provided to the first latch circuit 32 (2) at the second stage as the first latch signal L1 (2) in. As a result, the first latch circuit 32 (2) at the second stage captures the data signal DATA transmitted from the outside. Next, in a case where the binary clock signal BCK rises, the output signal LIEN (3) from the unit circuit 31 (3) at the third stage is set to the high level. The output signal LIEN (3) is provided to the first latch circuit 32 (3) at the third stage as the first latch signal L1 (3) in. As a result, the first latch circuit 32 (3) at the third stage captures the data signal DATA transmitted from the outside.
Incidentally, the output signal LIEN (3) is provided as the second latch signal L2 (1) in to the second latch circuit 33 (1) at the first stage. Thus, at the time point t01 (see
At the time point t02 (see
According to the present embodiment, as k is a natural number, the second latch circuit 33 (k) at the k-th stage is given the output signal LIEN (k+2) from the unit circuit 31 (k+2) at the (k+2)-th stage (in other words, the first latch signal provided to the first latch circuit 32 (k+2) at the (k+2)-th stage) as the second latch signal. For this reason, the capturing of the data signal in the second latch portion 330 is not performed in unison, but is performed sequentially stage by stage. In other words, the output of the data signal to the source bus lines is performed sequentially for every 16 lines. Since the output timing of the data signal to the source bus lines is distributed in this manner, the size of the voltage drop caused by the output of the data signal to the source bus lines becomes significantly smaller than in the related art (see portions with the reference signs 71 and 72 in
Hereinafter, aspects different from the first embodiment will be mainly described.
After the pulse of the binary start pulse signal BSP is generated, in a case where the binary clock signal BCK rises first, the output signal LIEN (1) is set to the high level, and as in the first embodiment, the data signal DATA transmitted from the outside is captured by the first latch circuit 32 (1) at the first stage. Next, in a case where the binary clock signal BCKB rises, the output signal LIEN (2) is set to the high level, and as in the first embodiment, the data signal DATA transmitted from the outside is captured by the first latch circuit 32 (2) at the second stage.
In the present embodiment, the output signal LIEN (2) is provided as the second latch signal L2 (1) in to the second latch circuit 33 (1) at the first stage (see
At the time point t12 (see
In the present embodiment as well, similar to the first embodiment, a binary driver 30 can be realized in which a voltage drop effect can be effectively reduced while suppressing an increase in circuit size.
In the present embodiment, the second latch circuit 33 (1) at the first stage is provided with the output signal LIEN (4) from the unit circuit 31 (4) at the fourth stage as the second latch signal. Therefore, by the output signal LTEN (4) being set to the high level at the time point t21 (see
At the time point t22 (see
In the present embodiment as well, similar to the first embodiment, a binary driver 30 can be realized in which a voltage drop effect can be effectively reduced while suppressing an increase in circuit size.
After the pulse of the binary start pulse signal BSP is generated, in a case where the binary clock signal BCK rises first, the output signal LIEN (1) is set to the high level, and as in the first embodiment, the data signal DATA transmitted from the outside is captured by the first latch circuit 32 (1) at the first stage. Next, in a case where the binary clock signal BCKB rises, the output signal LIEN (2) is set to the high level, and as in the first embodiment, the data signal DATA transmitted from the outside is captured by the first latch circuit 32 (2) at the second stage. Next, in a case where the binary clock signal BCK rises, the output signal LIEN (3) is set to the high level, and as in the first embodiment, the data signal DATA transmitted from the outside is captured by the first latch circuit 32 (3) at the third stage.
In the present embodiment, the output signal LIEN (3) is provided as the second latch signal L2 (1) in to the second latch circuit 33 (1) at the first stage and as the second latch signal L2 (2) in to the second latch circuit 33 (2) at the second stage. Thus, at the time point t31 (see
At the time point t32 (see
In the present embodiment as well, similar to the first embodiment, a binary driver 30 can be realized in which a voltage drop effect can be effectively reduced while suppressing an increase in circuit size.
Incidentally, in the present embodiment, the grouping is performed for every three second latch circuits 33 in a configuration in which 100 second latch circuits 33 are present, the second latch circuit 33 (100) at the 100-th stage is not grouped. In other words, as illustrated in
In the present embodiment, as described above, the output signal LIEN (4) from the unit circuit 31 (4) at the fourth stage is provided as the second latch signal to the second latch circuits 33 (1) to 33 (3) at the first to third stages. Therefore, by the output signal LIEN (4) being set to the high level at the time point t41 (see
At the time point t42 (see
In the present embodiment as well, similar to the first embodiment, a binary driver 30 can be realized in which a voltage drop effect can be effectively reduced while suppressing an increase in circuit size.
Although the disclosure has been described in detail above, the above description is exemplary in all respects and is not limiting. It is understood that numerous other modifications or variations can be made without departing from the scope of the disclosure.
While preferred embodiments of the present invention have been described above, it is to be understood that variations and modifications will be apparent to those skilled in the art without departing from the scope and spirit of the present invention. The scope of the present invention, therefore, is to be determined solely by the following claims.
This application claims the benefit of priority to U.S. Provisional Application No. 62/937,291 filed on Nov. 19, 2019. The entire contents of the above-identified application are hereby incorporated by reference.
| Number | Name | Date | Kind |
|---|---|---|---|
| 20010022581 | Koyama | Sep 2001 | A1 |
| 20020158857 | Iisaka | Oct 2002 | A1 |
| 20030090481 | Kimura | May 2003 | A1 |
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| 20100123704 | Nishimizu et al. | May 2010 | A1 |
| 20110148842 | Nakayama | Jun 2011 | A1 |
| Number | Date | Country |
|---|---|---|
| 2010-122509 | Jun 2010 | JP |
| Number | Date | Country | |
|---|---|---|---|
| 20210150999 A1 | May 2021 | US |
| Number | Date | Country | |
|---|---|---|---|
| 62937291 | Nov 2019 | US |
