Claims
- 1. A method of slicing a data signal comprising:
- clamping the data signal to a reference level;
- applying the clamped data signal to one input of a comparator to produce a sliced output;
- sampling the sliced output of the comparator with a high frequency dot clock to produce a series of positive and negative logic levels;
- applying the series of positive and negative logic levels to a D/A converter;
- filtering the output of the D/A converter to develop a DC voltage; and
- applying the DC voltage to the other input of said comparator to adjust the slice level of the comparator.
- 2. The method of claim 1 wherein said data signal is included in a television signal line and is preceded by a horizontal sync pulse, the tip of said horizontal sync pulse establishing said reference level.
- 3. A data slice circuit comprising:
- clamp means for clamping a received data signal to a reference level;
- a comparator having a first input coupled to said clamp means, a second input and an output;
- means for sampling the output of said comparator with a high frequency dot clock to develop a series of positive and negative logic levels for a period of said data signal;
- a D/A converter coupled to said comparator output and receiving said series of positive and negative logic levels; and
- filter means coupled between the output of said D/A converter and said second input of said comparator for developing a DC voltage representative of said series of positive and negative logic levels and for applying said DC voltage to said second comparator input for adjusting the slice level of said comparator.
- 4. A method of optimizing the slice level of a digital data signal comprising a run-in portion and a data portion of the same data rate comprising:
- clamping the digital data signal to a reference level;
- applying the clamped data signal to one input of a comparator for slicing the clamped data signal at a first level;
- sampling the sliced data signal with a high frequency dot clock to generate a series of positive and negative logic levels for a period of the sliced data signal;
- applying said series of positive and negative logic levels to a D/A converter;
- filtering the output of said D/A converter to develop a DC voltage based upon said series of positive and negative logic levels; and
- applying the Dc voltage to another input of said comparator to adjust said first level.
Parent Case Info
This application is a continuation of application Ser. No. 780,698 filed Oct. 18, 1991.
US Referenced Citations (7)
Foreign Referenced Citations (1)
Number |
Date |
Country |
62-084687 |
Apr 1982 |
JPX |
Continuations (1)
|
Number |
Date |
Country |
Parent |
780698 |
Oct 1991 |
|