Patent Application
20120005451
This application claims priority under 35 U.S.C §119, of Korean Patent Application No. 10-2010-0064049 filed Jul. 2, 2010, the entirety of which is incorporated by reference herein.
1. Field of the Invention
Exemplary embodiments of the present general inventive concept relate to a data storage device to manage a bad block of a storage unit.
2. Description of the Related Art
Semiconductor memory devices are a microelectronic component commonly found in digital logic systems, such as computers, and microprocessor-based applications ranging from satellites, consumer electronics, and so on. According to improvement in the fabrication of semiconductor memory devices, including process enhancements and circuit-design-related developments that allow scaling to higher memory densities and faster operating speeds, performance standards have been established for digital logic systems and other application systems using the semiconductor memory devices.
Semiconductor memory devices generally include volatile memory devices, such as random access memory (RAM) devices, and nonvolatile memory devices. In RAM devices, data is stored by either establishing the logic state of a bistable flip-flop such as in a static random access memory (SRAM), or by charging a capacitor in a dynamic random access memory (DRAM). In both SRAM and DRAM devices, data remains stored and may be read as long as the power is applied, but data is lost when the power is turned off.
Mask read-only memory (MROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM) nonvolatile memory electrically erasable programmable read-only memory (EEPROM) devices are capable of storing the data, even with the power turned off. The non-volatile memory data storage state may be permanent or reprogrammable, depending upon the fabrication technology used. Non-volatile semiconductor memories are used for store program and microcode storage in a wide variety of applications in the computer, avionics, telecommunications, and consumer electronics industries. A combination of single-chip volatile as well as non-volatile memory storage modes is also available in devices such as non-volatile SRAM (nvRAM) for use in systems that require fast, reprogrammable non-volatile memory. In addition, dozens of special memory architectures have evolved which contain some additional logic circuitry to optimize their performance for application-specific tasks.
Since mask read-only memory (MROM), programmable read-only memory (PROM) and erasable programmable read-only memory (EPROM) nonvolatile memory devices are not designed to erase and write by system itself, it is difficult to update the contents of the memory. Although electrically erasable programmable read-only memory (EEPROM) nonvolatile memory devices are electrically erasable and writable, a continuous update process should be readily applied to auxiliary memories or system programming memories.
The feature and utilities of embodiments of the inventive concept are directed to provide a data storage device including a storage unit, and a controller configured to control the storage unit. The controller is configured to manage a mapping between a logical address space and a virtual address space of the storage unit, virtual address space of the storage unit being variable.
Additional aspects and advantages of the present general inventive concept will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the general inventive concept.
The feature and utilities of embodiments of the inventive concept may be directed to provide a bad block managing method of a data storage device including a storage unit. The bad block managing method may include determining a virtual address space of the storage unit, and varying the virtual address space of the storage unit discontinuously when a bad block is generated from the storage unit.
The feature and utilities of embodiments of the inventive concept may be directed to provide a data storage device which includes a storage unit including a user data area having a plurality of blocks and a reserved area having a plurality of blocks, and a controller configured to control the storage unit. The controller may include a processing unit, a code RAM to store a flash translation layer and a virtual flash layer to be executed by the processing unit, and a buffer RAM to temporarily store data to be stored in the storage unit. The buffer RAM may store a map table having mapping information between a logical address space and a virtual address space of the storage unit. When a bad block is generated at the storage unit, the virtual flash layer may replace the bad block with a corresponding block of the reserved area to the bad block, and the flash translation layer may update the map table so as to map a virtual block address of the replaced block to a corresponding logical block address to the bad block instead of a virtual block address of the bad block.
The feature and utilities of embodiments of the inventive concept may be directed to provide a data storage device including a storage unit having a virtual block space and a reserved space, and a controller configured to control the storage unit, to set virtual addresses of the virtual block space, the virtual addresses including a virtual address of a block of the reserved space to replace a virtual address of a bad block of the virtual block space, and to perform a request using the previously set virtual addresses of the virtual block space. The virtual block space may be variable according to occurrence of the bad block of the reserved space.
When the request corresponds to the bad block of the virtual block space, the controller may perform the request received from an external device, without determining the bad block of the virtual block space and retrieving information on the virtual address of the block of the reserved space upon receiving the request.
The virtual addresses may not be continuous by replacing the virtual address of the bad block of the virtual block space with the virtual address of the block of the reversed space, and that virtual block space are increased by including the block of the reversed space.
The number of original virtual addresses of the virtual block space may be the same number of the virtual addresses including the virtual address of the block of the reserved space.
The storage unit may include a plurality of sub-storage units each having the virtual block space and the reserved space, the bad block may be one block of one row of the virtual block space of the one sub-storage unit, and the virtual addresses may include a virtual address of one block of one row of the reserved space of the other sub-storage unit.
These and/or other aspects and advantages of the present general inventive concept will become apparent and more readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:
Reference will now be made in detail to the embodiments of the present general inventive concept, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the like elements throughout. The embodiments are described below in order to explain the present general inventive concept while referring to the figures.
It will be understood that, although the terms first, second, third etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the inventive concept.
Spatially relative terms, such as “beneath”, “below”, “lower”, “under”, “above”, “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as “below” or “beneath” or “under” other elements or features would then be oriented “above” the other elements or features. Thus, the exemplary terms “below” and “under” can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. In addition, it will also be understood that when a layer is referred to as being “between” two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the inventive concept. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.
It will be understood that when an element or layer is referred to as being “on”, “connected to”, “coupled to”, or “adjacent to” another element or layer, it can be directly on, connected, coupled, or adjacent to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being “directly on,” “directly connected to”, “directly coupled to”, or “immediately adjacent to” another element or layer, there are no intervening elements or layers present.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this inventive concept belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and/or the present specification and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
Referring to
As illustrated in
The data storage device illustrated in
Referring to
In the event that a block of a user data area 101a is determined as a bad block, the bad block may be replaced with a block in a reserved area 101b. For example, as illustrated in
Here, the bad block may not be used to write or store data therein. The bad block may be prevented from being written thereto that has failed.
The controller 200 may manage the mapping between bad blocks and replaced blocks. The mapping between bad blocks and replaced blocks may be managed through a bad block map table 202. The bad block map table 202 may be used to determine whether a bad block is replaced with any block of the reserved area 101b. Managing of the bitmap 201 and the bad block map table 202 may be made by a lower layer (hereinafter, referred to as a Virtual Flash Layer (VFL)) of a FTL. The VFL may manage bad blocks in the user data area 101a using the bitmap 201 and the bit block map table 202. Information such as the bitmap, the bad block map table, etc., may be stored temporarily in a buffer RAM of
Referring to
Referring to
For example, when the requested block is a block BLK of
Referring to
The controller 1200 may control an access (for example, a read, write, or erase operation) to the storage unit 1100 in response to a request from a host 2000. The controller 1200 may include an FTL 1201 and a VFL 1202. The FTL 1201 may manage the mapping between logical addresses and virtual addresses. The VFL 1202 may manage bad blocks. The FTL 1201 may manage (create, change, modify, delete, update, control, etc.) a virtual address space of the user data area according to one or more bad blocks included in the user data area. In a case where a block is generated, the VFL 1202 replaces the bad block with a block of a reserved area and notifies a virtual address corresponding to the replaced block to the FTL 1201. The FTL 1201 may manage a map table such that a virtual address of the replaced block is mapped to a corresponding logical address instead of a virtual address of the bad block. This means that a virtual address space of the user data area is changed in a discontinuous manner because no virtual address of the bad block is used (or, because a virtual address of the bad block is mapped out from the map table). According to the discontinuous manner, the virtual addresses of the user data area are not continuously arranged to be used for a process of writing and storing data therein, or at least one or more blocks of continuously arranged blocks of the user data area are not used for the process of writing and storing data therein. Since the virtual address of the bad block is replaced with a virtual address of a block of the reserved area, the virtual address of the block of the reserved area is arranged to be used between the virtual addresses of the user data area, for example, to correspond to the virtual address of the replaced bad block.
In a case of the above-described bad block managing manner, since a virtual block address of a block of a reserved area used to replace a bad block is mapped directly with a corresponding logical block address to the bad block by the FTL 1201, it is possible to skip operations of determining whether a block to be accessed is a bad block and whether a bad block is replaced with any block.
As illustrated in
For example, when the user data area 1101 has M bad blocks, the virtual address space is increased to include corresponding blocks of the reserved area. When the user data area 1101 has N bad blocks, the virtual address space is increased to include corresponding blocks of the reserved area, as illustrated in
Referring to
It is possible to skip processes of determine whether a block to be accessed is a bad block and whether a bad block is replaced with any block, by managing the block map table 1210 so as to include a virtual block address of a replaced block. This means that there may not need to perform a process of storing bitmap information and bad block map information, for example, described in
When one or more blocks are found and determined as bad blocks, information on the bad blocks and replacement blocks of the reserved area is created. Thus, when the data storage device receives a request to write and store data, the data storage device does not have to perform a process of determining the blocks, in which the data is written or stored, as the bad blocks because of the created information on the bad blocks and the replacement blocks. And thus, the data storage device writes and stores the data according to the information without performing a process of storing bitmap information and bad block map information, when the corresponding request is received.
In operation S200, a controller 1200 receives an input/output (or, read/write) request from a host 2000. In operation S210, the controller 1200 may access the requested block without bitmap searching. For example, when an access is requested with respect to a normal block included in a user data area 1101, the normal block may be accessed in the same manner as described in
Referring to
In a case of the paired mapping manner, when one 5-1 of blocks 5-0 and 5-1 in a virtual block #5 is determined as a bad block, a virtual block #5 including the bad block 5-1 may be replaced with a virtual block #9 (including blocks 9-0 and 9-1) of the reserved area 3114. That is, replacement of the bad block may be made by a virtual block unit. In this case, as described in
In a case of the unpaired mapping manner, if one 5-1 of blocks 5-0 and 5-1 in a virtual block #5 is determined as a bad block, only the bad block 5-12 of the blocks 5-0 and 5-1 in the virtual block #5 may be replaced with a block 9-0 or 9-1 in a corresponding virtual block #9 of the reserved area 3114. At this time, a normal block 5-0 of the virtual block #5 including the bad block 5-1 may be used. Likewise, as described in
Referring to
In an exemplary embodiment, it is possible to access a normal block and a replaced block using the bad block map table 3202. For example, when an access is requested with respect to a virtual block 3116, the FTL may provide a virtual block address corresponding to the virtual block 3116 to the VFL. The VFL may judge whether the virtual block address corresponds to a replaced virtual block, depending upon a bitmap. If the virtual block address is judged to be a replaced virtual block, the VFL refers to the bad block map table 3202 and provides address information to a storage unit 3100 so as to access a normal block of the plane 3111 and a replaced block of the plane 3112.
Referring to
As illustrated in
That is, one or more bad blocks of Device 0 (4101) can be replaced with a block of the reserved area of Device 0 (4101), which is one of the memory chip pairs, or a block of the reserved area of Device 1 (4102), which is the other one of the memory chip pairs.
Referring to
In an exemplary embodiment, the first interface 5100 of the controller 5000 may be formed of one of computer bus standards, storage bus standards, and iFCPPeripheral bus standards, or a combination of two or more standards. The computer bus standards may includes S-100 bus, Mbus, Smbus, Q-Bus, ISA, Zorro II, Zorro III, CAMAC, FASTBUS, LPC, EISA, VME, VXI, NuBus, TURBOchannel, MCA, Sbus, VLB, PCI, PXI, HP GSC bus, CoreConnect, InfiniBand, UPA, PCI-X, AGP, PCIe, Intel QuickPath Interconnect, Hyper Transport, etc. The storage bus standards may include ST-506, ESDI, SMD, Parallel ATA, DMA, SSA, HIPPI, USB MSC, FireWire (1394), Serial ATA, eSATA, SCSI, Parallel SCSI, Serial Attached SCSI, Fibre Channel, iSCSI, SAS, RapidIO, FCIP, etc. The iFCPPeripheral bus standards may include Apple Desktop Bus, HIL, MIDI, Multibus, RS-232, DMX512-A, EIA/RS-422, IEEE-1284, UNI/O, 1-Wire, I2C, SPI, EIA/RS-485, USB, Camera Link, External PCIe, Light Peak, Multidrop Bus, etc.
The first interface 5100 may include a user input interface to receive a user input to control the controller to perform a writing and storing process to write and/or store data in the storage unit through the second interface 5200.
It is possible that the controller 5000 may communicate with the storage unit without the second interface 5200 if the storage unit is connected to components of the controller 5000 through a data bus.
A data storage device according to exemplary embodiments of the inventive concept, for example, may form a memory card. Although not shown in
Referring to
The computing system includes at least one processing unit (for example, CPU or microprocessor) 7100, a user interface 7200, a modem 7300 such as a baseband chipset, a controller 7400, and a storage unit 7500 formed of non-volatile memory chips. The modem 3300 may be linked with a network via a wire or wireless manner. The controller 7400 and the storage unit 7500 may be substantially identical to those in
Although a few embodiments of the present general inventive concept have been shown and described, it will be appreciated by those skilled in the art that changes may be made in these embodiments without departing from the principles and spirit of the general inventive concept, the scope of which is defined in the appended claims and their equivalents.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2010-0064049 | Jul 2010 | KR | national |
