Patent Application
20170285953
This Application claims priority of Taiwan Patent Application No. 105110254, filed on Mar. 31, 2016, the entirety of which is incorporated by reference herein.
The present invention is related to a data maintenance method of a data storage device, and in particular related to a data maintenance method for Triple-Level Cell.
Flash memory is considered a non-volatile data-storage device, using electrical methods to erase and program itself NAND Flash, for example, is often used in memory cards, USB flash devices, solid state devices, eMMCs, and other memory de vices.
Flash memory such as NAND Flash uses a multiple-block structure to store data, wherein the flash memory uses floating gate transistors. The floating gates of the floating gate transistor may catch electronic charges for storing data. However, the electronics might undergo loss from the floating gate due to the operation of the flash memory or various environmental parameters, which can affect data retention. The writing process of the Triple-Level Cell (TLC) is more complicated than the other types of cells of the flash memory. Therefore, a stable and efficient writing process for the Triple-Level Cell is needed.
A detailed description is given in the following embodiments with reference to the accompanying drawings.
An exemplary embodiment provides a data storage device including a flash memory and a controller. The flash memory has a plurality of first type spare blocks and a plurality of second type spare blocks, wherein the second type spare blocks are capable to store more data volume than the first type spare blocks. The controller writes data into the first type spare blocks in response to a write command, defines the first type spare blocks as a plurality of first type data blocks if stored with data, wherein when a predetermined condition is satisfied, the controller starts to move/copy valid data of a plurality of oldest first type data blocks into one of the second type spare blocks, wherein a plurality of logical addresses of the valid data are mapped to the oldest first type data blocks.
Another exemplary embodiment provides a data storage device including a flash memory and a controller. The flash memory has a plurality of SLC-spare blocks, a plurality of SLC-data blocks and a plurality of TLC-spare blocks. The controller rites data into the SLC-spare blocks in response to a write command arranged to write the data into the flash memory, wherein the controller writes a first part of the data into a first group SLC-spare blocks comprising three of the SLC-spare blocks when a predetermined condition is satisfied, and before writing other parts of the data into the other SLC-spare blocks, the controller selects a second group SLC-data blocks comprising three of the SLC-data blocks which have the oldest valid data from the SLC-data blocks, and moves/copies the data stored in the second group SLC-data blocks into one of the TLC-spare blocks to release the second group SLC-data blocks.
Another exemplary embodiment provides a data maintenance method applied to a data storage device having a flash memory, wherein the flash memory has a plurality of first type spare blocks and a plurality of second type spare blocks, and the second type spare blocks are capable to store more data volume than the first type spare blocks. The data maintenance method includes: writing data into the first type spare blocks in response to a write command; defining the first type spare blocks as a plurality of first type data blocks if stored with data; determining whether a predetermined condition is satisfied; when the predetermined condition is satisfied, starting to move/copy valid data of a plurality of oldest first type data blocks into one of the second type spare blocks, wherein a plurality of logical addresses of the valid data are mapped to the oldest first type data blocks.
Another exemplary embodiment further provides a data maintenance method applied to a data storage device having a flash memory, wherein the flash memory has a plurality of SLC-spare blocks, and a plurality of SLC-data blocks and a plurality of TLC-spare blocks. The data maintenance method includes: receiving a write command arranged to write data into the flash memory; and writing the data into the SLC-spare blocks in response to the write command, wherein when a predetermined condition is satisfied, the step of writing the data into the SIC-spare blocks further includes: writing the first part of the data into a first group SLC-spare blocks including three of the SLC-spare blocks; and before writing the remaining of the data into the other SLC-spare blocks, selecting a second group SLC-data blocks which have valid data for the longest time from the SLC-data blocks, and moving/coping the data stored in the first SLC-data blocks into one of the TLC-spare blocks to release the second group SLC-data blocks.
The present invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein:
The following description is of the best-contemplated mode of carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims.
It should be noted that, before any data is written into the flash memory 180, the TLC-data pool TLC_DA_POOL does not have any TLC-data block and the SLC-data pool SLC_DA_POOL does not have any SLC-data block.
Moreover, the memory space of each of the TLC-data blocks TLC_DA_1˜TLC_DA_Q and the TLC-spare blocks TLC_SP_1˜TLC_SP_M is three times the memory space of each of the SLC-data blocks SLC_DA_1˜SLC_DA_P and the SLC-spare blocks SLC_SP_1˜SLC_SP_N. More specifically, the TLC blocks and the SLC blocks are the blocks of the flash memory 180, the physical structure of the TLC block and the SLC block are the same. However, the controller has to program the TLC block by a specific voltage several times to write data into the TLC block, and the controller only has to program the SLC block one time to write data into the SLC block. In one embodiment, the controller has to program the TLC block by a specific voltage three times to write data into the TLC block. Namely, the data stored in three SLC-data blocks can be written into one TLC-data block.
The SLC block is more stable than the TLC block, so that, in one of the embodiments of the present invention, the function of SLC blocks is arranged to cache data. Namely, the SLC blocks serve as the cache memory for temporarily storing data before the data is written into the TLC blocks. In one embodiment, the controller 160 starts to write the data stored in the SLC blocks into the TLC blocks when the SLC blocks are almost consumed (the number of SLC-data blocks is greater than a predetermined amount). Although moving the data of the SLC-data blocks to the TLC blocks can increase the number of SLC-spare blocks, the controller 160 will not be able to finish the tasks indicated by the user or other devices timely and the performance (read or write) will suffer. Therefore, in one of the embodiments, based on the features of the SLC block and TLC block, the controller 160 may alternatively execute the write operation and the clear operation of the SLC data block to ensure that the SLC-spare block of the flash memory 180 will be provided adequately and the write operation indicated by the host will be finished smoothly.
More specifically, when the controller 160 receives a write command arranged to write data into the flash memory 180 from the host 120, the controller 160 writes the data into the SLC-spare blocks in response to the write command. Moreover, before any of the SLC-spare blocks is written, the controller 160 determines whether the number of SLC-spare blocks SLC_SP_1˜SLC_SP_N is less than a predetermined amount to determine whether a predetermined condition is satisfied. When the number of SLC-spare blocks SLC_SP_1˜SLC_SP_N is less than the predetermined amount, the predetermined condition is satisfied. When the predetermined condition is satisfied, the controller 160 starts to clear the SLC-data blocks SLC_DA_1˜SLC_DA_P. Namely, when the predetermined condition is satisfied, the controller 160 moves/copies the valid data of three oldest SLC data blocks from the SLC data blocks SLC_DA_1˜SLC_DA_P into one of the TLC spare blocks TLC_SP_1˜TLC_SP_M when every three of the SLC spare blocks are written. It should be noted that, in one embodiment, the data storage device 140 has a block maintenance table arranged to record how long the valid data has existed in each of the SLC-data blocks SLC_DA_1˜SLC_DA_P in the SLC-data pool SLC_DA_POOL, but it is not limited thereto. In other embodiments, the data storage device 140 may use other methods to record when or the sequence of the valid data has programmed in each of the SLC-data blocks SLC_DA_1˜SLC_DA_P in the SLC-data pool SLC_DA_POOL. Moreover, when the predetermined condition is not satisfied, the controller 160 writes the data into the SLC-spare blocks without clearing the SLC-data blocks, and determines whether the predetermined condition is satisfied before any of the SLC-spare blocks is written. In another embodiment, the predetermined condition may include any situation that needs to clear the SLC-data blocks.
In one embodiment, the controller 160 maps at least one logical address of the written data to the written SLC-spare blocks and defines the written SLC-spare blocks as the new SLC-data blocks (step S312) after moving/copying the data of the SLC-data block having the longest valid data into one of the TLC-spare blocks TLC_SP_1˜TLC_SP_M (step S310). When a power off event or another interruption occurs during the process of moving/copying data into the TLC-spare block, the original data is still stored in the original SLC-data block. Therefore, the data can also be kept in the SLC block, which is more stable than the TLC block.
For example, when the predetermined condition is satisfied, the controller 160 writes a first part of the data into three of the SLC spare blocks. Next, before a remaining part of the data are written into the other SLC-spare blocks, the controller 160 selects three oldest (first group) SLC-data blocks, which have the oldest valid data, from the SLC-data blocks SLC_DA_1˜SLC_DA_P and moves/copies the data stored in the first group SLC-data blocks into one of the TLC-spare blocks in order to release the first group SLC-data blocks, wherein the mapping between the released first group SLC-data blocks and the original data is lost, and the released first group SLC-data blocks are re-defined as SLC-spare blocks. Next, after the first group SLC-data blocks are released, the controller 160 maps at least one logical address of the first part of the data to the three SLC-spare blocks, and defines the three SLC-spare blocks as three new SLC-data blocks.
After defining the first SLC-spare blocks as the SLC-data blocks, the controller 160 writes a second part of the data into another three of the SLC-spare blocks SLC_DA_1˜SLC_DA_P. before the remaining of the data are written into the other SLC-spare blocks, the controller 160 selects the three oldest (second group) SLC-data blocks, which have the oldest valid data, from the SLC-data blocks SLC_DA_1˜SLC_DA_P and moves/copies the data stored in the second group SLC-data blocks into one of the TLC-spare blocks in order to release the second group SLC-data blocks, wherein the mapping between the released second group SLC-data blocks and the original data is lost, and the released second SLC-data blocks are re-defined as SLC-spare blocks. Next, after the second group SLC-data blocks are released, the controller 160 maps at least one logical address of the second part of the data to the second group SLC-spare blocks, and defines the second group SLC-spare blocks as three new SLC-data blocks. Next the controller 160 repeats the above steps until all of the data is written into the SLC-spare blocks. Moreover, the volume of the first part and second part of the data is able to be stored into three SLC blocks.
In step S300, the controller 160 receives a write command arranged to write data into the flash memory 180 from the host 120. In this embodiment, the volume of the data is larger than the volume of one SLC block, but it is not limited thereto.
Next, in step S302, the controller 160 determines whether a predetermined condition is satisfied. In one embodiment the controller 160 determines whether the number of SLC-spare blocks SLC_SP_1˜SLC_SP_N is less than a predetermined amount to determine whether the predetermined condition is satisfied. When the number of SLC-spare blocks SLC_SP_1˜SLC_SP_N is less than the predetermined amount, the predetermined condition is satisfied. More specifically, when the predetermined condition is satisfied, the process goes to step S304 to start clearing the SLC-data blocks SLC_DA_1˜SLC_DA_P. When the predetermined condition is not satisfied, the process goes to step S314. In the other embodiments, the predetermined condition may include any situation that needs to clear the SLC-data blocks.
In step S304, the controller 160 retrieves a part of the data that has not been written into the SLC-spare blocks. More specifically, the controller 160 retrieves the part of the data, which follows previously data, and the volume of the part of the data is able to be stored into three SLC blocks. If the volume of the data is less than the memory space of three SLC blocks, the controller 160 retrieves all of the data.
Next, in step S306, the controller 160 writes the retrieved part of the data into three (first group) SLC spare-blocks of the SLC-spare blocks SLC_SP_1˜SLC_SP_N. Namely, the controller 160 writes the part of the data that is retrieved in the step S304 into three of the SLC-spare blocks SLC_SP_1˜SLC_SP_N.
Next, in step S308, the controller 160 selects the three oldest (second group) SLC-data blocks which have the oldest valid data from the SLC-data blocks SLC_DA_1˜SLC_DA_P. Namely, the controller 160 selects three SLC-data blocks that have the coldest data from the SLC-data blocks SLC_DA_1˜SLC_DA_P.
Next, in step S310, the controller 160 moves/copies the data stored in the second group SLC-data blocks into one of the TLC-spare blocks to release the second group SLC-data blocks, wherein the mapping between the data and the second group SLC-data blocks are lost, and the released second group SLC-data blocks are defined as new SLC-spare blocks.
Next, in step S312, the controller 160 maps at least one logical address of the retrieved part of the data to the first group SLC-spare blocks, and defines the first group SLC-spare blocks as new SLC-data blocks. Namely, the controller 160 maps at least one logical address of the part of data, which is retrieved in step S304, to the first group SLC-spare blocks written in step S306, and defines the first group SLC-spare blocks written in step S306 as new SLC-data blocks.
In step S313, the controller 160 determines whether all of the data has been written into the SLC blocks. If not all of the data indicated by the received write command is written into the SLC blocks, the process returns to step S304 to continuously write the remaining of the data into the SLC-spare blocks and clear the SLC-data blocks. If all of the data is written into the SLC blocks, the process ends at step S313. It should be noted that, in another embodiment, when not all of the data is written into the SLC blocks, the process returns to step S302 to determine whether the predetermined condition is satisfied.
In step S314, the controller 160 retrieves another part of the data that has not been written into the SLC-spare blocks. More specifically, the controller 160 reeves the next part of the data, which follows the previously retrieved part of the data, wherein the volume of the next part of the data is able to be stored into one SLC block. When the volume of remaining data is less than the memory space of one SLC block, the controller 160 retrieves all of the remaining data.
In step S316, the controller 160 writes the retrieved part of the data into one of the SLC-spare blocks SLC_SP_1˜SLC_SP_N. Namely, the controller 160 writes the part of the data retrieved in step S314 into one of the SLC-spare blocks SLC_SP_1˜SLC_SP_N.
Next, in step S318, the controller 160 maps the logical address of the retrieved part of the data to the written SLC-spare block, and defines the written SLC-spare block as new SLC-data block. Namely, the controller 160 maps the logical address of the part of the data that was retrieved in step S314 to the SLC-spare block that is written in step S316, and defines the SLC-spare block that is written in step S316 as a new SLC-data block.
In step S320, the controller 160 determines whether all of the data are written into the SLC blocks. If not all of the data is written to the SLC-spare block, the process returns to step S302. If all of the data is written into the SLC-spare blocks, the process ends at step S320.
As described above, in steps S304˜S313, the controller 160 moves/copies the data stored in the three oldest SLC-data block SLC_DA_1˜SLC_DA_P that have the oldest valid data into one of the TLC-spare blocks TLC_SP_1˜TLC_SP_M. In steps S314˜S320, the controller 160 continuously writes the data into the SLC-spare blocks, and determines whether the predetermined condition is satisfied before any of the SLC-spare blocks is written.
The data storage device and the data maintenance method may provide SLC-spare blocks in order to write the data into the SLC-spare blocks smoothly.
Data transmission methods, or certain aspects or portions thereof, may take the form of program code (i.e., executable instructions) embodied in tangible media, such as floppy diskettes, CD-ROMS, hard drives, or any other machine-readable storage medium, wherein, when the program code is loaded into and executed by a machine such as a computer, the machine thereby becomes an apparatus for practicing the methods. The methods may also be embodied in the form of program code transmitted over some transmission medium, such as electrical wiring or cabling, through fiber optics, or via any other form of transmission, wherein, when the program code is received and loaded into and executed by a machine such as a computer, the machine becomes an apparatus for practicing the disclosed methods. When implemented on a general-purpose processor, the program code combines with the processor to provide a unique apparatus that operates analogously to application-specific logic circuits.
While the invention has been described by way of example and in terms of the preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.
| Number | Date | Country | Kind |
|---|---|---|---|
| 105110254 | Mar 2016 | TW | national |
