The present invention relates to a data storage device, and relates particularly, but not exclusively, to a semiconductor memory device. The invention also relates to a method of refreshing a data storage device.
DRAM (Dynamic Random Access Memory) devices are known in which an array of charge storage cells is provided, each storage cell consisting of a single transistor and a single capacitor. As is well known, each storage cell stores a single binary data bit according to whether the associated capacitor is charged (data state “1”) or discharged (data state “0”). It is also well known that the charge stored in the charged capacitors decays with time, and that it is therefore necessary to rewrite the data to the charged storage cells by periodically recharging the capacitors. A conventional DRAM arrangement of this type is shown in
For each data storage cell, the source of the associated transistor is connected to one terminal of a capacitor, the other terminal of which is connected to a ground terminal or a given reference voltage (not shown), the gates of the transistors of each row are connected together by a respective conductive track 12, and the drains of the transistors of each column are connected together by a respective conductive track 14. Each of the conductive tracks 12 is connected to a selection circuit 16 for sequentially scanning the conductive tracks 12 of the memory device, and the conductive tracks 14 are each connected to respective writing circuits 18i and reading circuits 20i, where i varies from 1 to m.
In order to refresh the charge states of the data storage cells 10 to counteract the effect of the charge stored in each capacitor decaying with time, the selection circuit 16 scans lines 1 to n by sequentially applying a signal to each conductive track 12 to successively switch on the transistors of all of the data storage cells 10 connected to the conductive track 12 being addressed. This in turn enables the reading circuits 20i to determine the charge state of the associated capacitor by determining the current flowing through each transistor. In response to the determination of the charge state of each capacitor determined by the associated reading circuit 20i, the associated writing circuit 18i causes the capacitor to be recharged or not, depending on its previous charge state.
Prior art DRAM devices of the type shown in
Preferred embodiments of the present invention seek to overcome the above disadvantages of the prior art.
According to an aspect of the present invention, there is provided a data storage device comprising:
a plurality of data storage cells, each said cell having a physical parameter in use which varies with time and has one of two data representing states, each said data representing state representing a respective binary logic state; and
refreshing means for applying input signals to each said data storage cell to at least partially reverse variation of said physical parameter with time of at least those data storage cells in a predetermined one of said states, wherein said input signals cause a different variation in said physical parameter in cells in one of said data representing states than the variation caused in cells in the other of said data representing states.
Data refreshing means are provided to at least partially reverse the variation of said physical parameter with time by means of input signals causing a different variation in said physical parameter in cells in one of said data representing states than the variation caused in cells in the other of said data representing states. This provides the advantage that each data storage cell can be re-written without the need to read the state of each cell in order to enable the re-write operation to proceed. In addition, the write signal can be input to all data storage cells simultaneously, thus significantly increasing the speed of the refreshing operation compared with prior art devices.
In a preferred embodiment, said at least partial reversal of said physical parameter occurs to a greater extent for said cells in said predetermined one of said data representing states than in the other of said states, and said input signals are applied sufficiently frequently in use that said states remain distinguishable from each other.
The device may further comprise writing means for applying input signals to each said data storage cell to adjust said physical parameter of said cell to select the binary logic state represented by each said data storage cell.
The device may further comprise reading means for determining the data representing state of each said data storage cell.
Said input signals may at least partially reverse variation of said physical parameter for cells in each of said data representing states.
The data storage device may be a semiconductor device.
In a preferred embodiment, at least some of said data storage cells each comprise a respective field effect transistor having a first threshold voltage when in said first state and a second threshold voltage when in said second state.
In a preferred embodiment, at least one said field effect transistor comprises a respective source, a respective drain, a respective body arranged between the corresponding said source and said drain and adapted to retain an electrical charge generated in said body representing one or the other of two binary data states, and at least one respective gate adjacent the corresponding said body, wherein said refreshing means is adapted to apply voltage signals between at least one said gate and said drain of each said cell lying between said first and second threshold voltages.
Said refreshing means may be adapted to also apply signals to at least partially reverse the variation of said physical parameter in the other of said data representing states.
Said refreshing means is preferably adapted to apply signals partially reversing the variation of said charge in the other of said data representing states by means of recombination of charge carriers with charge carriers of opposite polarity.
The device may be a memory device.
According to another aspect of the present invention, there is provided a method of refreshing data in a data storage device comprising a plurality of data storage cells, each said cell having a physical parameter in use which varies with time and has one of two data representing states, each said data representing state representing a respective binary logic state, the method comprising applying input signals to each said data storage cell to at least partially reverse variation of said physical parameter with time of at least those data storage cells in a predetermined one of said states, wherein said input signals cause a different variation in said physical parameter in cells in one of said data representing states than the variation caused in cells in the other of said data representing states.
Said input signals may cause said at least partial reversal of said physical parameter occurs to a greater extent for said cells in said predetermined one of said data representing states than in the other of said states.
The method may further comprise the step of applying signals to at least partially reverse the variation of said physical parameter in the other of said data representing states.
The step of applying signals to at least partially reverse the variation of said physical parameter in the other of said data representing states preferably causes recombination of charge carriers with charge carriers of opposite polarity.
Said input signals may at least partially reverse variation of said physical parameter for cells in each of said data representing states.
A preferred embodiment of the invention will now be described, by way of example only and not in any limitative sense, with reference to the accompanying drawings, in which:
Referring to
In the DRAM device of
European patent application no. 01810587.4 describes how data can be written to the individual memory cells 10 of the DRAM device of
Pulse I1 beginning at time t1 and ending at time t2 is applied to the gates of all of the transistors for a duration of some nanoseconds, and comprises a pulse of +0.6V applied to the gates, and +1.2V applied to the drains of the transistors. Pulse I2, which begins at time t3 and ends at time t4, also having a duration of some nanoseconds, consists of the application of a pulse of −2V to the gates alone. The times t2 and t3 may be coincident.
Referring now to
The cells 10 initially have a net positive charge represented by holes stored in the body of the transistor (representing state “1”) or a much lower negative or substantially zero charge (representing state “0”), i.e. the two charged states being higher than or lower than charge level Cn respectively. Without a refresh operation, the difference between these two charge levels decays generally logarithmically with time.
As disclosed in more detail in earlier European patent application no. 01810587.4, the electrical properties of the SOI MOSFET transistors of each data storage cell 10 vary according to the amount of charge stored in the body of the respective transistor. In particular, the threshold voltage of transistors in the higher charge state is lower than that of the transistors in the lower charge state.
When pulse I1 is applied at time t1, the voltage applied to the gates is arranged to be between the respective threshold voltages of the transistors in the higher and lower charge states. As a result, the transistor in the higher charge state is switched to its conductive state, i.e. a conductive channel between the source and drain forms in the body of the transistor in the vicinity of the gate, and a current can flow in the channel between the source and the drain at the interface of the body and the insulating layer adjacent the gate. This current flowing in the channel creates electron and hole pairs in the vicinity of the drain by impact ionisation, the holes being stored in the body, while the electrons are removed by the drain. In this way, the positive charge stored in the body of the transistors in the higher charge state increases by an amount Δ1, while the charge of the transistors in the lower charge state increases by a much smaller amount Δ2, since no conductive channel is formed in the transistors of lower charge state. Δ1 is generally 2 to 3 orders of magnitude greater than Δ2. It is found that electrons are trapped in structural defects in the body at its interface with the insulating film between the body and the gate generally to the same extent, regardless of whether the transistors are in the higher or lower charge state.
At time t3, which is shown in
It can therefore be seen that because pulse I1 has a much more significant effect on transistors in the higher state than in the lower state, this pulse can be applied to all of the memory cells 10 simultaneously, with the effect that the “1” states are refreshed, without the transistors in the “0” state being converted to the “1” state and without the necessity of reading the charge state of each memory cell 10. This permits a refresh process to be made by whole memory blocks allowing, for example in the case of a 1 Gigabit memory, a refresh process approximately 1000 times faster than in the prior art. It is also possible to use transistors having technical characteristics less difficult to achieve than in the prior art, in particular, transistors having a lower charge retention time, for which the cost is consequently lower.
It will be appreciated by persons skilled in the art that the above embodiment has been described by way of example only, and not in any limitative sense, and that various alterations and modifications are possible without departure from the scope of the invention as defined by the appended claims. In particular, the order of application of pulses I1 and I2 can be reversed, and the above process described with reference to NMOS transistors can also be applied to PMOS transistors, the polarity of the voltages applied to the gates in that case being reversed. Also, JFET type transistors can be used as well as MOSFET type transistors. Furthermore, as well as being applicable to DRAM memory type devices, it will be appreciated by persons skilled in the art that the refreshing process can be applied to other types of data storage device, such as optical imaging devices and memory devices other than DRAM memories.
Number | Date | Country | Kind |
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02405314 | Apr 2002 | EP | regional |
02077116 | May 2002 | EP | regional |
This application is a divisional application of application Ser. No. 11/048,387, filed Feb. 1, 2005 (now U.S. Pat. No. 7,170,807, which is a divisional application of application Ser. No. 10/487,162, filed Feb. 17, 2004 (now U.S. Pat. No. 6,982,918), which is the National Stage of International Application No. PCT/EP03/02747, filed Mar. 17, 2003, which claims priority to European Patent Application Ser. No. 02077116, filed May 29, 2002, and European Patent Application Ser. No. 02405314, filed Apr. 18, 2002.
Number | Name | Date | Kind |
---|---|---|---|
3439214 | Kabell | Apr 1969 | A |
3997799 | Baker | Dec 1976 | A |
4032947 | Kesel et al. | Jun 1977 | A |
4250569 | Sasaki et al. | Feb 1981 | A |
4262340 | Sasaki et al. | Apr 1981 | A |
4298962 | Hamano et al. | Nov 1981 | A |
4371955 | Sasaki | Feb 1983 | A |
4527181 | Sasaki | Jul 1985 | A |
4630089 | Sasaki et al. | Dec 1986 | A |
4791610 | Takemae | Dec 1988 | A |
4979014 | Hieda et al. | Dec 1990 | A |
5144390 | Matloubian | Sep 1992 | A |
5164805 | Lee | Nov 1992 | A |
5258635 | Nitayama et al. | Nov 1993 | A |
5388068 | Ghoshal et al. | Feb 1995 | A |
5446299 | Acovic et al. | Aug 1995 | A |
5448513 | Hu et al. | Sep 1995 | A |
5466625 | Hsieh et al. | Nov 1995 | A |
5489792 | Hu et al. | Feb 1996 | A |
5528062 | Hsieh et al. | Jun 1996 | A |
5568356 | Schwartz | Oct 1996 | A |
5593912 | Rajeevakumar | Jan 1997 | A |
5606188 | Bronner et al. | Feb 1997 | A |
5608250 | Kalnitsky | Mar 1997 | A |
5627092 | Alsmeier et al. | May 1997 | A |
5631186 | Park et al. | May 1997 | A |
5696718 | Hartmann | Dec 1997 | A |
5740099 | Tanigawa | Apr 1998 | A |
5778243 | Aipperspach et al. | Jul 1998 | A |
5780906 | Wu et al. | Jul 1998 | A |
5784311 | Assaderaghi et al. | Jul 1998 | A |
5811283 | Sun | Sep 1998 | A |
5847411 | Morii | Dec 1998 | A |
5877978 | Morishita et al. | Mar 1999 | A |
5886376 | Acovic et al. | Mar 1999 | A |
5886385 | Arisumi et al. | Mar 1999 | A |
5897351 | Forbes | Apr 1999 | A |
5929479 | Oyama | Jul 1999 | A |
5930648 | Yang | Jul 1999 | A |
5936265 | Koga | Aug 1999 | A |
5939745 | Park et al. | Aug 1999 | A |
5943258 | Houston et al. | Aug 1999 | A |
5943581 | Lu et al. | Aug 1999 | A |
5960265 | Acovic et al. | Sep 1999 | A |
5968840 | Park et al. | Oct 1999 | A |
5977578 | Tang | Nov 1999 | A |
5982003 | Hu et al. | Nov 1999 | A |
6018172 | Hidaka et al. | Jan 2000 | A |
6081443 | Morishita | Jun 2000 | A |
6096598 | Furukawa et al. | Aug 2000 | A |
6097056 | Hsu et al. | Aug 2000 | A |
6111778 | MacDonald et al. | Aug 2000 | A |
6121077 | Hu et al. | Sep 2000 | A |
6157216 | Lattimore et al. | Dec 2000 | A |
6171923 | Chi et al. | Jan 2001 | B1 |
6177300 | Houston et al. | Jan 2001 | B1 |
6177708 | Kuang et al. | Jan 2001 | B1 |
6214694 | Leobandung et al. | Apr 2001 | B1 |
6225158 | Furukawa et al. | May 2001 | B1 |
6245613 | Hsu et al. | Jun 2001 | B1 |
6252281 | Yamamoto et al. | Jun 2001 | B1 |
6292424 | Ohsawa | Sep 2001 | B1 |
6297090 | Kim | Oct 2001 | B1 |
6300649 | Hu et al. | Oct 2001 | B1 |
6320227 | Lee et al. | Nov 2001 | B1 |
6333532 | Davari et al. | Dec 2001 | B1 |
6350653 | Adkisson et al. | Feb 2002 | B1 |
6351426 | Ohsawa | Feb 2002 | B1 |
6359802 | Lu et al. | Mar 2002 | B1 |
6384445 | Hidaka et al. | May 2002 | B1 |
6391658 | Gates et al. | May 2002 | B1 |
6403435 | Kang et al. | Jun 2002 | B1 |
6421269 | Somasekhar et al. | Jul 2002 | B1 |
6424011 | Assaderaghi et al. | Jul 2002 | B1 |
6424016 | Houston | Jul 2002 | B1 |
6429477 | Mandelman et al. | Aug 2002 | B1 |
6440872 | Mandelman et al. | Aug 2002 | B1 |
6441435 | Chan | Aug 2002 | B1 |
6441436 | Wu et al. | Aug 2002 | B1 |
6466511 | Fujita et al. | Oct 2002 | B2 |
6479862 | King et al. | Nov 2002 | B1 |
6492211 | Divakaruni et al. | Dec 2002 | B1 |
6518105 | Yang et al. | Feb 2003 | B1 |
6531754 | Nagano et al. | Mar 2003 | B1 |
6538916 | Ohsawa | Mar 2003 | B2 |
6544837 | Divakaruni et al. | Apr 2003 | B1 |
6548848 | Horiguchi et al. | Apr 2003 | B2 |
6549450 | Hsu et al. | Apr 2003 | B1 |
6552398 | Hsu et al. | Apr 2003 | B2 |
6556477 | Hsu et al. | Apr 2003 | B2 |
6566177 | Radens et al. | May 2003 | B1 |
6567330 | Fujita et al. | May 2003 | B2 |
6590258 | Divakauni et al. | Jul 2003 | B2 |
6590259 | Adkisson et al. | Jul 2003 | B2 |
6617651 | Ohsawa | Sep 2003 | B2 |
6621725 | Ohsawa | Sep 2003 | B2 |
6632723 | Watanabe et al. | Oct 2003 | B2 |
6650565 | Ohsawa | Nov 2003 | B1 |
6661042 | Hsu | Dec 2003 | B2 |
6714436 | Burnett et al. | Mar 2004 | B1 |
6721222 | Somasekhar et al. | Apr 2004 | B2 |
6771546 | Ikehashi et al. | Aug 2004 | B2 |
6861689 | Burnett | Mar 2005 | B2 |
6913964 | Hsu | Jul 2005 | B2 |
20010055859 | Yamada et al. | Dec 2001 | A1 |
20020030214 | Horiguchi | Mar 2002 | A1 |
20020034855 | Horiguchi et al. | Mar 2002 | A1 |
20020036322 | Divakauni et al. | Mar 2002 | A1 |
20020051378 | Ohsawa | May 2002 | A1 |
20020064913 | Adkisson et al. | May 2002 | A1 |
20020070411 | Vermandel et al. | Jun 2002 | A1 |
20020072155 | Liu et al. | Jun 2002 | A1 |
20020076880 | Yamada et al. | Jun 2002 | A1 |
20020086463 | Houston et al. | Jul 2002 | A1 |
20020089038 | Ning | Jul 2002 | A1 |
20020098643 | Kawanaka et al. | Jul 2002 | A1 |
20020110018 | Ohsawa | Aug 2002 | A1 |
20020114191 | Iwata et al. | Aug 2002 | A1 |
20020130341 | Horiguchi et al. | Sep 2002 | A1 |
20020160581 | Watanabe et al. | Oct 2002 | A1 |
20020180069 | Houston | Dec 2002 | A1 |
20030003608 | Arikado et al. | Jan 2003 | A1 |
20030015757 | Ohsawa | Jan 2003 | A1 |
20030035324 | Fujita et al. | Feb 2003 | A1 |
20030057487 | Yamada et al. | Mar 2003 | A1 |
20030057490 | Nagano et al. | Mar 2003 | A1 |
20030102497 | Fried et al. | Jun 2003 | A1 |
20030112859 | Ohsawa | Jun 2003 | A1 |
20030123279 | Aipperspach et al. | Jul 2003 | A1 |
20030146488 | Nagano et al. | Aug 2003 | A1 |
20030151112 | Yamada et al. | Aug 2003 | A1 |
20030168677 | Hsu | Sep 2003 | A1 |
20030213994 | Hayashi et al. | Nov 2003 | A1 |
20040041206 | Bhattacharyya | Mar 2004 | A1 |
20040041208 | Bhattacharyya | Mar 2004 | A1 |
20040042268 | Bhattacharyya | Mar 2004 | A1 |
20040108532 | Forbes | Jun 2004 | A1 |
20050141262 | Yamada et al. | Jun 2005 | A1 |
Number | Date | Country |
---|---|---|
0 030 856 | Jun 1981 | EP |
0 350 057 | Jan 1990 | EP |
0 354 348 | Feb 1990 | EP |
0 202 515 | Mar 1991 | EP |
0 207 619 | Aug 1991 | EP |
0 175 378 | Nov 1991 | EP |
0 253 631 | Apr 1992 | EP |
0 513 923 | Nov 1992 | EP |
0 300 157 | May 1993 | EP |
0 564 204 | Oct 1993 | EP |
0 579 566 | Jan 1994 | EP |
0 362 961 | Feb 1994 | EP |
0 599 506 | Jun 1994 | EP |
0 359 551 | Dec 1994 | EP |
0 366 882 | May 1995 | EP |
0 465 961 | Aug 1995 | EP |
0 694 977 | Jan 1996 | EP |
0 333 426 | Jul 1996 | EP |
0 727 820 | Aug 1996 | EP |
0 739 097 | Oct 1996 | EP |
0 245 515 | Apr 1997 | EP |
0 788 165 | Aug 1997 | EP |
0 801 427 | Oct 1997 | EP |
0 510 607 | Feb 1998 | EP |
0 537 677 | Aug 1998 | EP |
0 858 109 | Aug 1998 | EP |
0 860 878 | Aug 1998 | EP |
0 869 511 | Oct 1998 | EP |
0 878 804 | Nov 1998 | EP |
0 920 059 | Jun 1999 | EP |
0 924 766 | Jun 1999 | EP |
0 642 173 | Jul 1999 | EP |
0 727 822 | Aug 1999 | EP |
0 933 820 | Aug 1999 | EP |
0 951 072 | Oct 1999 | EP |
0 971 360 | Jan 2000 | EP |
0 980 101 | Feb 2000 | EP |
0 601 590 | Apr 2000 | EP |
0 993 037 | Apr 2000 | EP |
0 836 194 | May 2000 | EP |
0 599 388 | Aug 2000 | EP |
0 689 252 | Aug 2000 | EP |
0 606 758 | Sep 2000 | EP |
0 682 370 | Sep 2000 | EP |
1 073 121 | Jan 2001 | EP |
0 726 601 | Sep 2001 | EP |
0 731 972 | Nov 2001 | EP |
1 162 663 | Dec 2001 | EP |
1 162 744 | Dec 2001 | EP |
1 179 850 | Feb 2002 | EP |
1 180 799 | Feb 2002 | EP |
1 191 596 | Mar 2002 | EP |
1 204 146 | May 2002 | EP |
1 204 147 | May 2002 | EP |
1 209 747 | May 2002 | EP |
0 744 772 | Aug 2002 | EP |
1 233 454 | Aug 2002 | EP |
0 725 402 | Sep 2002 | EP |
1 237 193 | Sep 2002 | EP |
1 241 708 | Sep 2002 | EP |
1 253 634 | Oct 2002 | EP |
0 844 671 | Nov 2002 | EP |
1 280 205 | Jan 2003 | EP |
1 288 955 | Mar 2003 | EP |
2 197 494 | Mar 1974 | FR |
1 414 228 | Nov 1975 | GB |
62-272561 | Nov 1987 | JP |
02-294076 | Feb 1991 | JP |
3-171768 | Jul 1991 | JP |
8-213624 | Aug 1996 | JP |
8-274277 | Oct 1996 | JP |
9-046688 | Feb 1997 | JP |
9-82912 | Mar 1997 | JP |
10-242470 | Sep 1998 | JP |
11-87649 | Mar 1999 | JP |
2000-247735 | Aug 2000 | JP |
2000-274221 | Sep 2000 | JP |
2000-389106 | Dec 2000 | JP |
2001-180633 | Jun 2001 | JP |
2002-009081 | Jan 2002 | JP |
2002-94027 | Mar 2002 | JP |
2002-176154 | Jun 2002 | JP |
2002-246571 | Aug 2002 | JP |
2002-329795 | Nov 2002 | JP |
2002-343886 | Nov 2002 | JP |
2002-353080 | Dec 2002 | JP |
2003-31693 | Jan 2003 | JP |
2003-86712 | Mar 2003 | JP |
2003-100641 | Apr 2003 | JP |
2003-100900 | Apr 2003 | JP |
2003-132682 | May 2003 | JP |
2003-203967 | Jul 2003 | JP |
2003-243528 | Aug 2003 | JP |
Number | Date | Country | |
---|---|---|---|
20070109896 A1 | May 2007 | US |
Number | Date | Country | |
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Parent | 11048387 | Feb 2005 | US |
Child | 11649945 | US | |
Parent | 10487162 | US | |
Child | 11048387 | US |