BACKGROUND
Data storage devices (e.g., disk drives or non-volatile semiconductor memories) may be employed as mass storage for a computer system (e.g., desktop, laptop, portable, etc.) or a consumer device (e.g., music player, cell phone, camera, etc.) or other suitable application. The data storage device includes a non-volatile memory (e.g., a disk or a semiconductor memory) for storing user data in blocks which are accessed using an address translation layer. For example, the address translation layer may map a logical block address (LBA) received from a host to a physical block address (PBA) representing a segment of the non-volatile memory. The indirect mapping of LBA to PBA facilitates aspects such as defect mapping, and log-structured file systems where the LBA to PBA mapping may change over time.
An example data storage device employing an address translation layer is a non-volatile semiconductor memory comprising one or more memory devices (such as a flash memory). Each memory device typically comprises a number of blocks which are accessed a page at a time. For example, a single block may comprise 128 pages where each page comprises 4096 bytes. Since a page typically cannot be overwritten without first being erased, a new page in a different block is typically selected to perform an “overwrite” operation. Accordingly, the address translation layer must maintain the appropriate LBA to PBA mapping as each write operation changes the physical location of the user data (similar to a log-structured file system).
When a data storage device is powered on, it typically loads a LBA to PBA mapping table from the non-volatile memory into a volatile memory (DRAM or SRAM) for on-the-fly mapping of LBAs to PBAs when performing access operations. It is desirable to minimize the size of the mapping table in order to reduce the size (and cost) of the volatile memory needed to store the mapping table.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1A shows a data storage device comprising a non-volatile memory and control circuitry.
FIG. 1B is a flow diagram executed by the control circuitry according to an embodiment of the present invention wherein when a write command is received to write to a number of consecutive memory segments, a new run-length mapping entry in a run-length mapping table (RLMT) is created.
FIG. 2 shows a data storage device in the form of a non-volatile semiconductor memory according to an embodiment of the present invention.
FIG. 3A shows an example RLMT comprising a number of entries according to an embodiment of the present invention.
FIG. 3B shows an example entry in the RLMT according to an embodiment of the present invention.
FIG. 3C shows an example single address mapping table (SAMT) comprising a number of entries according to an embodiment of the present invention.
FIG. 3D shows an example entry in the SAMT according to an embodiment of the present invention.
FIGS. 4A-4D illustrate an embodiment of the present invention wherein the memory segments are accessed using a paged based mapping scheme.
FIG. 5A is a flow diagram according to an embodiment of the present invention wherein when a RLMT entry is created or updated in response to a write command, and overlapping entries in the SAMT are deleted.
FIG. 5B is a flow diagram according to an embodiment of the present invention wherein when a read command is received, the LBA to PBA mapping first searches the SAMT and then the RLMT.
FIG. 6A illustrates an embodiment of the present invention wherein entries in the SAMT are periodically coalesced into the RLMT and the corresponding entries in the SAMT deleted.
FIG. 6B illustrates an embodiment of the present invention wherein the coalescing of the SAMT entries into the RLMT occurs during a write operation.
FIG. 6C illustrates an embodiment of the present invention wherein the coalescing of the SAMT entries into the RLMT occurs during a garbage collection procedure.
FIG. 7A shows a data storage device in the form of a disk drive according to an embodiment of the present invention.
FIG. 7B shows an embodiment of the present invention wherein each memory segment corresponds to a data sector in a data track.
DETAILED DESCRIPTION OF EMBODIMENTS OF THE INVENTION
FIG. 1A shows a data storage device 2 according to an embodiment of the present invention comprising a non-volatile memory 4 having a plurality of memory segments, and control circuitry 6 for executing the flow diagram of FIG. 1B. When a write command comprising a logical block address (LBA) is received (step 8), a number of consecutive memory segments to access in response to the write command is determined. When the number of consecutive memory segments to access is greater than a threshold (step 10), a new run-length mapping entry in a run-length mapping table (RLMT) is created (step 12). When the number of memory segments to access is not greater than a threshold, at least one new single address mapping entry in a single address mapping table (SAMT) is created (step 14).
The RLMT and the SAMT are used to map the LBA received in an access command (write/read) to physical block addresses (PBAs). Each PBA is mapped to one of the memory segments in the non-volatile memory 4, wherein the LBA to PBA mapping facilitates mapping out of defective memory segments as well as a log-structured file system (or derivative thereof) such as in a flash memory device or a disk drive implementing shingled tracks.
FIG. 2 shows a data storage device in the form of a non-volatile semiconductor memory 16 comprising a memory controller 18 (e.g., a flash memory controller) and a memory device 20 (e.g., a flash memory). The memory controller 18 comprises a microprocessor 22 for implementing various algorithms, including LBA to PBA mapping, wear leveling, error correction code (etc.). The memory controller 18 further comprises a buffer 24 for buffering write/read data, and an interface circuit 26 for interfacing with one or more memory devices 20. The interface circuitry 26 generates suitable control signals 28 and receives status information 30 from the memory device 20 in connection with executing write/read commands initiated by the microprocessor 22. The interface circuitry 26 also transmits and receives data over an I/O bus 32, including write/read data stored in the buffer 24 or command data generated by the microprocessor 22 and transmitted to a controller 34 integrated with the memory device 20.
The memory device 20 comprises an array of memory cells 36 that are accessed in memory segments referred to as pages. During a write operation, write data received over the I/O bus 32 from the buffer 24 is first stored in a data register 38. The controller 34 then transfers the write data from the data register 38 to a target page in the memory array 36. During a read operation, a page in the memory array 36 is read into the data register 38 and then transferred over the I/O bus 32 where it is stored in the buffer 24. In one embodiment, the memory array 36 comprises a plurality of blocks, each block comprises a plurality of pages, and the pages in a block are erased together by erasing the block.
FIG. 3A shows a RLMT according to an embodiment of the present invention comprising a plurality of entries. In one embodiment, a new entry is created in the RLMT when a write command is received from the host to write to a number of consecutive memory segments that is greater than a threshold. FIG. 3B shows an example entry in the RLMT comprising a starting LBA, a run length identifying the number of consecutive memory segments, and a starting PBA corresponding to the first memory segment. In the embodiment shown in FIG. 3B, the starting PBA may be identified by a block number and a page offset within the block. In another embodiment, the starting PBA may further include an offset within a page. In the latter embodiment, each memory segment may correspond to a part of a page. For example, in an embodiment where the non-volatile semiconductor memory emulates a disk drive, a 4096 byte page may comprise eight 512 byte memory segments (data sectors).
When the number of consecutive memory segments identified in a write command is not greater than a threshold, at least one new entry is created in the SAMT an embodiment of which is shown in FIG. 3C. Each entry in the SAMT may comprise an LBA and a corresponding PBA which may include a block number and page offset within the block as shown in FIG. 3D. In the embodiment wherein a PBA may identify a part of a page, the PBA may further include an offset within a page. If the write command identifies more than one consecutive memory segment but still less than the threshold, multiple entries are created in the SAMT. For example, if a write command identifies two consecutive memory segments and the threshold is two, then two new entries in the SAMT are created each comprising an LBA and corresponding PBA.
Any suitable threshold may be used to determine whether to create a single entry in the RLMT or multiple entries in the SAMT. In one embodiment, the threshold is selected to minimize the size of both tables. Referring to the embodiments of FIGS. 3B and 3D, an RLMT entry is larger than an SAMT entry because it includes a field for storing the run length. Therefore, in one embodiment it may require less memory to store multiple SAMT entries as compared to the memory required to store a single RLMT entry. In one embodiment, the threshold for determining whether to create a new RLMT entry may be adapted over time. For example, the threshold may be increased if too many RLMT entries are being created, or the threshold may be decreased if too many SAMT entries are being created.
In one embodiment, the microprocessor 22 of the memory controller 18 processes the entries in the RLMT to implement page based mapping of the pages in the memory array 24. FIGS. 4A-4D illustrate a paged based mapping scheme according to an embodiment of the present invention. With page based mapping, a page within a first block may be overwritten by writing to a new page of a second block without moving the remaining pages from the first block. This is illustrated in FIG. 4A wherein the third page of a first block is overwritten by writing the new data to a first page of a second block. As shown in FIG. 4B, the third page of the first block is flagged as invalid whereas the remaining pages are unchanged. FIG. 4B also illustrates another overwrite command of the sixth page in the first block to the second page of the second block. This process may be repeated over time until all of the pages of the first block are overwritten by writing the new write data to the pages of the second block as illustrated in FIG. 4D. Once all of the pages in the first block have been overwritten and flagged as invalid, the first block can be erased in order to re-allocate the first block. In an alternative embodiment, a garbage collection procedure may move valid pages remaining in the first block to the second block so that the first block can be erased and re-allocated. In one embodiment, an entry in the RLMT may identify a run length of pages that is less than a full block of pages. In other embodiments, a run length of pages may span multiple blocks (e.g., an integer or fractional number of blocks).
FIG. 5A is a flow diagram according to an embodiment of the present invention wherein when a write command is received (step 40) and the number of consecutive memory segments to access is not greater than a threshold (step 42), a SAMT entry is created (step 44). If the write command performs an overwrite of an existing PBA, the corresponding entry in the SAMT is updated with the new PBA. If the number of consecutive memory segments is greater than the threshold (step 42), a RLMT entry is created (step 46). If the write command performs an overwrite of one or more existing PBAs, one or more corresponding entries in the RLMT are updated (e.g., truncated or extended). In one embodiment, if a new or updated RLMT entry overlaps one or more entries in the SAMT, the corresponding overlapping entries are deleted from the SAMT (step 48). The order of writing the data and updating the tables may be reversed so that the tables are updated prior to executing the write command.
In one embodiment, a new entry created in the SAMT may overlap an entry in the RLMT. Rather than update the RLMT (e.g., by splitting an entry), the microprocessor 22 gives priority to the SAMT. This embodiment is illustrated in the flow diagram of FIG. 5B wherein when a read command is received (step 50) the LBA in the read command is first compared to the entries in the SAMT (step 52). If the LBA is in the SAMT, the read command is executed using the SAMT (step 54). Otherwise, the read command is executed using the RLMT (step 56). In one embodiment, some of the LBAs of a read command may be located in the SAMT, with the remaining LBAs located in the RLMT (any overlapping entries located in both the SAMT and RLMT are taken from the SAMT).
In one embodiment, a plurality of entries in the SAMT may be coalesced into one or more entries in the RLMT thereby reducing the size of the SAMT. FIG. 6A shows an example where LBAs 34-36 were written by executing three separate single segment write commands resulting in three SAMT entries. During a background scan, the control circuitry may identify and coalesce the three consecutive SAMT entries into a single RLMT entry as illustrated in FIG. 6A (the three SAMT entries are deleted). FIG. 6B shows an example where LBAs 34-36 were initially written to three non-consecutive pages resulting in three SAMT entries. During a subsequent write operation, the three LBAs are written to three consecutive pages, and therefore the three SAMT entries are coalesced into a single RLMT entry as illustrated in FIG. 6B (the three SAMT entries are deleted). FIG. 6C shows an example wherein LBAs 34-36 were written to three non-consecutive pages of two blocks resulting in three SAMT entries. During a garbage collection procedure, the three LBAs are relocated to three consecutive pages of a third block and the three SAMT entries coalesced into a single RLMT entry as illustrated in FIG. 6C (the three SAMT entries are deleted).
FIG. 7A shows a data storage system in the form of a disk drive comprising a head 58 actuated over a disk 60 by a voice coil motor (VCM). The disk drive further comprises control circuitry 62 for implementing at least one of the LBA to PBA mapping techniques described above. The disk comprises a plurality of data tracks, wherein in an example shown in FIG. 7B each data track comprises a plurality of data sectors for storing user data and embedded servo sectors (SS) for storing servo positioning information (e.g., track address and servo bursts). In one embodiment, each memory segment corresponds to a data sector accessed through a PBA. Similar to a flash based memory device described above, the disk drive of FIG. 7A may implement a dynamic LBA to PBA mapping, for example, when implementing a log-structured file system. With a log-structured file system, data is typically written to a new memory segment (e.g., data sector) during each write operation (including overwrite operations). The old memory segments (e.g., data sectors) are invalidated and then reallocated using a garbage collection algorithm. A disk drive may implement a log-structured file system, for example, when implementing a shingled track system where write operations progress in the same radial direction so that the data tracks can overlap, thereby increasing the tracks per inch (TPI). Since write operations progress in the same radial direction (e.g., from the OD to ID), an LBA previously assigned to an old PBA is relocated to a new PBA at the “head” of the write log when executing an overwrite operation. The SAMT and RLMT embodiments described above help facilitate this dynamic relocation of LBAs during write operations, thereby reducing the memory required to implement LBA to PBA mapping.
Any suitable control circuitry may be employed to implement the flow diagrams in the embodiments of the present invention, such as any suitable integrated circuit or circuits. For example, the control circuitry may be implemented within a flash memory controller and/or memory device controller as illustrated in FIG. 2. In the embodiment shown in FIG. 7A, the control circuitry may be implemented within a read channel integrated circuit, or in a component separate from the read channel, such as a disk controller, or certain steps described above may be performed by a read channel and others by a disk controller. In one embodiment, the read channel and disk controller are implemented as separate integrated circuits, and in an alternative embodiment they are fabricated into a single integrated circuit or system on a chip (SOC). In addition, the control circuitry may include a suitable preamp circuit implemented as a separate integrated circuit, integrated into the read channel or disk controller circuit, or integrated into an SOC.
In one embodiment, the control circuitry comprises a microprocessor executing instructions, the instructions being operable to cause the microprocessor to perform the steps of the flow diagrams described herein. The instructions may be stored in any suitable computer-readable medium. In one embodiment, they may be stored on a non-volatile semiconductor memory external to the microprocessor, or integrated with the microprocessor in a SOC. In another embodiment, the instructions are stored on a disk and read into a volatile semiconductor memory when the disk drive is powered on. In yet another embodiment, the control circuitry comprises suitable logic circuitry, such as state machine circuitry.
Patent Grant
8443167
