BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 shows a block diagram of a memory card system, according to the prior art;
FIG. 2 shows the memory card system of FIG. 1 with I/O circuits clocked in a host and memory card, according to the prior art;
FIG. 3 shows a flow-chart of steps for a read operation in the memory card system of FIG. 2, according to the prior art;
FIG. 4 shows a timing diagram of signals during a read operation in the memory card system of FIG. 2, according to the prior art;
FIG. 5 shows a block diagram of a memory card system having a memory card generating a read clock signal, according to an embodiment of the present invention;
FIG. 6 shows a flow-chart of steps during a read operation within the memory card system of FIG. 5, according to an embodiment of the present invention;
FIG. 7 shows a timing diagram of signals during a read operation within the memory card system of FIG. 5, according to an embodiment of the present invention;
FIG. 8 shows a flow-chart of steps during a write operation within the memory card system of FIG. 5, according to an embodiment of the present invention;
FIG. 9 shows a block diagram of a memory card system having a card controller and a memory unit with respective read clock signal generators, according to another embodiment of the present invention;
FIG. 10 illustrates a block diagram of an example host controller in the memory card system of FIG. 5, according to an embodiment of the present invention; and
FIG. 11 illustrates a block diagram of an example card controller in the memory card system of FIG. 5, according to an embodiment of the present invention.
The figures referred to herein are drawn for clarity of illustration and are not necessarily drawn to scale. Elements having the same reference number in FIGS. 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, and 11 refer to elements having similar structure and/or function.
DETAILED DESCRIPTION
FIG. 5 shows a block diagram of a memory card system 200 having increased allowable setup time according to an embodiment of the present invention. The memory card system 200 includes a host 202 and a memory card 204.
The host 202 may be a portable electronic device such as a mobile phone, a MP3 player, or a PMP (portable media player), for example. The memory card 204 may be a smart card, a SIM (subscriber identification module) card, or a flash memory card, for example. The present invention may be practiced when the memory card 204 is any type of electronic card having read data accessed by the host 202 that is any electronic device having a coupling with such a memory card 204.
The host 202 includes a host controller 206, a host I/O circuit 208, a host connection unit 210, and a write clock signal generator 223. The host I/O circuit 208 includes a plurality of n data flip flops HF1, HF2, . . . , and HFn for latching data to/from the memory card 204. FIG. 10 shows an example embodiment of the host controller 206 including a host data processor 412 and a host memory device 414 having sequences of instructions (i.e., software) stored thereon. Execution of such sequences of instructions by the host data processor 412 causes the host data processor 412 to perform any function/process/step as described herein as being performed by the host controller 206.
The memory card 204 includes a card internal circuit comprised of a card controller 214 and a memory unit 216. The memory card 204 also includes a card I/O circuit 218, a card connection unit 220, and a read clock generator 222. The card I/O circuit 218 includes a plurality of n data flip flops CF1, CF2, . . . , and CFn for latching data to/from the host 202.
FIG. 11 shows an example embodiment of the card controller 214 including a card data processor 422 and a card memory device 424 having sequences of instructions (i.e., software) stored thereon. Execution of such sequences of instructions by the card data processor 422 causes the card data processor 412 to perform any function/process/step as described herein as being performed by the card controller 214.
FIG. 6 shows a flow-chart of steps during a read operation of the memory card system 200 of FIG. 5, in an example embodiment of the present invention. Referring to FIGS. 5 and 6, the host controller 206 generates a read command RD_CMD sent to the memory card 204 through the host connection unit 210 (step S232 of FIG. 6).
The card controller 214 upon receiving the read command RD_CMD reads data from the memory unit 216 in synchronism with an internal clock signal generated within the card controller 214 (step S234 of FIG. 6). In addition, the card controller 214 upon receiving the read command RD_CMD controls the read clock generator 222 to generate a read clock signal RD_CLK (step S236 of FIG. 6).
Subsequently, the memory card 204 transfers the read data generated by the card controller 214 from the memory unit 216 to the host 202 in synchronism with the read clock signal RD_CLK from the read clock generator 222 (step S238 of FIG. 6). To that end, the data flip flops CF1, CF2, and CFn in the card I/O circuit 218 are clocked with the read clock signal RD_CLK from the read clock generator 222 for latching such read data to the host 202 through the card connection unit 220.
In addition, the memory card 204 also transfers the read clock signal RD_CLK from the read clock generator 222 to the host 202 through the card connection unit 220 (step S238 of FIG. 6). The host 202 receives the read data and the read clock signal RD_CLK through the host connection unit 210 (step S240 of FIG. 6). The host I/O circuit 208 transfers such read data to the host controller 206 in synchronism with the received RD_CLK signal (step S240 of FIG. 6).
To that end, the data flip flops HF1, HF2, . . . , and HFn in the host I/O circuit 208 are clocked with the read clock signal RD_CLK received from the memory card 204 for latching such read data to the host controller 206 from the host connection unit 210. FIG. 7 illustrates a timing diagram of the read clock signal RD_CLK S50 and the read data S60 received at the host connection unit 210.
Referring to FIG. 7, the read clock signal RD_CLK S50 and the read data S60 are received at the host connection unit 210 with a transfer delay t6 between such signals S50 and S60. Such a transfer delay t6 may arise from the different signal paths for such signals S50 and S60. For example, the data path for the read data S60 may have a pad associated with a higher delay than the pad for the read clock signal RD_CLK S50. Alternatively, the data path for the read data S60 may be longer with higher time delay than the data path for the read clock signal RD_CLK S50.
In any case, a maximum allowable setup time t7 for the host I/O circuit 208 to transfer the read data S60 to the host controller 206 is from the end of the time delay t6 to the subsequent transition (i.e., Cl in FIG. 7) of the received read clock signal RD_CLK S50 when the flip flops HF1, HF2, . . . , and HFn latch the read data S60. Such a maximum allowable setup time t7 in FIG. 7 is advantageously longer than the maximum allowable setup time t5 in the prior art of FIG. 4.
The reason for such an increased maximum allowable setup time t7 in FIG. 7 is that the output delay t3=t1+t2 is eliminated with the memory card system 200 of FIG. 5 with the read clock signal RD_CLK being generated and transmitted from the memory card 202 for clocking the host I/O circuit 208. Such an increased maximum allowable setup time t7 in FIG. 7 is advantageous for increasing the operating frequency of the memory card system 200 according to an aspect of the present invention.
In addition, the read clock signal RD_CLK from the read clock generator 222 is transferred to the host 202 substantially only during a read operation when read data is also being transferred to the host 202 in one embodiment of the present invention. The card connection unit 220 may determine the time duration for sending such read data and read clock signal RD_CLK from an estimation of the size of the read data to be sent to the host 202. Alternatively, the host 202 may send an acknowledge command back to the card connection unit 220 indicating when all of the desired read data has been received by the host 202.
FIG. 8 shows a flow-chart of steps performed by the memory card system 200 of FIG. 5 for a write operation. Referring to FIGS. 5 and 8, the host 202 sends a write command WR_CMD, a write clock signal WR_CLK, and write data to be written to the memory card 204 through the host connection unit 210 (step S242 of FIG. 8). To that end, the host 202 includes a write clock signal generator 223 for generating the write clock signal WR_CLK.
Further referring to FIGS. 5 and 8, the data flip flops CF1, CF2, . . . , and CFn of the card I/O circuit 218 latch such write data received at the card connection unit 220 in synchronism to the write clock signal WR_CLK received at the card connection unit 220 (step S244 of FIG. 8). In addition, the card controller 214 receives such latched write data from the card I/O circuit 218 and writes the latched write data into the memory unit 216 in synchronism with an internal clock signal generated within the card controller 214 (step S246 of FIG. 8).
FIG. 9 shows a memory card system 500 according to an alternative embodiment of the present invention. Elements having the same reference number in FIGS. 5 and 11 refer to elements having similar structure and/or function. The memory card system 500 of FIG. 9 has a memory card 502 with a memory unit 504 including a first read clock signal generator 505 and with a card controller 506 having a second read clock signal generator 507.
When the memory unit 504 is transferring read data to the card controller 506, the memory unit 504 also transfers a first read clock signal RD_CLK1 from the first read clock signal generator 505 to the card controller 506. Thus, the card controller 506 and the memory unit 504 of FIG. 9 operate similarly for any read operation as already described between the host 202 and the card 204, respectively, for FIG. 5.
Similarly, when the card controller 506 is transferring read data to the card connection unit 220, the card controller 506 also transfers a second read clock signal RD_CLK2 from the second read clock signal generator 507 to the card connection unit 220. Thus, the card connection unit 220 and the card controller 506 of FIG. 9 operate similarly for any read operation as already described between the host 202 and the card 204, respectively, for FIG. 5.
The foregoing is by way of example only and is not intended to be limiting. For example, any number of elements as illustrated and described herein is by way of example. The present invention is limited only as defined in the following claims and equivalents thereof.
Patent Application
20080034142
