Patent Application
20080043736
The details of the present invention, both as to its structure and operation, may be gleaned in part by study of the accompanying drawings, in which like reference numerals refer to like parts, and in which:
Certain embodiments as disclosed herein provide for transmission of various types of data files through a private network without requiring “Write” permissions on the private network server. For example, one method as disclosed herein allows for transmission of data files of driving event information collected by fleet vehicles through a private fleet network and a public network such as the Internet to a driving event evaluation server.
After reading this description it will become apparent to one skilled in the art how to implement the invention in various alternative embodiments and alternative applications. However, although various embodiments of the present invention will be described herein, it is understood that these embodiments are presented by way of example only, and not limitation. As such, this detailed description of various alternative embodiments should not be construed to limit the scope or breadth of the present invention as set forth in the appended claims.
As illustrated in
User device 10 includes a data transmission system as illustrated in
Referring to
The message M1 is then sent by communication module 55 through the private network 15 and public network 18 to the communication module 56 at destination server 12 (step 30), as indicated in
Although steps 24 to 32 are shown as a sequence in
The messages M1, M2 . . . Mn are received at the destination server (step 34), and the data segment is extracted from each message by the processor module 58 (step 35). The original data file is then reconstructed from the extracted data segments (step 36), and the reconstructed data file is stored or further processed as desired, according to programmed instructions at the destination server.
This method allows file transfer to be executed across any number of private network OCSs or local servers without reconstructing or writing the file until the destination is reached. This will considerably simplify file transfer since there will be no need to have any intermediate write permissions at the OCSs. Successive segments of each data file are simply populated in the data payload of a series of network messages such as DIME messages which utilize the World Wide Web (www) Hypertext Transfer Protocol (HTTP) in the header. Since HTTP requests are usually allowed through firewalls, the network messages can be transmitted through any number of private networks without needing intermediate write permissions at the private network or OC servers. The file data is not distinguished from the rest of the data in the network message transmitted through the private network, and does not have to be reconstructed and written to any intermediate server of a private network, as is the normal rule for conventional data files. The remote server is configured to receive the series of messages associated with each file, and extract the sequence of data segments from the payloads of the messages before reconstructing/writing the file on the remote server.
As noted above, one situation where the method and system of this invention may be used is for evaluating driving data for an organization having a fleet of motor vehicles, although it is applicable to many different data collection scenarios where the collected data has to be transmitted to a remote server through one or more private networks. In the specific instance mentioned above, each vehicle in the fleet will have an on-board computer unit or user device linked to one or more driving event data collection devices, such as cameras and various sensors. Data from these devices is collected in a data storage area of the computer unit for subsequent transmission to the remote evaluation server for further analysis. The method and system of this invention allows such data to be transmitted in separate segments as the payload of a series of network messages, avoiding the need for write permissions on a private network such as the network of the organization having the fleet vehicles.
The user device 10 of
As noted above,
In the illustrated embodiment, wireless communication device 650 comprises an antenna 652, a multiplexor 654, a low noise amplifier (“LNA”) 656, a power amplifier (“PA”) 658, a modulation circuit 660, and a baseband processor 662. A central processing unit (“CPU”) 668 with a data storage area 670 is connected to the baseband processor 662, and a hardware interface 672 is connected to the baseband processor.
In the wireless communication device 650, radio frequency (“RF”) signals are transmitted and received by antenna 652. Multiplexor 654 acts as a switch, coupling antenna 652 between the transmit and receive signal paths. In the receive path, received RF signals are coupled from a multiplexor 654 to LNA 656. LNA 656 amplifies the received RF signal and couples the amplified signal to a demodulation portion of the modulation circuit 660.
Typically modulation circuit 660 will combine a demodulator and modulator in one integrated circuit (“IC”). The demodulator and modulator can also be separate components. The demodulator strips away the RF carrier signal leaving a base-band receive signal, which is sent from the demodulator output to the base-band processor 662.
The baseband processor 662 also codes digital signals for transmission and generates a baseband transmit signal that is routed to the modulator portion of modulation circuit 660. The modulator mixes the baseband transmit signal with an RF carrier signal generating an RF transmit signal that is routed to the power amplifier 658. The power amplifier 658 amplifies the RF transmit signal and routes it to the multiplexor 654 where the signal is switched to the antenna port for transmission by antenna 652.
The baseband processor 662 is also communicatively coupled with the central processing unit 668. The central processing unit 668 has access to data storage area 670. The central processing unit 668 is preferably configured to execute instructions (i.e., computer programs or software) that can be stored in the data storage area 670. Computer programs can also be received from the baseband processor 662 and stored in the data storage area 670 or executed upon receipt.
The central processing unit 668 is also preferably configured to receive notifications from the hardware interface 672 when new devices are detected by the hardware interface. Hardware interface 672 can be a combination electromechanical detector with controlling software that communicates with the CPU 668 and interacts with new devices. The hardware interface 672 may be a firewire port, a USB port, a Bluetooth or infrared wireless unit, or any of a variety of wired or wireless access mechanisms. Examples of hardware that may be linked with the device 650 include data storage devices, computing devices, headphones, microphones, and the like.
In this description, the term “computer readable medium” is used to refer to any media used to provide executable instructions (e.g., software and computer programs) to the wireless communication device 650 for execution by the central processing unit 668. Examples of these media include the data storage area 670, microphone 666 (via the baseband processor 662), antenna and multiplexor 654 (also via the baseband processor 662), and hardware interface 672. These computer readable mediums are means for providing executable code, programming instructions, and software to the wireless communication device 650. The executable code, programming instructions, and software, when executed by the central processing unit 668, preferably cause the central processing unit 668 to perform the inventive features and functions previously described herein. In other words, the central processing unit (CPU) at the user device is configured to create network messages and populate the data payload of such messages with successive configurable segments of data from a data file, while the CPU at the destination server is configured to extract the data segments from successive messages received at the destination server, reconstruct the original data file from the data segments, and write the data file to the server.
The central processing unit 668 is also preferably configured to receive notifications from the hardware interface 672 when new devices are detected by the hardware interface. Hardware interface 672 can be a combination electromechanical detector with controlling software that communicates with the CPU 668 and interacts with new devices. The hardware interface 672 may be a firewire port, a USB port, a Bluetooth or infrared wireless unit, or any of a variety of wired or wireless access mechanisms.
The computer system 750 preferably includes one or more processors, such as processor 752. Additional processors may be provided, such as an auxiliary processor to manage input/output, an auxiliary processor to perform floating point mathematical operations, a special-purpose microprocessor having an architecture suitable for fast execution of signal processing algorithms (e.g., digital signal processor), a slave processor subordinate to the main processing system (e.g., back-end processor), an additional microprocessor or controller for dual or multiple processor systems, or a coprocessor. Such auxiliary processors may be discrete processors or may be integrated with the processor 752.
The processor 752 is preferably connected to a communication bus 754. The communication bus 754 may include a data channel for facilitating information transfer between storage and other peripheral components of the computer system 750. The communication bus 754 further may provide a set of signals used for communication with the processor 752, including a data bus, address bus, and control bus (not shown). The communication bus 754 may comprise any standard or non-standard bus architecture such as, for example, bus architectures compliant with industry standard architecture (“ISA”), extended industry standard architecture (“EISA”), Micro Channel Architecture (“MCA”), peripheral component interconnect (“PCI”) local bus, or standards promulgated by the Institute of Electrical and Electronics Engineers (“IEEE”) including IEEE 488 general-purpose interface bus (“GPIB”), IEEE 696/S-100, and the like.
Computer system 750 preferably includes a main memory 756 and may also include a secondary memory 758. The main memory 756 provides storage of instructions and data for programs executing on the processor 752. The main memory 756 is typically semiconductor-based memory such as dynamic random access memory (“DRAM”) and/or static random access memory (“SRAM”). Other semiconductor-based memory types include, for example, synchronous dynamic random access memory (“SDRAM”), Rambus dynamic random access memory (“RDRAM”), ferroelectric random access memory (“FRAM”), and the like, including read only memory (“ROM”).
The secondary memory 758 may optionally include a hard disk drive 760 and/or a removable storage drive 762, for example a floppy disk drive, a magnetic tape drive, a compact disc (“CD”) drive, a digital versatile disc (“DVD”) drive, etc. The removable storage drive 762 reads from and/or writes to a removable storage medium 764 in a well-known manner. Removable storage medium 764 may be, for example, a floppy disk, magnetic tape, CD, DVD, etc.
The removable storage medium 764 is preferably a computer readable medium having stored thereon computer executable code (i.e., software) and/or data. The computer software or data stored on the removable storage medium 764 is read into the computer system 750 as electrical communication signals 778.
In alternative embodiments, secondary memory 758 may include other similar means for allowing computer programs or other data or instructions to be loaded into the computer system 750. Such means may include, for example, an external storage medium 772 and an interface 770. Examples of external storage medium 772 may include an external hard disk drive or an external optical drive, or and external magneto-optical drive.
Other examples of secondary memory 758 may include semiconductor-based memory such as programmable read-only memory (“PROM”), erasable programmable read-only memory (“EPROM”), electrically erasable read-only memory (“EEPROM”), or flash memory (block oriented memory similar to EEPROM). Also included are any other removable storage units 772 and interfaces 770, which allow software and data to be transferred from the removable storage unit 772 to the computer system 750.
Computer system 750 may also include a communication interface 774. The communication interface 774 allows software and data to be transferred between computer system 750 and external devices (e.g. printers), networks, or information sources. For example, computer software or executable code may be transferred to computer system 750 from a network server via communication interface 774. Examples of communication interface 774 include a modem, a network interface card (“NIC”), a communications port, a PCMCIA slot and card, an infrared interface, and an IEEE 1394 fire-wire, just to name a few.
Communication interface 774 preferably implements industry promulgated protocol standards, such as Ethernet IEEE 802 standards, Fiber Channel, digital subscriber line (“DSL”), asynchronous digital subscriber line (“ADSL”), frame relay, asynchronous transfer mode (“ATM”), integrated digital services network (“ISDN”), personal communications services (“PCS”), transmission control protocol/Internet protocol (“TCP/IP”), serial line Internet protocol/point to point protocol (“SLIP/PPP”), and so on, but may also implement customized or non-standard interface protocols as well.
Software and data transferred via communication interface 774 are generally in the form of electrical communication signals 778. These signals 778 are preferably provided to communication interface 774 via a communication channel 776. Communication channel 776 carries signals 778 and can be implemented using a variety of wired or wireless communication means including wire or cable, fiber optics, conventional phone line, cellular phone link, wireless data communication link, radio frequency (RF) link, or infrared link, just to name a few.
Computer executable code (i.e., computer programs or software) is stored in the main memory 756 and/or the secondary memory 758. Computer programs can also be received via communication interface 774 and stored in the main memory 756 and/or the secondary memory 758. Such computer programs, when executed, enable the computer system 750 to perform the various functions of the present invention as previously described.
In this description, the term “computer readable medium” is used to refer to any media used to provide computer executable code (e.g., software and computer programs) to the computer system 750. Examples of these media include main memory 756, secondary memory 758 (including hard disk drive 760, removable storage medium 764, and external storage medium 772), and any peripheral device communicatively coupled with communication interface 774 (including a network information server or other network device). These computer readable mediums are means for providing executable code, programming instructions, and software to the computer system 750.
In an embodiment that is implemented using software, the software may be stored on a computer readable medium and loaded into computer system 750 by way of removable storage drive 762, interface 770, or communication interface 774. In such an embodiment, the software is loaded into the computer system 750 in the form of electrical communication signals 778. The software, when executed by the processor 752, preferably causes the processor 752 to perform the inventive features and functions previously described herein.
Various embodiments may also be implemented primarily in hardware using, for example, components such as application specific integrated circuits (“ASICs”), or field programmable gate arrays (“FPGAs”). Implementation of a hardware state machine capable of performing the functions described herein will also be apparent to those skilled in the relevant art. Various embodiments may also be implemented using a combination of both hardware and software.
Furthermore, those of skill in the art will appreciate that the various illustrative logical blocks, modules, and method steps described in connection with the above described figures and the embodiments disclosed herein can often be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative blocks, modules, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the overall system. Skilled persons can implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the invention. In addition, the grouping of functions within a module, block, or step is for ease of description. Specific functions or steps can be moved from one module, block or step to another without departing from the invention.
Moreover, the various illustrative logical blocks, modules, and methods described in connection with the embodiments disclosed herein can be implemented or performed with a general purpose processor, a digital signal processor (“DSP”), an ASIC, FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general-purpose processor can be a microprocessor, but in the alternative, the processor can be any processor, controller, microcontroller, or state machine. A processor can also be implemented as a combination of computing devices, for example, a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.
Additionally, the steps of a method or algorithm described in connection with the embodiments disclosed herein can be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module can reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium including a network storage medium. An exemplary storage medium can be coupled to the processor such the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium can be integral to the processor. The processor and the storage medium can also reside in an ASIC.
The above description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles described herein can be applied to other embodiments without departing from the spirit or scope of the invention. Thus, it is to be understood that the description and drawings presented herein represent a presently preferred embodiment of the invention and are therefore representative of the subject matter which is broadly contemplated by the present invention. It is further understood that the scope of the present invention fully encompasses other embodiments that may become obvious to those skilled in the art and that the scope of the present invention is accordingly limited by nothing other than the appended claims.
