DATA TRANSMISSION CIRCUIT SYSTEM AND DATA RECEPTION CIRCUIT SYSTEM USING EDGE OF PULSE SIGNAL

Abstract

Provided are a data transmission circuit system and a data reception circuit system, which use an edge of a pulse signal. The data transmission circuit system modulates a digital signal by using time levels determined by time differences between rising edges (or falling edges) of a clock pulse signal and rising edges (or falling edges) of a data pulse signal. The data reception circuit system demodulates a digital signal by using time levels determined by time differences between rising edges (or falling edges) of a recovered clock pulse signal and rising edges (or falling edges) of a data pulse signal.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based on and claims priority under 35 U.S.C. § 119 to Korean Patent Application Nos. 10-2024-0005678, filed on Jan. 12, 2024, 10-2024-0007533, filed on Jan. 17, 2024, 10-2024-0032055, filed on Mar. 6, 2024, and 10-2024-0070999, filed on May 30, 2024, in the Korean Intellectual Property Office, the disclosures of which are incorporated by reference herein in their entirety.

BACKGROUND

1. Field

The disclosure relates to a data transmission circuit system and a data reception circuit system. More particularly, the disclosure relates to a circuit system for transmitting and receiving data by using a time level.

2. Description of the Related Art

Examples of digital data modulation methods in data transmission include non-return-to-zero (NRZ) and pulse amplitude modulation (PAM). NRZ and PAM are methods of encoding digital data at different amplitude levels (i.e., voltage levels) of pulses. NRZ encodes digital data by using amplitude levels represented by “0” and “1”. PAM is classified into pulse amplitude modulation 2-levels (PAM2), pulse amplitude modulation 4-levels (PAM4), etc., depending on the number of amplitude levels. NRZ and PAM require an analog-to-digital converter (ADC) and a digital-to-analog converter (DAC) with high power consumption in order to modulate and demodulate amplitude of pulses.

SUMMARY

Provided are a data transmission circuit system and a data reception circuit system using an edge of a pulse signal.

Additional aspects will be set forth in part in the description which follows and, in part, will be apparent from the description, or may be learned by practice of the presented embodiments of the disclosure.

According to an aspect of the disclosure, provided is a data transmission circuit system.

The data transmission circuit system according to an embodiment includes a data pulse generation circuit configured to receive a digital signal and generate, based on a clock pulse signal, a data pulse signal with a first type edge of a time level corresponding to the digital signal, a clock pulse generation circuit configured to generate the clock pulse signal with a first type edge of a base time level that is a basis of the time level, and a transmission interface circuit configured to transmit the data pulse signal, wherein a time difference between a first type edge of the clock pulse signal and a first type edge of the data pulse signal indicates the time level.

According to an embodiment, the data pulse generation circuit may be further configured to generate the data pulse signal by delaying the clock pulse signal according to the time level corresponding to the digital signal.

According to an embodiment, the clock pulse generation circuit may be further configured to generate a plurality of clock pulse signals with different phases, and the data pulse generation circuit may be further configured to generate sub-data pulse signals by respectively delaying the plurality of clock pulse signals according to time levels corresponding to the digital signal, and generate the data pulse signal by combining the sub-data pulse signals with each other.

According to an embodiment, the data pulse generation circuit may include a serialization circuit configured to generate a digital stream signal by serializing the digital signal, and a digital-time conversion circuit configured to generate the data pulse signal by delaying the clock pulse signal according to a time level corresponding to the digital stream signal.

According to an embodiment, the data pulse generation circuit may include an equalization circuit configured to adjust a delay of a pulse of the clock pulse signal of a current symbol, based on a value of the digital stream signal of a previous symbol and a value of the digital stream signal of the current symbol.

According to an embodiment, the clock pulse generation circuit may be further configured to generate a first clock pulse signal with a first phase and a second clock pulse signal with a second phase, and the data pulse generation circuit may include a serialization circuit configured to generate a first digital stream signal and a second digital stream signal by serializing and distributing the digital signal, a first digital-time conversion circuit configured to generate a first sub-data pulse signal by delaying the first clock pulse signal according to a time level corresponding to the first digital stream signal, a second digital-time conversion circuit configured to generate a second sub-data pulse signal by delaying the second clock pulse signal according to a time level corresponding to the second digital stream signal, and a data pulse combining circuit configured to generate the data pulse signal by combining the first sub-data pulse signal with the second sub-data pulse signal such that the data pulse signal includes a first type edge of the first sub-data pulse signal and a first type edge of the second sub-data pulse signal.

According to an embodiment, the clock pulse generation circuit may be further configured to generate a first clock pulse signal with a first phase, a second clock pulse signal with a second phase, a third clock pulse signal with a third phase, and a fourth clock pulse signal with a fourth phase, and the data pulse generation circuit may include a serialization circuit configured to generate a first digital stream signal, a second digital stream signal, a third digital stream signal, and a fourth digital stream signal by serializing and distributing the digital signal, a first digital-time conversion circuit configured to generate a first sub-data pulse signal by delaying the first clock pulse signal according to a time level corresponding to the first digital stream signal, a second digital-time conversion circuit configured to generate a second sub-data pulse signal by delaying the second clock pulse signal according to a time level corresponding to the second digital stream signal, a third digital-time conversion circuit configured to generate a third sub-data pulse signal by delaying the third clock pulse signal according to a time level corresponding to the third digital stream signal, a fourth digital-time conversion circuit configured to generate a fourth sub-data pulse signal by delaying the fourth clock pulse signal according to a time level corresponding to the fourth digital stream signal, and a data pulse combining circuit configured to generate the data pulse signal by combining the first sub-data pulse signal, the second sub-data pulse signal, the third sub-data pulse signal, and the fourth sub-data pulse signal with each other such that the data pulse signal includes a first type edge of the first sub-data pulse signal, a first type edge of the second sub-data pulse signal, a first type edge of the third sub-data pulse signal, and a first type edge of the fourth sub-data pulse signal.

According to an embodiment, an interval between a plurality of time levels indicated by pulses of the data pulse signal may be less than 1 ns.

According to an embodiment, the first type edge may be one of a rising edge and a falling edge.

According to another aspect of the disclosure, provided is a data transmission method.

A data transmission method according to an embodiment includes receiving a digital signal, generating a clock pulse signal with a first type edge of a base time level that is a basis of a time level, generating, based on the clock pulse signal, a data pulse signal with a first type edge of a time level corresponding to the digital signal, and transmitting the data pulse signal, wherein a time difference between a first type edge of the clock pulse signal and a first type edge of the data pulse signal indicates the time level.

According to another aspect of the disclosure, provided is a data reception circuit system.

The data reception circuit system according to an embodiment includes a reception interface circuit configured to receive a data pulse signal, a digital signal generation circuit configured to generate, based on a recovered clock pulse signal, a digital signal corresponding to a time level of a first type edge of the data pulse signal, and a clock recovery circuit configured to generate the recovered clock pulse signal with a first type edge of a base time level that is a basis of the time level, wherein a time difference between a first type edge of the recovered clock pulse signal and a first type edge of the data pulse signal determines the time level.

According to an embodiment, the digital signal generation circuit includes a time-digital conversion circuit configured to generate a digital stream signal corresponding to a time level of the data pulse signal, and a parallelization circuit configured to generate the digital signal by parallelizing the digital stream signal.

According to an embodiment, the time-digital conversion circuit includes an equalization circuit configured to adjust a delay of a pulse of the recovered clock pulse signal of a current symbol or a delay of a pulse of the data pulse signal of the current symbol, based on a value of the digital stream signal of a previous symbol.

According to an embodiment, the clock recovery circuit includes a clock pulse separation circuit configured to separate the recovered clock pulse signal into a first sub-clock pulse signal and a second sub-clock pulse signal such that the first sub-clock pulse signal and the second sub-clock pulse signal alternately include pulses of the recovered clock pulse signal, and the digital signal generation circuit includes a data pulse separation circuit configured to separate the data pulse signal into a first sub-data pulse signal and a second sub-data pulse signal such that the first sub-data pulse signal and the second sub-data pulse signal alternately include pulses of the data pulse signal, a first time-digital conversion circuit configured to generate a first digital stream signal corresponding to a time level determined by a time difference between a first type edge of the first sub-clock pulse signal and a first type edge of the first sub-data pulse signal, a second time-digital conversion circuit configured to generate a second digital stream signal corresponding to a time level determined by a time difference between a first type edge of the second sub-clock pulse signal and a first type edge of the second sub-data pulse signal, and a parallelization circuit configured to generate the digital signal by merging and parallelizing the first digital stream signal and the second digital stream signal.

According to an embodiment, the clock recovery circuit includes a clock pulse separation circuit configured to separate the recovered clock pulse signal into a first sub-clock pulse signal, a second sub-clock pulse signal, a third sub-clock pulse signal, and a fourth sub-clock pulse signal such that the first sub-clock pulse signal, the second sub-clock pulse signal, the third sub-clock pulse signal, and the fourth sub-clock pulse signal alternately include pulses of the recovered clock pulse signal, and the digital signal generation circuit includes a data pulse separation circuit configured to separate the data pulse signal into a first sub-data pulse signal, a second sub-data pulse signal, a third sub-data pulse signal, and a fourth sub-data pulse signal such that the first sub-data pulse signal, the second sub-data pulse signal, the third sub-data pulse signal, and the fourth sub-data pulse signal alternately include pulses of the data pulse signal, a first time-digital conversion circuit configured to generate a first digital stream signal corresponding to a time level determined by a time difference between a first type edge of the first sub-clock pulse signal and a first type edge of the first sub-data pulse signal, a second time-digital conversion circuit configured to generate a second digital stream signal corresponding to a time level determined by a time difference between a first type edge of the second sub-clock pulse signal and a first type edge of the second sub-data pulse signal, a third time-digital conversion circuit configured to generate a third digital stream signal corresponding to a time level determined by a time difference between a first type edge of the third sub-clock pulse signal and a first type edge of the third sub-data pulse signal, a fourth time-digital conversion circuit configured to generate a fourth digital stream signal corresponding to a time level determined by a time difference between a first type edge of the fourth sub-clock pulse signal and a first type edge of the fourth sub-data pulse signal, and a parallelization circuit configured to generate the digital signal by merging and parallelizing the first digital stream signal, the second digital stream signal, the third digital stream signal, and the fourth digital stream signal.

According to an embodiment, the clock recovery circuit may be further configured to generate the recovered clock pulse signal by receiving a forward clock signal and delaying the forward clock signal such that a first type edge of the forward clock signal is located at the base time level.

According to an embodiment, the clock recovery circuit may include a delay locked loop circuit configured to receive a forward clock signal and output the recovered clock pulse signal by delaying the forward clock signal, wherein the delay locked loop circuit may include a feedback loop, and the delay locked loop circuit may be configured to delay the forward clock signal, based on a phase difference between a feedback signal of the feedback loop and the data pulse signal.

According to an embodiment, the base time level may be located between two middle time levels of a plurality of time levels determined by pulses of the recovered clock pulse signal and pulses of the data pulse signal.

According to an embodiment, the first type edge may be one of a rising edge and a falling edge.

According to another aspect of the disclosure, provided is a data reception method.

A data reception method according to an embodiment includes receiving a data pulse signal, generating a recovered clock pulse signal with a first type edge of a base time level that is a basis of a time level, and generating, based on the recovered clock pulse signal, a digital signal corresponding to a time level of a first type edge of the data pulse signal, wherein a time difference between a first type edge of the recovered clock pulse signal and a first type edge of the data pulse signal determines the time level.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other aspects, features, and advantages of certain embodiments of the disclosure will be more apparent from the following description taken in conjunction with the accompanying drawings, in which:

FIG. 1A is a schematic eye diagram of a non-return-to-zero (NRZ) signal;

FIG. 1B is a schematic eye diagram of a pulse amplitude modulation 4-levels (PAM4) signal;

FIGS. 2A and 2B are schematic eye diagrams of a data pulse signal according to embodiments;

FIGS. 3A to 3D are schematic diagrams of a base time level and time levels according to embodiments;

FIG. 4 is a block diagram of a first circuit system and a second circuit system, according to an embodiment;

FIG. 5 is a block diagram of a data transmission circuit system and a data reception circuit system, according to an embodiment;

FIGS. 6A and 6B are diagrams for describing a data pulse signal in which a digital signal is encoded, according to embodiments;

FIGS. 7A and 7B are diagrams for describing a digital signal obtained by decoding a data pulse signal, according to embodiments;

FIG. 8A is a block diagram of a data transmission circuit system according to an embodiment;

FIGS. 8A to 8D are diagrams for describing a digital stream signal supplied by a serialization circuit to a digital-time conversion circuit, according to embodiments;

FIGS. 9A and 9B are circuit diagrams of a digital-time conversion circuit according to embodiments;

FIG. 10 is a block diagram of a data transmission circuit system according to an embodiment;

FIGS. 11A and 11B are circuit diagrams of a digital-time conversion circuit and an equalization circuit, according to embodiments;

FIGS. 12A and 12B are graphs of a channel response of a pulse signal, according to embodiments;

FIG. 13 is a block diagram of a data transmission circuit system according to an embodiment;

FIG. 14 is a diagram for describing an operation of a data pulse combining circuit, according to an embodiment;

FIG. 15 is a block diagram of a data transmission circuit system according to an embodiment;

FIG. 16 is a diagram for describing an operation of a data pulse combining circuit, according to an embodiment;

FIGS. 17A and 17B are eye diagrams of a PAM4 signal;

FIGS. 17C and 17D are eye diagrams of a data pulse signal according to an embodiment;

FIG. 18A is a block diagram of a data reception circuit system according to an embodiment;

FIGS. 18B to 18D are diagrams for describing a digital stream signal supplied by a time-digital conversion circuit to a parallelization circuit, according to embodiments;

FIG. 19A is a diagram for describing a clock recovery circuit according to an embodiment;

FIGS. 19B and 19C are schematic diagrams of a mechanism for generating a recovered clock pulse signal, according to embodiments;

FIG. 20A is a block diagram of a delay locked loop circuit according to an embodiment;

FIG. 20B is a graph of a voltage signal according to an embodiment;

FIGS. 20C and 20D are schematic eye diagrams of a recovered clock pulse signal and a data pulse signal, according to embodiments;

FIG. 21A is a block diagram of a delay locked loop circuit according to an embodiment;

FIG. 21B is a block diagram of a voltage controlled delay line (VCDL) according to an embodiment;

FIG. 22A is a block diagram of a data reception circuit system according to an embodiment;

FIG. 22B is a diagram for describing operations of a time-digital conversion circuit and an equalization circuit, according to an embodiment;

FIG. 23A is a block diagram of a data reception circuit system according to an embodiment;

FIG. 23B is a diagram for describing a clock pulse separation circuit and a data pulse separation circuit, according to an embodiment;

FIG. 24 is a diagram for describing operations of a first time-digital conversion circuit and a second time-digital conversion circuit, according to an embodiment;

FIGS. 25 and 26 are block diagrams of a data reception circuit system according to embodiments;

FIG. 27 is a flowchart of a data transmission method according to an embodiment; and

FIG. 28 is a flowchart of a data reception method according to an embodiment.

DETAILED DESCRIPTION

The terms used in the specification will be briefly defined, and the disclosure will be described in detail. Throughout the disclosure, the expression “at least one of a, b, or c” indicates only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, or variations thereof. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.

All terms including descriptive or technical terms which are used herein should be construed as having meanings that are obvious to one of ordinary skill in the art. However, the terms may have different meanings according to the intention of one of ordinary skill in the art, precedent cases, or the appearance of new technologies. Also, some terms may be arbitrarily selected by the applicant, and in this case, the meaning of the selected terms will be described in detail in the detailed description. Thus, the terms used herein have to be defined based on the meaning of the terms together with the description throughout the specification.

An expression used in the singular may encompass the expression in the plural, unless it has a clearly different meaning in the context. Terms used herein, including technical or scientific terms, may have the same meaning as commonly understood by one of ordinary skill in the art described in the disclosure. Further, the terms including ordinal numbers such as “first”, “second”, and the like used in the present specification may be used to describe various components, but the components should not be limited by the terms. The above terms are used only to distinguish one component from another.

When a part “includes” or “comprises” an element, unless there is a particular description contrary thereto, the part may further include other elements, not excluding the other elements.

In the disclosure, a voltage level may denote a level of a voltage used to transmit or receive data. For example, non-return-to-zero (NRZ) may use two types of voltage levels, i.e., a low level and a high level, wherein the low level may indicate “0” and the high level may indicate “1”. For example, pulse amplitude modulation 4-levels (PAM4) may use four voltage levels and the voltage levels may indicate “00”, “01”, “10”, and “11”.

In the disclosure, a “time level” may denote a level of time used to transmit or receive data. For example, 2ⁿ time levels may be used to transmit or receive data of n bits. For example, two time levels may be used to transmit or receive data of 1 bit, four time levels may be used to transmit or receive data of 2 bits, and eight time levels may be used to transmit or receive data of 3 bits.

In the disclosure, a “base time level” may denote a level that is a basis of time levels.

Hereinafter, embodiments will be described in detail with reference to the accompanying drawings such that one of ordinary skill in the art may easily implement the embodiments. However, the disclosure may be implemented in various different forms and is not limited to the embodiments described herein.

Hereinafter, the disclosure will be described in detail with reference to accompanying drawings.

FIG. 1A is a schematic eye diagram of an NRZ signal, and FIG. 1B is a schematic eye diagram of a PAM4 signal.

Referring to FIG. 1A, the NRZ transmits data by using two types of voltage levels of a low level 101 and a high level 102. For example, a bit “0” is encoded at the low level 101 and a bit “1” is encoded at the high level 102.

Referring to FIG. 1B, PAM4 transmits data by using four types of voltage levels of first to fourth voltage levels 111 to 114. For example, a bit “00” is encoded at a first voltage level 111, a bit “01” is encoded at a second voltage level 112, a bit “10” is encoded at a third voltage level 113, and a bit “11” is encoded at a fourth voltage level.

In NRZ and PAM4, a digital-to-analog converter (DAC) is used to convert digital data into an NRZ signal or a PAM4 signal. Also, in NRZ and PAM4, an analog-to-digital converter (ADC) is used to convert an NRZ signal or a PAM4 signal into digital data. Accordingly, NRZ and PAM4 require resources for the ADC and the DAC.

Compared to NRZ, PAM4 has two times greater data rate in a same symbol rate and symbol period. However, in PAM4, data is encoded at four voltage levels, and thus, encoding resolution decreases when an operating voltage decreases.

FIGS. 2A and 2B are schematic eye diagrams of a data pulse signal according to embodiments.

In the disclosure, time levels may be used to transmit and receive data. The time levels may be represented by rising edges (or falling edges) of a data pulse signal. In order to transmit data, a pulse with a rising edge (or a falling edge) located at a time level corresponding to the data may be generated. In order to receive data, the data may be decoded from a time level where a rising edge (or a falling edge) of a pulse is located.

A time level may be defined by a time difference between a rising edge (or a falling edge) of a clock pulse signal and a rising edge (or a falling edge) of a data pulse signal.

When a timepoint of the rising edge (or the falling edge) of the clock pulse signal is referred to as a base time level, each time level may have a pre-determined time difference with the base time level.

According to an embodiment, a time interval between the base time level and the time level may be less than a period of the clock pulse signal. Also, a time interval between the time levels may be less than a period of the clock pulse signal. For example, for the clock pulse signal of 1 GHz, an interval between the time levels may be less than 1 ns.

According to an embodiment, when the data pulse signal is generated as m clock pulse signals are time-interleaved, a time interval between the base time level and the time level may be less than (period)/m of the clock pulse signal. Also, the time interval between the time levels may be less than (period)/m of the clock pulse signal. For example, when the data pulse signal is generated by interleaving four clock pulse signals of 4 GHz, the interval between the time levels may be less than 62.5 ps.

Referring to FIG. 2A, according to an embodiment, first to fourth time levels 201 to 204 may be used to transmit and receive data of 2 bits. A bit “00” may correspond to the first time level 201, a bit “01” may correspond to the second time level 202, a bit “10” may correspond to a third time level 203, and a bit “11” may correspond to a fourth time level 204.

Data is encoded to the time level of the rising edge (or the falling edge) of the data pulse signal, and thus, a time difference between the rising edge and the falling edge of the data pulse signal, i.e., a pulse width, may not be directly related to the encoded data. Accordingly, the data pulse signal may be generated to have a consistent pulse width or may be generated to have an inconsistent pulse width. For example, an eye diagram of the data pulse signal with a consistent pulse width may be illustrated as FIG. 2A, and an eye diagram of the data pulse signal with an inconsistent pulse width and consistent falling edges of timepoints may be illustrated as FIG. 2B.

In the disclosure, an edge of a pulse is used to transmit or receive data, and thus, ADC or DAC for modulating or demodulating amplitude of the pulse are not required and data may be encoded and decoded with high resolution even in a low operating voltage.

FIGS. 3A to 3D are schematic diagrams of a base time level and time levels according to embodiments.

According to an embodiment, a base time level may be the first time level from among time levels. For example, when data of n bits is encoded to first to (2ⁿ)th time levels, the first time level may be a base time level.

Referring to FIG. 3A, according to an embodiment, a data pulse signal may include first to fourth data pulses 301 to 304 in which data is encoded to a rising edge. The first to fourth data pulses 301 to 304 may respectively have first to fourth time levels. In detail, a rising edge of the first data pulse 301 may be located in the first time level, i.e., a base time level 300, a rising edge of the second data pulse 302 may be located in the second time level, a rising edge of the third data pulse 303 may be located in the third time level, and a rising edge of the fourth data pulse 304 may be located in the fourth time level.

Referring to FIG. 3B, according to an embodiment, a data pulse signal may include first to fourth data pulses 311 to 314 in which data is encoded to a falling edge. The first to fourth data pulses 311 to 314 may respectively have first to fourth time levels. In detail, a falling edge of the first data pulse 311 may be located in the first time level, i.e., a base time level 310, a falling edge of the second data pulse 312 may be located in the second time level, a falling edge of the third data pulse 313 may be located in the third time level, and a falling edge of the fourth data pulse 314 may be located in the fourth time level.

According to an embodiment, a base time level may be located between two middle time levels among time levels. For example, when data of n bits is encoded to first to (2ⁿ)th time levels, the base time level may be located between the (2^n-1)th time level and the (2^n-1)th time level.

Referring to FIG. 3C, according to an embodiment, a data pulse signal may include first to fourth data pulses 321 to 324 in which data is encoded to a rising edge. Rising edges of the first to fourth data pulses 321 to 324 may be respectively located in first to fourth time levels, and a base time level 320 may be located between the second and third time levels.

Referring to FIG. 3D, according to an embodiment, a data pulse signal may include first to fourth data pulses 331 to 334 in which data is encoded to a falling edge. Falling edges of the first to fourth data pulses 331 to 334 may be respectively located in first to fourth time levels, and a base time level 330 may be located between the second and third time levels.

A base time level is a level that is a basis of time levels, may have various locations on a time axis, and is not limited by embodiments described with reference to FIGS. 3A to 3D.

FIG. 4 is a block diagram of a first circuit system 410 and a second circuit system 420, according to an embodiment.

According to an embodiment, the first circuit system 410 and the second circuit system 420 may transmit and receive data, based on a time level. The first circuit system 410 may include a data transmission circuit system 411 and the second circuit system 420 may include a data reception circuit system 421. The data transmission circuit system 411 may generate a data pulse signal by modulating a digital signal and transmit the data pulse signal. The data reception circuit system 421 may receive the data pulse signal that has passed through a channel 430 and generate the digital signal by demodulating the data pulse signal.

According to an embodiment, the first circuit system 410 and the second circuit system 420 may each include a semiconductor die, and the data transmission circuit system 411 and the data reception circuit system 421 may provide a die-to-die interface.

According to an embodiment, the first circuit system 410 and the second circuit system 420 may each include an integrated chip (IC), and the data transmission circuit system 411 and the data reception circuit system 421 may provide an IC interface.

According to an embodiment, the first circuit system 410 and the second circuit system 420 may each include a chiplet, and the data transmission circuit system 411 and the data reception circuit system 421 may provide a chiplet interface.

According to an embodiment, the first circuit system 410 and the second circuit system 420 may each include a semiconductor package, and the data transmission circuit system 411 and the data reception circuit system 421 may provide a semiconductor package interface.

According to an embodiment, the first circuit system 410 and the second circuit system 420 may each include a multi-chip module (MCM), and the data transmission circuit system 411 and the data reception circuit system 421 may provide an MCM interface.

According to an embodiment, the first circuit system 410 and the second circuit system 420 may each include a system-in-package (SiP), and the data transmission circuit system 411 and the data reception circuit system 421 may provide a SIP interface.

According to an embodiment, the first circuit system 410 and the second circuit system 420 may each include a system-on-chip (SoC), and the data transmission circuit system 411 and the data reception circuit system 421 may provide an SoC interface.

According to an embodiment, the first circuit system 410 and the second circuit system 420 may each include a 2.5D-IC, and the data transmission circuit system 411 and the data reception circuit system 421 may provide a 2.5D-IC interface.

According to an embodiment, the first circuit system 410 and the second circuit system 420 may each include an 3D-IC, and the data transmission circuit system 411 and the data reception circuit system 421 may provide a 3D-IC interface.

According to an embodiment, the first circuit system 410 and the second circuit system 420 may each include at least one of a semiconductor die, an IC, a chiplet, a semiconductor package, an MCM, a SiP, an SoC, a 2.5D-IC, or a 3D-IC, and the data transmission circuit system 411 and the data reception circuit system 421 may provide an interface therebetween.

Although not illustrated in FIG. 4, the first circuit system 410 may further include a data reception circuit system and the second circuit system 420 may further include a data transmission circuit system.

According to an embodiment, the first circuit system 410 and the second circuit system 420 may be included in an electronic device. The electronic device may include at least one processor and a memory, and may be any device in which the at least one processor is configured to execute one or more instructions stored in the memory. For example, the electronic device may be a computer, a personal computer (PC), a laptop PC, a tablet PC, a smartphone, a wearable device, a home appliance, an office electronic device, or an experimental electronic device, but is not limited thereto. For example, the electronic device may be a device mounted on at least one of a vehicle, an electric vehicle, an autonomous vehicle, an aircraft, a spacecraft, or a robot.

FIG. 5 is a block diagram of a data transmission circuit system 510 and a data reception circuit system 520, according to an embodiment.

The data transmission circuit system 510 according to an embodiment includes a data pulse generation circuit 511, a clock pulse generation circuit 512, and a transmission interface circuit 513.

The data pulse generation circuit 511 may be configured to receive a digital signal and generate a data pulse signal with time levels corresponding to the digital signal, based on a clock pulse signal. The clock pulse generation circuit 512 may be configured to generate the clock pulse signal with a base time level that is a basis of time levels. The transmission interface circuit 513 may be configured to transmit the data pulse signal.

Referring to FIG. 6A, an embodiment in which a digital signal is encoded to a rising edge of a data pulse signal will be described. According to an embodiment, “00” corresponds to a first time level, “01” corresponds to a second time level, “10” corresponds to a third time level, and “11” corresponds to a fourth time level. The digital signal is “00011011” and 2 bits of the digital signal are encoded to one pulse of the data pulse signal per symbol. The data pulse signal in which the digital signal is encoded includes a pulse 601 with a rising edge of the first time level in which “00” is encoded, a pulse 602 with a rising edge of the second time level in which “01” is encoded, a pulse 603 with a rising edge of the third time level in which “10” is encoded, and a pulse 604 with a rising edge of the fourth time level in which “11” is encoded. Here, a clock pulse signal includes a pulse with a rising edge of a base time level, and a time difference between a rising edge of the clock pulse signal and the rising edge of the data pulse signal in each symbol indicates a time level.

Then, referring to FIG. 6B, an embodiment in which a digital signal is encoded to a falling edge of a data pulse signal will be described. According to an embodiment, the data pulse signal in which the digital signal is encoded includes a pulse 611 with a falling edge of the first time level in which “00” is encoded, a pulse 612 with a falling edge of the second time level in which “01” is encoded, a pulse 613 with a falling edge of the third time level in which “10” is encoded, and a pulse 614 with a falling edge of the fourth time level in which “11” is encoded. Here, a clock pulse signal includes a pulse with a falling edge of a base time level, and a time difference between a falling edge of the clock pulse signal and the falling edge of the data pulse signal in each symbol indicates a time level.

Referring back to FIG. 5, the data reception circuit system 520 according to an embodiment includes a digital signal generation circuit 521, a clock recovery circuit 522, and a reception interface circuit 523.

The reception interface circuit 523 may be configured to receive the data pulse signal that has passed through a channel 530. The digital signal generation circuit 521 may be configured to generate the digital signal corresponding to time levels of the data pulse signal, based on a recovered clock pulse signal. The clock recovery circuit 522 may be configured to generate the recovered clock pulse signal with a base time level that is a basis of time levels.

Referring to FIG. 7A, an embodiment in which a digital signal is decoded from a rising edge of a data pulse signal will be described. According to an embodiment, a first time level corresponds to “00” of the digital signal, a second time level corresponds to “01” of the digital signal, a third time level corresponds to “10” of the digital signal, and a fourth time level corresponds to “11” of the digital signal. Pulses 701 to 704 of the data pulse signal respectively have first to fourth time levels, and 2 bits of digital signal are decoded from one pulse of the data pulse signal per symbol. In detail, “00” is decoded from the pulse 701 with a rising edge of the first time level of the data pulse signal, “01” is decoded from the pulse 702 with a rising edge of the second time level, “10” is decoded from the pulse 703 with a rising edge of the third time level, and “11” is decoded from the pulse 704 with a rising edge of the fourth time level. Here, a recovered clock pulse signal includes a pulse with a rising edge of a base time level, and a time level may be determined from a time difference between a rising edge of the recovered clock pulse signal and the rising edge of the data pulse signal in each symbol.

Then, referring to FIG. 7B, an embodiment in which a digital signal is decoded from a falling edge of a data pulse signal will be described. According to an embodiment, “00” is decoded from a pulse 711 with a falling edge of a first time level of the data pulse signal, “01” is decoded from a pulse 712 with a falling edge of a second time level, “10” is decoded from a pulse 713 with a falling edge of a third time level, and “11” is decoded from a pulse 714 with a falling edge of a fourth time level. Here, a recovered clock pulse signal includes a pulse with a falling edge of a base time level, and a time level may be determined from a time difference between a falling edge of the recovered clock pulse signal and the falling edge of the data pulse signal in each symbol.

FIG. 8A is a block diagram of a data transmission circuit system 800 according to an embodiment.

The data transmission circuit system 800 according to an embodiment includes a data pulse generation circuit 810, a clock pulse generation circuit 820, and a transmission interface circuit 830. The data pulse generation circuit 810 includes a serialization circuit 811 and a digital-time conversion circuit 812.

According to an embodiment, the clock pulse generation circuit 820 may generate clock signals CLK1 and CLK2 required for an operation of the data transmission circuit system 800, based on a base clock signal CLK0. The clock signal CLK1 may be used for an operation of the serialization circuit 811 and the clock pulse signal CLK2 may be used for an operation of the digital-time conversion circuit 812.

According to an embodiment, the clock pulse generation circuit 820 may generate a forward clock signal CLK3 required for an operation of a data reception circuit system. The forward clock signal CLK3 may be forwarded to the data reception circuit system together with a data pulse signal DPS.

The clock pulse generation circuit 820 may generate the clock signals CLK1 to CLK3 by changing a frequency and/or a phase of the base clock signal CLK0. In this regard, the clock pulse generation circuit 820 may include at least one of a frequency divider, a frequency multiplier, a frequency converter, or a delay circuit.

The serialization circuit 811 may receive a digital signal DS and generate a digital stream signal DSS by serializing the digital signal DS. The serialization circuit 811 may serialize the digital signal DS, based on the clock signal CLK1. The digital stream signal DSS may be supplied to the digital-time conversion circuit 812.

The serialization circuit 811 may distribute the digital stream signal DSS according to the number of bits per symbol and supply the same to the digital-time conversion circuit 812.

Referring to FIG. 8B, when the number of bits per symbol is 1, the serialization circuit 811 may supply the digital stream signal DSS to the digital-time conversion circuit 812. The digital-time conversion circuit 812 may generate a pulse with a time level corresponding to 1 bit of the digital stream signal DSS, per symbol.

Referring to FIG. 80, when the number of bits per symbol is 2, the serialization circuit 811 may supply, to the digital-time conversion circuit 812, the digital stream signal DSS divided into a first sub-digital stream signal SDSS1 and a second sub-digital stream signal SDSS2. The digital-time conversion circuit 812 may generate a pulse with a time level corresponding to 2 bits including 1 bit of the first sub-digital stream signal SDSS1 and 1 bit of the second sub-digital stream signal SDSS2, per symbol.

Referring to FIG. 8D, when the number of bits per symbol is n, the serialization circuit 811 may supply, to the digital-time conversion circuit 812, the digital stream signal DSS divided into n sub-digital stream signals SDSS1 to SDSSn. The digital-time conversion circuit 812 may generate a pulse with a time level corresponding to n bits including 1 bit of each of the n sub-digital stream signals SDSS1 to SDSSn, per symbol.

Referring back to FIG. 8A, the digital-time conversion circuit 812 may generate the data pulse signal DPS corresponding to the digital stream signal DSS, based on the clock pulse signal CLK2. The digital-time conversion circuit 812 may generate the data pulse signal DPS by delaying the clock pulse signal CLK2 by a time level corresponding to the digital stream signal DSS. For example, when a value of the digital stream signal DSS is “11” in one symbol and “11” corresponds to a fourth time level, the digital-time conversion circuit 812 may generate a pulse of the data pulse signal DPS by delaying a pulse of the clock pulse signal CLK2 by the fourth time level.

The transmission interface circuit 830 may transmit the data pulse signal DPS to the data reception circuit system through a channel.

FIGS. 9A and 9B are circuit diagrams of a digital-time conversion circuit according to embodiments.

The digital-time conversion circuit may convert a digital signal into a time level. The time level may be defined by a time difference between a rising edge (or a falling edge) of a clock pulse signal and a rising edge (or a falling edge) of a data pulse signal, and the digital-time conversion circuit may generate the data pulse signal by delaying the clock pulse signal by a time level corresponding to the digital signal.

The digital-time conversion circuit may be implemented through various designs, and for example, the digital-time conversion circuit may include a digital-to-time converter (DTC). Hereinafter, embodiments of the digital-time conversion circuit for generating a data pulse signal corresponding to a digital signal of 2 bits will be described with reference to FIGS. 9A and 9B.

Referring to FIG. 9A, the digital-time conversion circuit according to an embodiment may include capacitors 901 and 902, and transistors 903 and 904. An input signal (i.e., the clock pulse signal) of the digital-time conversion circuit may be delayed by the capacitors 901 and 902 operated by the switches 903 and 904 that are turned on or off according to a digital stream signal (i.e., the digital signal).

A first bit D [0] of the digital stream signal may be connected to a gate terminal of the transistor 903, and a second bit D [1] of the digital stream signal may be connected to a gate terminal of the transistor 904. When the digital stream signal is “00”, an output signal that is not delayed (i.e., the data pulse signal with a first time level) may be generated. When the digital stream signal is “01”, an output signal delayed by the capacitor 901 (i.e., the data pulse signal with a second time level) may be generated. When the digital stream signal is “10”, an output signal delayed by the capacitor 902 (i.e., the data pulse signal with a third time level) may be generated. When the digital stream signal is “11”, an output signal delayed by the capacitors 901 and 902 (i.e., the data pulse signal with a fourth time level) may be generated. Here, the capacitors 901 and 902 may have different capacitances so that delay times when the digital stream signal is “01” and “10” are different.

Referring to FIG. 9B, the digital-time conversion circuit according to an embodiment includes a ramp generation circuit 911 and a threshold comparison circuit 912. The ramp generation circuit 911 may receive an input signal (i.e., a clock pulse signal) and generate a ramp signal with an inclination determined by capacitors operating according to a digital stream signal (i.e., a digital signal). The threshold comparison circuit 912 may generate an output signal (i.e., a data pulse signal) with a delay according to time when the ramp signal exceeds a threshold voltage.

FIG. 10 is a block diagram of a data transmission circuit system 1000 according to an embodiment.

The data transmission circuit system 1000 according to an embodiment includes a data pulse generation circuit 1010, a clock pulse generation circuit 1020, and a transmission interface circuit 1030. The data pulse generation circuit 1010 includes a serialization circuit 1011, a digital-time conversion circuit 1012, and an equalization circuit 1013. Descriptions of embodiments apply to the data transmission circuit system 1000 of FIG. 10. Thus, redundant descriptions are omitted.

The data transmission circuit system 1000 may generate the data pulse signal DPS with time levels corresponding to the digital signal DS. Each symbol may include one pulse of the data pulse signal DPS, and each pulse may have a time level corresponding to a value of a corresponding digital signal.

The time level determines a timepoint of a rising edge (or a falling edge) of the pulse, and thus, an interval between edges may vary according to a time level of a previous symbol and a time level of a current symbol. In other words, the interval between the edges may vary according to a value of a digital signal of the previous symbol and a value of a digital signal of the current symbol. Accordingly, inter-symbol interference (ISI) may occur, wherein data of the previous symbol and data of the current symbol affect the current symbol.

To alleviate the described ISI, the data transmission circuit system 1000 according to an embodiment may include the equalization circuit 1013 configured to improve quality of a data pulse signal, based on the value of the digital signal of the previous symbol and the value of the digital signal of the current symbol. The equalization circuit 1013 may receive, from the serialization circuit 1011, the value of the digital signal (i.e., a value of a digital stream signal) of the previous symbol and the value of the digital signal (i.e., a value of a digital stream signal) of the current symbol, and improve the quality of the data pulse signal by adjusting a delay of the digital-time conversion circuit 1012, based on the value of the digital signal of the previous symbol and the value of the digital signal of the current symbol.

FIGS. 11A and 11B are circuit diagrams of a digital-time conversion circuit and an equalization circuit, according to embodiments.

An equalization circuit may adjust a delay of a digital-time conversion circuit, based on a value of a digital signal (i.e., a value of a digital stream signal) of a previous symbol and a value of a digital signal (i.e., a value of a digital stream signal) of a current symbol. The equalization circuit may be implemented through various designs according to the digital-time conversion circuit, and for example, the equalization circuit may include a feed-forward equalizer (FFE). Hereinafter, embodiments of an equalization circuit when the number of bits of a digital signal per symbol is 2 will be described with reference to FIGS. 11A and 11B.

Referring to FIG. 11A, an equalization circuit 1100 may be configured to adjust a delay of the digital-time conversion circuit of FIG. 9A, based on a value of a digital signal of a previous symbol and a value of a digital signal of a current symbol. The digital signal of 2 bits of the previous symbol and the digital signal of 2 bits of the current symbol may provide 16 cases CASE0 to CASE15. For example, CASE0 denotes a case where the digital signal of the previous symbol is “00” and the digital signal of the current symbol is “00”, and CASE15 denotes a case where the digital signal of the previous symbol is “11” and the digital signal of the current symbol is “11”. The equalization circuit 1100 may adjust a delay of the digital-time conversion circuit by using transistors and capacitors operating according to the 16 cases. Accordingly, a delay of a clock pulse signal (i.e., an input signal) is adjusted based on the value of the digital signal of the previous symbol and the value of the digital signal of the current symbol, and thus, a data pulse signal (i.e., an output signal) of the current symbol may be generated.

In a similar manner, referring to FIG. 11B, an equalization circuit 1110 may be configured to adjust a delay of the digital-time conversion circuit of FIG. 9B, based on a value of a digital signal of a previous symbol and a value of a digital signal of a current symbol.

FIGS. 12A and 12B are graphs of a channel response of a pulse signal, according to embodiments.

FIG. 12A is a graph of a channel response of a data pulse signal of a data transmission circuit system that does not include an equalization circuit, and FIG. 12B is a graph of a channel response of a data pulse signal of a data transmission circuit system that includes an equalization circuit. Comparing FIGS. 12A and 12B, it is determined that ISI of a data pulse signal is alleviated when an equalization circuit is included.

FIG. 13 is a block diagram of a data transmission circuit system 1300 according to an embodiment.

The data transmission circuit system 1300 according to an embodiment includes a data pulse generation circuit 1310, a clock pulse generation circuit 1320, and a transmission interface circuit 1330. The data pulse generation circuit 1310 includes a serialization circuit 1311, a first digital-time conversion circuit 1312a, a second digital-time conversion circuit 1312b, and a data pulse combining circuit 1313. Descriptions of embodiments apply to the data transmission circuit system 1300 of FIG. 13. Thus, redundant descriptions are omitted.

The data transmission circuit system 1300 according to an embodiment may generate the data pulse signal DPS trough a time-interleaved operation. Time interleaving may be performed by using a first clock pulse signal CLK2a and a second clock pulse signal CLK2b, which have different phases. A phase difference between the first clock pulse signal CLK2a and the second clock pulse signal CLK2b may be variously set such as not to exceed 360 degrees.

The clock pulse generation circuit 1320 may generate the first clock pulse signal CLK2a and the second clock pulse signal CLK2b, which have different phases and a same frequency, for the time interleaving. A rising edge (or a falling edge) of the first clock pulse signal CLK2a and a rising edge (or a falling edge) of the second clock pulse signal CLK2b have different timepoints, and may be accordingly time-interleaved.

The serialization circuit 1311 may generate a first digital stream signal DSS1 and a second digital stream signal DSS2 by serializing and distributing the digital signal DS. The first digital stream signal DSS1 may be supplied to the first digital-time conversion circuit 1312a, and the second digital stream signal DSS2 may be supplied to the second digital-time conversion circuit 1312b.

The first digital-time conversion circuit 1312a may generate a first sub-data pulse signal SDPS1 by delaying the first clock pulse signal CLK2a by a time level corresponding to the first digital stream signal DSS1. Similarly, the second digital-time conversion circuit 1312b may generate a second sub-data pulse signal SDPS2 by delaying the second clock pulse signal CLK2b by a time level corresponding to the second digital stream signal DSS2.

The data pulse combining circuit 1313 may generate the data pulse signal DPS by combining the first sub-data pulse signal SDPS1 with the second sub-data pulse signal SDPS2. When the digital signal DS is encoded to rising edges of the first sub-data pulse signal SDPS1 and second sub-data pulse signal SDPS2, the data pulse combining circuit 1313 may generate the data pulse signal DPS such that the data pulse signal DPS includes the rising edges of the first sub-data pulse signal SDPS1 and the rising edges of the second sub-data pulse signal SDPS2. Alternatively, when the digital signal DS is encoded to falling edges of the first sub-data pulse signal SDPS1 and second sub-data pulse signal SDPS2, the data pulse combining circuit 1313 may generate the data pulse signal DPS such that the data pulse signal DPS includes the falling edges of the first sub-data pulse signal SDPS1 and the falling edges of the second sub-data pulse signal SDPS2.

The data transmission circuit system 1300 may provide a same transmission speed by using a digital-time conversion circuit operating at a frequency twice lower than the data transmission circuit system 800 of FIG. 8A. For example, the data transmission circuit system 800 provides a 32 Gbps transmission speed by using a digital-time conversion circuit configured to modulate data of 2 bits per symbol to 16 GHz, whereas the data transmission circuit system 1300 provides a 32 Gbps transmission speed by using two digital-time conversion circuits configured to modulate data of 2 bits per symbol to 8 GHz.

FIG. 14 is a diagram for describing an operation of a data pulse combining circuit, according to an embodiment.

An operation of the data pulse combining circuit 1313 according to an embodiment will be described with reference to FIGS. 13 and 14. According to an embodiment, the first clock pulse signal CLK2a and the second clock pulse signal CLK2b have a phase difference of 180 degrees, and the digital signal DS is encoded to a rising edge of the data pulse signal DPS. A first time level is a base time level, a time difference between a second time level and the base time level is Δt1, and a time difference between a third time level and the base time level is Δt2.

According to an embodiment, the first digital-time conversion circuit 1312a generates a pulse 1411 of the first sub-data pulse signal SDPS1 by delaying a pulse 1401 of the first clock pulse signal CLK2a by the second time level corresponding to a value of the digital signal DS (i.e., a value of the first digital stream signal DSS1) of a symbol. Similarly, the second digital-time conversion circuit 1312b generates a pulse 1412 of the second sub-data pulse signal SDPS2 by delaying a pulse 1402 of the second clock pulse signal CLK2b by the third time level corresponding to the value of the digital signal DS (i.e., a value of the second digital stream signal DSS2) of a next symbol.

The data pulse combining circuit 1313 generates the data pulse signal DPS including a rising edge of the pulse 1411 and a rising edge of the pulse 1412 by combining the first sub-data pulse signal SDPS1 with the second sub-data pulse signal SDPS2.

According to an embodiment, the data pulse combining circuit 1313 may include a switching circuit (not shown) using rising edges of the first sub-data pulse signal SDPS1 and second sub-data pulse signal SDPS2 as triggers. The switching circuit may output the first sub-data pulse signal SDPS1 for a certain time and then output the second sub-data pulse signal SDPS2, in response to the rising edge of the first sub-data pulse signal SDPS1. Also, the switching circuit may output the second sub-data pulse signal SDPS2 for a certain time and then output the first sub-data pulse signal SDPS1, in response to the rising edge of the second sub-data pulse signal SDPS2. Here, when the certain time is consistent, pulses 1421 and 1422 of the data pulse signal DPS may have consistent pulse widths. Alternatively, when the certain time is different for each time level, the pulses 1421 and 1422 of the data pulse signal DPS may have falling edges with consistent timepoints.

FIG. 15 is a block diagram of a data transmission circuit system 1500 according to an embodiment.

The data transmission circuit system 1500 according to an embodiment includes a data pulse generation circuit 1510, a clock pulse generation circuit 1520, and a transmission interface circuit 1530. The data pulse generation circuit 1510 includes a serialization circuit 1511, a first digital-time conversion circuit 1512a, a second digital-time conversion circuit 1512b, a third digital-time conversion circuit 1512c, a fourth digital-time conversion circuit 1512d, and a data pulse combining circuit 1513. Descriptions of embodiments apply to the data transmission circuit system 1500 of FIG. 15. Thus, redundant descriptions are omitted.

The data transmission circuit system 1500 according to an embodiment may perform a time-interleaved operation by using a first clock pulse signal CLK2a, a second clock pulse signal CLK2b, a third clock pulse signal CLK2c, and a fourth clock pulse signal CLK2d, which have different phases. Phase differences between the first clock pulse signal CLK2a, the second clock pulse signal CLK2b, the third clock pulse signal CLK2c, and the fourth clock pulse signal CLK2d may be variously set such as not to exceed 360 degrees.

The clock pulse generation circuit 1520 may generate the first clock pulse signal CLK2a, the second clock pulse signal CLK2b, the third clock pulse signal CLK2c, and the fourth clock pulse signal CLK2d, which have different phases and a same frequency, for the time interleaving. The first clock pulse signal CLK2a, the second clock pulse signal CLK2b, the third clock pulse signal CLK2c, and the fourth clock pulse signal CLK2d have rising edges (or falling edges) having different timepoints, and may be accordingly time-interleaved.

The data transmission circuit system 1500 may provide a same transmission speed by using a digital-time conversion circuit operating at a frequency twice lower than the data transmission circuit system 1300 of FIG. 13. Also, the data transmission circuit system 1500 may provide a same transmission speed by using a digital-time conversion circuit operating at a frequency four times lower than the data transmission circuit system 800 of FIG. 8A.

For example, the data transmission circuit system 1300 provides a 64 Gbps transmission speed by using two digital-time conversion circuits configured to modulate data of 2 bits per symbol to 16 GHz, whereas the data transmission circuit system 1500 provides a 64 Gbps transmission speed by using four digital-time conversion circuits configured to modulate data of 2 bits per symbol to 8 GHz.

FIG. 16 is a diagram for describing an operation of a data pulse combining circuit, according to an embodiment.

An operation of the data pulse combining circuit according to an embodiment will be described with reference to FIGS. 15 and 16. According to an embodiment, the first clock pulse signal CLK2a, the second clock pulse signal CLK2b, the third clock pulse signal CLK2c, and the fourth clock pulse signal CLK2d have phase differences of 90 degrees, and the digital signal DS is encoded to a rising edge of the data pulse signal DPS. A first time level is a base time level, a time difference between a second time level and the base time level is Δt1, a time difference between a third time level and the base time level is Δt2, and a time difference between a fourth time level and the base time level is Δt3.

According to an embodiment, the first digital-time conversion circuit 1512a generates a pulse 1611 of the first sub-data pulse signal SDPS1 by delaying a pulse 1601 of the first clock pulse signal CLK2a by the first time level corresponding to a value of the digital signal DS (i.e., a value of the first digital stream signal DSS1) of a symbol. Here, the first time level is the base time level, and thus, the pulse 1601 is not delayed.

The second digital-time conversion circuit 1512b generates a pulse 1612 of the second sub-data pulse signal SDPS2 by delaying a pulse 1602 of the second clock pulse signal CLK2b by the second time level corresponding to the value of the digital signal DS (i.e., a value of the second digital stream signal DSS2) of a next symbol. Here, the pulse 1602 is delayed by Δt1.

The third digital-time conversion circuit 1512c generates a pulse 1613 of a third sub-data pulse signal SDPS3 by delaying a pulse 1603 of the third clock pulse signal CLK2c by the third time level corresponding to the value of the digital signal DS (i.e., a value of a third digital stream signal DSS3) of a next next symbol. Here, the pulse 1603 is delayed by Δt2.

The fourth digital-time conversion circuit 1512d generates a pulse 1614 of a fourth sub-data pulse signal SDPS4 by delaying a pulse 1604 of the fourth clock pulse signal CLK2d by the fourth time level corresponding to the value of the digital signal DS (i.e., a value of a fourth digital stream signal DSS4) of a next next next symbol. Here, the pulse 1604 is delayed by Δt3.

The data pulse combining circuit 1513 generates the data pulse signal DPS with pulses 1621 to 1624 having same timepoints of rising edges respectively as the pulses 1611 to 1614 by combining the first sub-data pulse signal SDPS1, the second sub-data pulse signal SDPS2, the third sub-data pulse signal SDPS3, and the fourth sub-data pulse signal SDPS4 with each other.

FIGS. 17A and 17B are eye diagrams of a PAM4 signal and FIGS. 17C and 17D are eye diagrams of a data pulse signal according to an embodiment.

FIG. 17A is an eye diagram of a PAM4 signal before passing through a channel having a channel characteristic of −12 dB at 16 GHz, and FIG. 17B is an eye diagram of a PAM4 signal after passing through the same channel. FIG. 17C is an eye diagram of a data pulse signal before passing through the same channel, and FIG. 17D is an eye diagram of a data pulse signal after passing through the same channel.

Comparing FIGS. 17B and 17D, it is determined that a reduction of an eye caused by channel attenuation is low when a data pulse signal is transmitted to a data transmission circuit system of the disclosure compared to when a PAM4 signal is transmitted. Accordingly, it is determined that the data transmission circuit system of the disclosure is able to transmit data with high signal reliability and a low bit error rate.

FIG. 18A is a block diagram of a data reception circuit system 1800 according to an embodiment.

The data reception circuit system 1800 according to an embodiment includes a digital signal generation circuit 1810, a clock recovery circuit 1820, and a reception interface circuit 1830. The digital signal generation circuit 1810 includes a parallelization circuit 1811 and a time-digital conversion circuit 1812.

The reception interface circuit 1830 may receive the data pulse signal DPS that has passed through a channel.

The clock recovery circuit 1820 may generate clock signals CLK4 and CLK5 required for an operation of the data reception circuit system 1800, based on the forward clock signal CLK3. The forward clock signal CLK3 may be a clock signal forwarded together with the data pulse signal DPS from a data transmission circuit system.

The clock recovery circuit 1820 may generate the clock signals CLK4 and CLK5 by delaying the forward clock signal CLK3 or changing a frequency of the forward clock signal CLK3. In this regard, the clock recovery circuit 1820 may include at least one of a frequency divider, a frequency multiplier, a frequency converter, or a delay circuit.

The time-digital conversion circuit 1812 may generate the digital stream signal DSS corresponding to the data pulse signal DPS, based on the recovered clock pulse signal CLK4. The time-digital conversion circuit 1812 may generate the digital stream signal DSS by outputting a digital value corresponding to a time level determined by a time difference between a rising edge (or a falling edge) of the recovered clock pulse signal CLK4 and a rising edge (or a falling edge) of the data pulse signal DPS. For example, when the time difference between the rising edge of the recovered clock pulse signal CLK4 and the rising edge of the data pulse signal DPS indicates a fourth time level, the time-digital conversion circuit 1812 may generate the digital stream signal DSS of “11”.

The time-digital conversion circuit 1812 may be implemented through various designs, and for example, the time-digital conversion circuit 1812 may include a time-to-digital converter (TDC).

The time-digital conversion circuit 1812 may supply, to the parallelization circuit 1811, the digital stream signal DSS distributed according to the number of bits per symbol.

Referring to FIG. 18B, when the number of bits per symbol is 1, the time-digital conversion circuit 1812 may supply, to the parallelization circuit 1811, the digital stream signal DSS of 1 bit per symbol.

Referring to FIG. 18C, when the number of bits per symbol is 2, the time-digital conversion circuit 1812 may supply, to the parallelization circuit 1811, the digital stream signal DSS of 2 bits including 1 bit of the first sub-digital stream signal SDSS1 and 1 bit of the second sub-digital stream signal SDSS2, per symbol.

Referring to FIG. 18D, when the number of bits per symbol is n, the time-digital conversion circuit 1812 may supply, to the parallelization circuit 1811, the digital stream signal DSS of n bits including 1 bit of each of the first to (n)th sub-digital stream signals SDSS1 to SDSSn, per symbol.

Referring back to FIG. 18A, the parallelization circuit 1811 may generate the digital signal DS by receiving the digital stream signal DSS from the time-digital conversion circuit 1812 and parallelizing the digital stream signal DSS.

FIG. 19A is a diagram for describing a clock recovery circuit 1900 according to an embodiment.

Pulses of the data pulse signal DPS may have time levels determined by an encoded digital signal. To decode a digital signal from the data pulse signal DPS, a base time level for determining the time levels of the pulses of the data pulse signal DPS needs to be provided. In this regard, the clock recovery circuit 1900 may generate the recovered clock pulse signal CLK4 with the base time level.

According to an embodiment, the clock recovery circuit 1900 may include a frequency converter 1910 and a delay locked loop circuit 1920.

When frequencies of the data pulse signal DPS and the forward clock signal CLK3 are not the same, the frequency converter 1910 may convert the frequency of the forward clock signal CLK3 into the frequency of the data pulse signal DPS. When the frequencies of the data pulse signal DPS and the forward clock signal CLK3 are the same, the clock recovery circuit 1900 may not include the frequency converter 1910.

The delay locked loop circuit 1920 may generate the recovered clock pulse signal CLK4 by delaying the forward clock signal CLK3 (or a frequency-converted forward clock signal CLK3a), based on the data pulse signal DPS. Embodiments of an operating mechanism of the delay locked loop circuit 1920 will be described with reference to FIGS. 19B and 19C.

FIGS. 19B and 19C are schematic diagrams of a mechanism for generating a recovered clock pulse signal, according to embodiments.

A mechanism for generating a recovered clock pulse signal, according to an embodiment, will be described with reference to FIGS. 19A and 19B. The clock recovery circuit 1900 may generate the recovered clock pulse signal CLK4, based on a phase difference between the forward clock signal CLK3 and the data pulse signal DPS. The delay locked loop circuit 1920 may generate the recovered clock pulse signal CLK4 by delaying the forward clock signal CLK3 such that an error signal generated based on the phase difference between the forward clock signal CLK3 and the data pulse signal DPS is stabilized.

A mechanism in which the clock recovery circuit 1900 generates a recovered clock pulse signal, according to an embodiment, will be described with reference to FIGS. 19A and 19C. When falling edges of the data pulse signal DPS have consistent timing, the clock recovery circuit 1900 may generate the recovered clock pulse signal CLK4, based on the falling edges of the data pulse signal DPS. The delay locked loop circuit 1920 may generate a delayed and inverted data pulse signal DPSa by inverting the data pulse signal DPS and then delaying the same by a half of a period of the forward clock signal CLK3. The delay locked loop circuit 1920 may generate the recovered clock pulse signal CLK4 by delaying the forward clock signal CLK3 such that a rising edge of the forward clock signal CLK3 and a rising edge of the delayed and inverted data pulse signal DPSa have a same timepoint.

FIG. 20A is a block diagram of a delay locked loop circuit 2000 according to an embodiment.

The delay locked loop circuit 2000 according to an embodiment includes a phase comparison circuit 2010, a charge pump circuit 2020, and a voltage controlled delay circuit 2030. The delay locked loop circuit 2000 may include a feedback loop in which the recovered clock pulse signal CLK4 (i.e., the forward clock signal CLK3 that has passed through the voltage controlled delay circuit 2030) is fed back.

The phase comparison circuit 2010 may generate an error signal ES, based on a phase difference between a feedback signal FS (i.e., the recovered clock pulse signal CLK4) and the data pulse signal DPS. The error signal ES may be a pulse signal and a duty cycle of the error signal ES may be determined by the phase difference between the feedback signal FS and the data pulse signal DPS. The phase comparison circuit 2010 may be implemented through various designs, and for example, the phase comparison circuit 2010 may include a phase frequency detector (PFD).

The charge pump circuit 2020 may output a voltage signal VS determined according to the duty cycle of the error signal ES. The charge pump circuit 2020 may be configured such that an output terminal is connected to a first node of a first voltage when the error signal ES is in a high state and the output terminal is connected to a second node of a second voltage when the error signal ES is in a low state. When the feedback loop is repeated in the delay locked loop circuit 2000, the voltage signal VS may converge as the duty cycle of the error signal ES converges to a pre-determined value (e.g., 50%). In other words, when the feedback loop is repeated in the delay locked loop circuit 2000, the error signal ES and the voltage signal VS may be stabilized. FIG. 20B is a graph of the voltage signal VS converged within about 50 ns, according to an embodiment.

The voltage controlled delay circuit 2030 may generate the recovered clock pulse signal CLK4 by delaying the forward clock signal CLK3 according to the voltage signal VS. When the voltage signal VS is converged, a delay may be locked and the recovered clock pulse signal CLK4 with a base time level may be generated. The voltage controlled delay circuit 2030 may be designed through various designs, and for example, the voltage controlled delay circuit 2030 may include a voltage controlled delay line (VCDL).

FIGS. 20C and 20D are schematic eye diagrams of the recovered clock pulse signal CLK4 and the data pulse signal DPS, according to embodiments.

Referring to FIGS. 19B and 20C, according to an embodiment, when the feedback loop converges, the recovered clock pulse signal CLK4 is locked to an average timepoint of time levels of the data pulse signal DPS.

Referring to FIGS. 19C and 20D, according to an embodiment, the recovered clock pulse signal CLK4 is generated based on falling edges of the data pulse signal DPS with consistent timing, and thus, a rising edge of the recovered clock pulse signal CLK4 is locked to a center timepoint of the time levels.

FIG. 21A is a block diagram of a delay locked loop circuit 2100 according to an embodiment.

The delay locked loop circuit 2100 according to an embodiment includes a phase comparison circuit 2110, a charge pump circuit 2120, and a voltage controlled delay circuit 2130. The delay locked loop circuit may include a feedback loop in which a forward clock signal CLK3+ that has passed through the voltage controlled delay circuit 2130 is fed back. Descriptions of embodiments apply to the delay locked loop circuit 2100 of FIG. 21A. Thus, redundant descriptions are omitted.

The phase comparison circuit 2110 may generate the error signal ES, based on a phase difference between the feedback signal FS (i.e., the forward clock signal CLK3+ that has passed through the voltage controlled delay circuit 2130) and the data pulse signal DPS.

The charge pump circuit 2120 may generate the voltage signal VS, based on the error signal ES. The voltage signal VS may be supplied to the voltage controlled delay circuit 2130.

The voltage controlled delay circuit 2130 may receive the forward clock signal CLK3+ and a phase-inverted forward clock signal CLK3− of 180 degrees. The voltage controlled delay circuit 2130 may generate the feedback signal FS by delaying the forward clock signal CLK3+ according to the voltage signal VS. Also, the voltage controlled delay circuit 2130 may generate the recovered clock pulse signal CLK4 by delaying the phase-inverted forward clock signal CLK3− according to the voltage signal VS.

FIG. 21B is a block diagram of a VCDL according to an embodiment.

Referring to FIGS. 21A and 21B, the voltage controlled delay circuit 2130 may include a VCDL. According to an embodiment, the VCDL may include a first delay cell 2131, a second delay cell 2132, a third delay cell 2133, and a fourth delay cell 2134. Each of the first delay cell 2131, the second delay cell 2132, the third delay cell 2133, and the fourth delay cell 2134 may be configured to generate an output signal by delaying an input signal according to an input voltage.

The first delay cell 2131, the second delay cell 2132, the third delay cell 2133, and the fourth delay cell 2134 may generate the feedback signal FS by delaying the forward clock signal CLK3+. Also, the first delay cell 2131, the second delay cell 2132, the third delay cell 2133, and the fourth delay cell 2134 may generate the recovered clock pulse signal CLK4 by delaying the phase-inverted forward clock signal CLK3−.

According to an embodiment, the forward clock signal CLK3+ and the phase-inverted forward clock signal CLK3− may be delayed by the first delay cell 2131, the second delay cell 2132, the third delay cell 2133, and the fourth delay cell 2134 stepwise. A stepwise delay may allow a delay of the delay locked loop circuit 2100 to be quickly locked.

According to an embodiment, the first delay cell 2131, the second delay cell 2132, and the third delay cell 2133 may have a locked delay, and the fourth delay cell 2134 may have a delay controllable by the voltage signal VS. The locked delay reduces a range of delay to be actually controlled by the VCDL, and thus, a delay of the delay locked loop circuit 2100 may be quickly locked. On the other hand, when four delay cells all have controllable delays, a range of delay to be actually controlled by the VCDL is increased, and thus, it may be difficult to lock the delay of the delay locked loop circuit 2100 within a desired range.

According to an embodiment, the phase comparison circuit 2110 may receive, as the feedback signal FS, the phase-inverted forward clock signal CLK3− that has passed through the VCDL, and generate the error signal ES, based on the phase difference between the feedback signal FS and the data pulse signal DPS.

According to an embodiment, the voltage controlled delay circuit 2130 may have a reduced overall delay range for generating the recovered clock pulse signal CLK4 by using the forward clock signal CLK3+ and the phase-inverted forward clock signal CLK3− compared to using only the forward clock signal CLK3+. Accordingly, the delay of the delay locked loop circuit 2100 may be quickly locked.

FIG. 22A is a block diagram of a data reception circuit system 2200 according to an embodiment.

The data reception circuit system 2200 according to an embodiment includes a digital signal generation circuit 2210, a clock recovery circuit 2220, and a reception interface circuit 2230. The digital signal generation circuit 2210 includes a parallelization circuit 2211, a time-digital conversion circuit 2212, and an equalization circuit 2213. Descriptions of embodiments apply to the data reception circuit system 2200 of FIG. 22A. Thus, redundant descriptions are omitted.

ISI and jitter may affect edges of the recovered clock pulse signal CLK4 and data pulse signal DPS, thereby affecting reliability of a time level. To reduce an effect of ISI and jitter on a time level, the data reception circuit system 2200 according to an embodiment may include the equalization circuit 2213 configured to perform equalization on the recovered clock pulse signal CLK4 and the data pulse signal DPS, based on a value of the digital stream signal DSS.

The equalization circuit 2213 may receive a value of the digital stream signal DSS of a previous symbol and perform equalization on the recovered clock pulse signal CLK4 and data pulse signal DPS of a current symbol according to the value of the digital stream signal DSS of the previous symbol. The equalization may be performed by delaying the recovered clock pulse signal CLK4 or the data pulse signal DPS according to a weight.

When the equalization circuit 2213 delays the recovered clock pulse signal CLK4, the time-digital conversion circuit 2212 may receive, from the equalization circuit 2213, the delayed recovered clock pulse signal CLK4 and the data pulse signal DPS, and generate the digital stream signal DSS corresponding to a time level determined by the delayed recovered clock pulse signal CLK4 and the data pulse signal DPS. Alternatively, when the equalization circuit 2213 delays the data pulse signal DPS, the time-digital conversion circuit 2212 may receive, from the equalization circuit 2213, the recovered clock pulse signal CLK4 and the delayed data pulse signal DPS, and generate the digital stream signal DSS corresponding to a time level determined by the recovered clock pulse signal CLK4 and the delayed data pulse signal DPS.

The equalization circuit 2213 according to an embodiment may delay one of the recovered clock pulse signal CLK4 and data pulse signal DPS of the current symbol by using a weight corresponding to the value of the digital stream signal DSS of the previous symbol. For example, when the number of bits per symbol is 2, four weights respectively corresponding to “00”, “01”, “10”, and “11” may be used. For example, when the digital stream signal DSS of the previous symbol is “10”, the equalization circuit 2213 may delay the recovered clock pulse signal CLK4 or data pulse signal DPS of the current symbol by using the weight corresponding to “10”.

FIG. 22B is a diagram for describing operations of a time-digital conversion circuit and an equalization circuit, according to an embodiment.

Referring to FIGS. 22A and 22B, according to an embodiment, the time-digital conversion circuit 2212 may determine a time level based on a time difference between a rising edge of the recovered clock pulse signal CLK4 and a rising edge of the data pulse signal DPS, and generate a digital value corresponding to the time level.

An embodiment in which the rising edge of the data pulse signal DPS is located at a first timepoint TP1 will be described. An initial location of the rising edge of the recovered clock pulse signal CLK4 may be a fourth timepoint TP4. The time-digital conversion circuit 2212 may determine that the rising edge of the recovered clock pulse signal CLK4 at the fourth timepoint TP4 is after a rising edge of the data pulse signal DPS at the first timepoint TP1, and delay the data pulse signal DPS up to a third timepoint TP3. Then, the time-digital conversion circuit 2212 may determine that the rising edge of the recovered clock pulse signal CLK4 at the fourth timepoint TP4 is after the rising edge of the data pulse signal DPS at the third timepoint TP3, and determine a time level corresponding to the rising edge of the data pulse signal DPS as a first time level.

An embodiment in which the rising edge of the data pulse signal DPS is located at a fifth timepoint TP5 will be described. The initial location of the rising edge of the recovered clock pulse signal CLK4 may be a fourth timepoint TP4. The time-digital conversion circuit 2212 may determine that the rising edge of the recovered clock pulse signal CLK4 at the fourth timepoint TP4 is before the rising edge of the data pulse signal DPS at the fifth timepoint TP5, and delay the recovered clock pulse signal CLK4 up to a sixth timepoint TP6. The time-digital conversion circuit 2212 may determine that the rising edge of the recovered clock pulse signal CLK4 at the sixth timepoint TP6 is after the rising edge of the data pulse signal DPS at the fifth timepoint TP5, and determine a time level corresponding to the rising edge of the data pulse signal DPS as a third time level.

The rising edge of the recovered clock pulse signal CLK4 may deviate from the fourth timepoint TP4 and the rising edge of the data pulse signal DPS may deviate from the first, third, fifth, and seventh timepoints TP1, TP3, TP5, and TP7, due to ISI or jitter. In this case, the equalization circuit 2213 may reduce effects of the ISI and jitter by delaying the recovered clock pulse signal CLK4 or the data pulse signal DPS.

According to an embodiment, when the rising edge of the data pulse signal DPS is located in a section A, C, E, or G, the equalization circuit 2213 may delay the data pulse signal DPS such that the rising edge of the data pulse signal DPS is located at the first, third, fifth, or seventh timepoints TP1, TP3, TP5, or TP7. According to an embodiment, when the rising edge of the data pulse signal DPS is located in a section B, D, F, or H, the equalization circuit 2213 may delay the recovered clock pulse signal CLK4 such that the rising edge of the data pulse signal DPS is located at the first, third, fifth, or seventh timepoints TP1, TP3, TP5, or TP7.

According to an embodiment, the time-digital conversion circuit 2212 may be configured to have resolution greater than the number of bits per symbol by 1 bit. The equalization circuit 2213 may determine a weight for equalization by using the last bit (of the time-digital conversion circuit 2212. For example, when the number of bits per symbol is 2, the time-digital conversion circuit 2212 may have resolution of 3 bits. In this case, first and second bits of the time-digital conversion circuit 2212 may be used to decode the digital signal DS, and a third bit thereof may be used for equalization of the equalization circuit 2213.

An embodiment of the equalization circuit 2213 configured to perform equalization by using the time-digital conversion circuit 2212 having resolution of 3 bits when the number of bits per symbol is 2 will be described. Output for the sections A to H of the time-digital conversion circuit 2212 are respectively “000”, “001”, “010”, “011”, “100”, “101”, “110”, and “111”. When the rising edge of the data pulse signal DPS is located at the section A, C, E, or G, the third bit of the time-digital conversion circuit 2212 is “0”, and when the rising edge of the data pulse signal DPS is located at the section B, D, F, or H, the third bit of the time-digital conversion circuit 2212 is “1”.

When the rising edges of the data pulse signal DPS are biased towards the section A, C, E, or G on average due to ISI or jitter, the third bit of the time-digital conversion circuit 2212 may be mainly “0”. On the other hand, when the rising edges of the data pulse signal DPS are biased towards the section B, D, F, or H on average, the third bit of the time-digital conversion circuit 2212 may be mainly “1”.

According to an embodiment, the equalization circuit 2213 may delay the recovered clock pulse signal CLK4 or the data pulse signal DPS, based on values of the third bit of the time-digital conversion circuit 2212, which are observed during certain sections. When the number of “0”s is greater than the number of “1”s in the values of the third bit during the certain sections, the equalization circuit 2213 may delay the data pulse signal DPS. Alternatively, when the number of “1”s is greater than the number of “0”s in the values of the third bit during the certain sections, the equalization circuit 2213 may delay the recovered clock pulse signal CLK4.

According to an embodiment, the equalization circuit 2213 may determine the weight, based on a least mean square (LMS) algorithm that is an algorithm for reducing an error. According to an embodiment, the equalization circuit 2213 may determine the weight for delaying the recovered clock pulse signal CLK4 or the data pulse signal DPS, based on the values of the third bit of the time-digital conversion circuit 2212, which are observed during the certain sections. The equalization circuit 2213 may increase the weight as a difference between the number of “0”s and the number of “1”s increases among the values of the third bit during the certain sections. Accordingly, a delay amount for the equalization may increase. Alternatively, the equalization circuit 2213 may decrease the weight as the difference between the number of “0”s and the number of “1”s decreases among the values of the third bit during the certain sections. Accordingly, the delay amount for the equalization may decrease.

According to an embodiment, the equalization circuit 2213 may perform equalization on a current section by using a weight determined for a previous section. The previous section and the current section may include a pre-determined number of symbols. For example, the equalization circuit 2213 may perform equalization on next 100 symbols (i.e., the current section) by using a weight determined for 100 symbols (i.e., the previous section).

According to an embodiment, the equalization circuit 2213 may update the weight for each section. For example, the equalization circuit 2213 may update the weight by determining a weight, based on values of third bit of the time-digital conversion circuit 2212 of the previous section, and determining a new weight, based on values of third bit of the time-digital conversion circuit 2212 of the current section.

According to an embodiment, the equalization circuit 2213 may determine a weight for each time level, based on values of third bit of the time-digital conversion circuit 2212 for sections adjacent to each time level. For example, the equalization circuit 2213 may determine a weight for a first time level, based on values of third bit of the time-digital conversion circuit 2212 for the section A/B. Similarly, the equalization circuit 2213 may determine weights for second to fourth time levels, based on values of third bit of the time-digital conversion circuit 2212 for the section C/D, section E/F, and section G/H respectively. The equalization circuit 2213 may perform equalization on each time level by using the weight determined for each time level.

According to an embodiment, the equalization circuit 2213 may determine a weight for all time levels, based on values of third bit of the time-digital conversion circuit 2212 for sections adjacent to any one time level. For example, the equalization circuit 2213 may determine a weight, based on values of third bit of the time-digital conversion circuit 2212 for the sections A and B, and perform equalization on the first to fourth time levels by using the determined weight.

FIG. 23A is a block diagram of a data reception circuit system 2300 according to an embodiment.

The data reception circuit system 2300 according to an embodiment includes a digital signal generation circuit 2310, a clock recovery circuit 2320, and a reception interface circuit 2330. The digital signal generation circuit 2310 includes a parallelization circuit 2311, a first time-digital conversion circuit 2312a, a second time-digital conversion circuit 2312b, and a data pulse separation circuit 2314. The clock recovery circuit 2320 includes a clock pulse separation circuit 2321. Descriptions of embodiments apply to the data reception circuit system 2300 of FIG. 23A. Thus, redundant descriptions are omitted.

The data reception circuit system 2300 according to an embodiment may generate the digital signal DS trough a time-interleaved operation. Time interleaving may be performed by using a first sub-clock pulse signal CLK4a and a second sub-clock pulse signal CLK4b, which are signals separated from the recovered clock pulse signal CLK4, and the first sub-data pulse signal SDPS1 and the second sub-data pulse signal SDPS2, which are signals separated from the data pulse signal DPS.

The clock pulse separation circuit 2321 may separate the recovered clock pulse signal CLK4 into the first sub-clock pulse signal CLK4a and the second sub-clock pulse signal CLK4b such that the first sub-clock pulse signal CLK4a and the second sub-clock pulse signal CLK4b alternately include pulses of the recovered clock pulse signal CLK4.

The data pulse separation circuit 2314 may separate the data pulse signal DPS into the first sub-data pulse signal SDPS1 and the second sub-data pulse signal SDPS2 such that the first sub-data pulse signal SDPS1 and the second sub-data pulse signal SDPS2 alternately include pulses of the data pulse signal DPS.

The first sub-clock pulse signal CLK4a and the second sub-clock pulse signal CLK4b have different timings, and may be accordingly time-interleaved. Also, the first sub-data pulse signal SDPS1 and the second sub-data pulse signal SDPS2 have different timings, and may be accordingly time-interleaved.

The first time-digital conversion circuit 2312a may generate the first digital stream signal DSS1 corresponding to the first sub-data pulse signal SDPS1, based on the first sub-clock pulse signal CLK4a. The second time-digital conversion circuit 2312b may generate the second digital stream signal DSS2 corresponding to the second sub-data pulse signal SDPS2, based on the second sub-clock pulse signal CLK4b.

The parallelization circuit 2311 may generate the digital signal DS by merging and parallelizing the first digital stream signal DSS1 and the second digital stream signal DSS2.

FIG. 23B is a diagram for describing a clock pulse separation circuit and a data pulse separation circuit, according to an embodiment.

Referring to FIGS. 23A and 23B, the clock pulse separation circuit 2321 according to an embodiment may include a first AND gate AND1 and a second AND gate AND2. In the clock pulse separation circuit 2321, a first input signal IS1 of the first AND gate AND1 is the recovered clock pulse signal CLK4, a second input signal IS2 is a recovered clock pulse signal in which a frequency is reduced by ½, and a first output signal OS1 is the first sub-clock pulse signal CLK4a. In the clock pulse separation circuit 2321, a first input signal IS1 of the second AND gate AND2 is the recovered clock pulse signal CLK4, a third input signal IS3 is an inverted signal of the second input signal IS2, and a second output signal OS2 is the second sub-clock pulse signal CLK4b. The first sub-clock pulse signal CLK4a and the second sub-clock pulse signal CLK4b may alternately include pulses of the recovered clock pulse signal CLK4.

Similarly, the data pulse separation circuit 2314 according to an embodiment may include the first AND gate AND1 and the second AND gate AND2. In the data pulse separation circuit 2314, a first input signal IS1 of the first AND gate AND1 is the data pulse signal DPS, a second input signal IS2 is a recovered clock pulse signal in which a frequency is reduced by ½, and a first output signal OS1 is the first sub-data pulse signal SDPS1. In the data pulse separation circuit 2314, a first input signal IS1 of the second AND gate AND2 is the data pulse signal DPS, a third input signal IS3 is an inverted signal of the second input signal IS2, and a second output signal OS2 is the second sub-data pulse signal SDPS2. The first sub-data pulse signal SDPS1 and the second sub-data pulse signal SDPS2 alternately include pulses of the data pulse signal DPS.

FIG. 24 is a diagram for describing operations of a first time-digital conversion circuit and a second time-digital conversion circuit, according to an embodiment.

Operations of the first time-digital conversion circuit 2312a and the second time-digital conversion circuit 2312b, according to an embodiment, will be described with reference to FIGS. 23A and 24. According to an embodiment, the digital signal DS is encoded from a rising edge of the data pulse signal DPS. A base time level is located between a second time level and a third time level, a time difference between a first time level and the base time level is Δt1, and a time difference between a fourth time level and the base time level is Δt2.

According to an embodiment, the data pulse separation circuit 2314 generates the first sub-data pulse signal SDPS1 and the second sub-data pulse signal SDPS2 by separating pulses 2401 and 2402 of the data pulse signal DPS.

The first time-digital conversion circuit 2312a determines the first time level, based on a time difference (Δt1) between a rising edge of the pulse 2401 of the first sub-data pulse signal SDPS1 and a rising edge of a pulse 2411 of the first sub-clock pulse signal CLK4a, and generates a value “00” of the first digital stream signal DSS1 corresponding to the first time level. Similarly, the second time-digital conversion circuit 2312b determines the fourth time level, based on a time difference (Δt2) between a rising edge of the pulse 2402 of the second sub-data pulse signal SDPS2 and a rising edge of a pulse 2412 of the second sub-clock pulse signal CLK4b, and generates a value “11” of the second digital stream signal DSS2 corresponding to the fourth time level.

FIG. 25 is a block diagram of a data reception circuit system 2500 according to an embodiment.

The data reception circuit system 2500 according to an embodiment includes a digital signal generation circuit 2510, a clock recovery circuit 2520, and a reception interface circuit 2530. The digital signal generation circuit 2510 includes a parallelization circuit 2511, a first time-digital conversion circuit 2512a, a second time-digital conversion circuit 2512b, a third time-digital conversion circuit 2512c, a fourth time-digital conversion circuit 2512d, and a data pulse separation circuit 2513. The clock recovery circuit 2520 includes a clock pulse separation circuit 2521. Descriptions of embodiments apply to the data reception circuit system 2500 of FIG. 25. Thus, redundant descriptions are omitted.

The data reception circuit system 2500 according to an embodiment may perform a time-interleaved operation by using the first sub-clock pulse signal CLK4a, the second sub-clock pulse signal CLK4b, a third sub-lock pulse signal CLK4c, and a fourth sub-clock pulse signal CLK4d.

For time interleaving, the clock pulse separation circuit 2521 may separate the recovered clock pulse signal CLK4 into the first sub-clock pulse signal CLK4a, the second sub-clock pulse signal CLK4b, the third sub-lock pulse signal CLK4c, and the fourth sub-clock pulse signal CLK4d such that the first sub-clock pulse signal CLK4a, the second sub-clock pulse signal CLK4b, the third sub-lock pulse signal CLK4c, and the fourth sub-clock pulse signal CLK4d alternately include pulses of the recovered clock pulse signal CLK4. Also, the data pulse separation circuit 2513 may separate the data pulse signal DPS into the first sub-data pulse signal SDPS1, the second sub-data pulse signal SDPS2, the third sub-data pulse signal SDPS3, and the fourth sub-data pulse signal SDPS4 such that the first sub-data pulse signal SDPS1, the second sub-data pulse signal SDPS2, the third sub-data pulse signal SDPS3, and the fourth sub-data pulse signal SDPS4 alternately include pulses of the data pulse signal DPS.

The first time-digital conversion circuit 2512a, the second time-digital conversion circuit 2512b, the third time-digital conversion circuit 2512c, and the fourth time-digital conversion circuit 2512d may generate the first digital stream signal DSS1, the second digital stream signal DSS2, the third digital stream signal DSS3, and the fourth digital stream signal DSS4, based on the first sub-clock pulse signal CLK4a, the second sub-clock pulse signal CLK4b, the third sub-lock pulse signal CLK4c, and the fourth sub-clock pulse signal CLK4d, respectively. The parallelization circuit 2511 may generate the digital signal DS by merging and parallelizing the first digital stream signal DSS1, the second digital stream signal DSS2, the third digital stream signal DSS3, and the fourth digital stream signal DSS4.

The data reception circuit system 2500 may process data received at a same transmission speed by using a time-digital conversion circuit operating at a frequency twice lower than the data reception circuit system 2300 of FIG. 23A. Also, the data reception circuit system 2500 may process data received at a same transmission speed by using a time-digital conversion circuit operating at a frequency for times lower than the data reception circuit system 1800 of FIG. 18A.

For example, the data reception circuit system 2300 processes a data pulse signal of 32 Gbps by using two time-digital conversion circuits configured to demodulate data of 2 bits per symbol to 8 GHz, whereas the data reception circuit system 2500 may process a data pulse signal of 32 Gbps by using four time-digital conversion circuits configured to demodulate data of 2 bits per symbol to 4 GHz.

FIG. 26 is a block diagram of a data reception circuit system 2600 according to an embodiment.

The data reception circuit system 2600 according to an embodiment includes a digital signal generation circuit 2610, a clock recovery circuit 2620, and a reception interface circuit 2630. The digital signal generation circuit 2610 includes a parallelization circuit 2611, a first time-digital conversion circuit 2612a, a second time-digital conversion circuit 2612b, a first equalization circuit 2613a, a second equalization circuit 2613b, and a data pulse separation circuit 2614. The clock recovery circuit 2620 includes a clock pulse separation circuit 2621. Descriptions of embodiments apply to the data reception circuit system 2600 of FIG. 26. Thus, redundant descriptions are omitted.

The first equalization circuit 2613a may receive a value of the digital signal DS (i.e., a value of the second digital stream signal DSS2) of a previous symbol, and perform equalization on the first sub-clock pulse signal CLK4a and the first sub-data pulse signal SDPS1 of a current symbol according to the value of the digital signal DS of the previous symbol. The equalization may be performed by delaying the first sub-clock pulse signal CLK4a or the first sub-data pulse signal SDPS1 according to a weight.

When the first equalization circuit 2613a delays the first sub-clock pulse signal CLK4a, the first time-digital conversion circuit 2612a may receive, from the first equalization circuit 2613a, the delayed first sub-clock pulse signal CLK4a and the first sub-data pulse signal SDPS1, and generate the first digital stream signal DSS1 corresponding to a time level determined by the delayed first sub-clock pulse signal CLK4a and the first sub-data pulse signal SDPS1. Alternatively, when the first equalization circuit 2613a delays the first sub-data pulse signal SDPS1, the first time-digital conversion circuit 2612a may receive, from the first equalization circuit 2613a, the first sub-clock pulse signal CLK4a and the delayed first sub-data pulse signal SDPS1, and generate the first digital stream signal DSS1 corresponding to a time level determined by the first sub-clock pulse signal CLK4a and the delayed first sub-data pulse signal SDPS1.

The second equalization circuit 2613b may receive a value of the digital signal DS (i.e., a value of the first digital stream signal DSS1) of the current symbol, and perform equalization on the second sub-clock pulse signal CLK4b and the second sub-data pulse signal SDPS2 of a next symbol according to the value of the digital signal DS of the current symbol. The equalization may be performed by delaying the second sub-clock pulse signal CLK4b or the second sub-data pulse signal SDPS2 according to a weight.

When the second equalization circuit 2613b delays the second sub-clock pulse signal CLK4b, the second equalization circuit 2613b may receive, from the second equalization circuit 2613b, the delayed second sub-clock pulse signal CLK4b and the second sub-data pulse signal SDPS2, and generate the second digital stream signal DSS2 corresponding to a time level determined by the delayed second sub-clock pulse signal CLK4b and the second sub-data pulse signal SDPS2. Alternatively, when the second equalization circuit 2613b delays the second sub-data pulse signal SDPS2, the second equalization circuit 2613b may receive, from the second equalization circuit 2613b, the second sub-clock pulse signal CLK4b and the delayed second sub-data pulse signal SDPS2, and generate the second digital stream signal DSS2 corresponding to a time level determined by the second sub-clock pulse signal CLK4b and the delayed second sub-data pulse signal SDPS2.

FIG. 27 is a flowchart of a data transmission method according to an embodiment.

In operation S2701, a data transmission circuit system may receive a digital signal.

According to an embodiment, the data transmission circuit system may be a sub-circuit system of a higher circuit system, and the digital signal may be data to be transmitted by the higher circuit system. For example, the digital signal may be 32-bit data or 64-bit data, but is not limited thereto.

In operation S2702, the data transmission circuit system may generate a clock pulse signal with a first type edge of a base time level that is a basis of a time level corresponding to the digital signal.

According to an embodiment, the data transmission circuit system may generate the clock pulse signal, based on a base clock signal of the higher circuit system. For example, the clock pulse signal may have a frequency of 4 GHz, 8 GHz, or 16 GHz, but is not limited thereto.

In operation S2703, the data transmission circuit system may generate a data pulse signal with a first type edge of a time level, based on the clock pulse signal.

According to an embodiment, the data transmission circuit system may generate the data pulse signal by delaying the clock pulse signal by the time level.

In operation S2704, the data transmission circuit system may transmit the data pulse signal.

According to an embodiment, the data transmission circuit system may transmit a forward clock signal together with the data pulse signal.

In operations S2701 to 2704, the first type edge may be a rising edge or a falling edge.

FIG. 28 is a flowchart of a data reception method according to an embodiment.

In operation S2801, a data reception circuit system may receive a data pulse signal.

According to an embodiment, the data reception circuit system may receive the data pulse signal that is transmitted by a data transmission circuit system and has passed through a channel.

According to an embodiment, the data reception circuit system may receive a forward clock signal together with the data pulse signal.

In operation S2802, the data reception circuit system may generate a recovered clock pulse signal with a first type edge of a base time level that is a basis of a time level of a first type edge of the data pulse signal.

According to an embodiment, the data reception circuit system may generate the recovered clock pulse signal by delaying the forward clock signal, based on a phase difference between the recovered clock pulse signal and the data pulse signal.

In operation S2803, the data reception circuit system may generate a digital signal corresponding to the time level, based on the recovered clock pulse signal.

According to an embodiment, the data reception circuit system may determine the time level based on a time difference between the first type edge of the recovered clock pulse signal and the first type edge of the data pulse signal, and generate the digital signal corresponding to the time level.

In operations S2801 to 2803, the first type edge may be a rising edge or a falling edge.

In the description of the disclosure above, embodiments from encoding a digital signal to a rising edge of a data pulse signal to encoding a digital signal to a falling edge of a data pulse signal have been described. Also, in the description of the disclosure, embodiments from decoding a digital signal from a rising edge of a data pulse signal to decoding a digital signal from a falling edge of a data pulse signal have been described.

A data transmission circuit system and a data reception circuit system, according to embodiments, use a time level instead of a voltage level, and thus do not require ADC and DAC. Accordingly, the data transmission circuit system and the data reception circuit system may operate at low power consumption and resolution thereof may not decrease due to a change in an operating voltage. Such characteristics of the data transmission circuit system and data reception circuit system allow energy-efficient and reliable data transmission and reception even for a semiconductor circuit according to device scaling.

Effects achieved from the embodiments are not limited to those described above, and other effects that are not described may be clearly derived and understood by one of ordinary skill in the art from the description of the embodiments. In other words, unintended effects according to the embodiments may be derived by one of ordinary skill in the art.

The above description of the disclosure is provided for illustration, and it will be understood by one of ordinary skill in the art that various changes in form and details may be readily made therein without departing from essential features and the scope of the disclosure as defined by the following claims. Accordingly, embodiments described above are examples in all aspects and are not limited. For example, each element described as a single type may be implemented in a distributed manner, and similarly, elements described as distributed may be implemented in a combined form.

The scope of the disclosure is defined by the appended claims rather than the detailed description, and all changes or modifications within the scope of the appended claims and their equivalents will be construed as being included in the scope of the disclosure.

Claims

1. A data transmission circuit system using an edge of a pulse signal, the data transmission circuit system comprising: a data pulse generation circuit configured to receive a digital signal and generate, based on a clock pulse signal, a data pulse signal with a first type edge of a time level corresponding to the digital signal;a clock pulse generation circuit configured to generate the clock pulse signal with a first type edge of a base time level that is a basis of the time level; anda transmission interface circuit configured to transmit the data pulse signal,wherein a time difference between a first type edge of the clock pulse signal and a first type edge of the data pulse signal indicates the time level.

2. The data transmission circuit system of claim 1, wherein the data pulse generation circuit is further configured to generate the data pulse signal by delaying the clock pulse signal according to the time level corresponding to the digital signal.

3. The data transmission circuit system of claim 1, wherein the clock pulse generation circuit is further configured to generate a plurality of clock pulse signals with different phases, and the data pulse generation circuit is further configured to generate sub-data pulse signals by respectively delaying the plurality of clock pulse signals according to time levels corresponding to the digital signal, and generate the data pulse signal by combining the sub-data pulse signals with each other.

4. The data transmission circuit system of claim 1, wherein the data pulse generation circuit comprises: a serialization circuit configured to generate a digital stream signal by serializing the digital signal; anda digital-time conversion circuit configured to generate the data pulse signal by delaying the clock pulse signal according to a time level corresponding to the digital stream signal.

5. The data transmission circuit system of claim 4, wherein the data pulse generation circuit comprises an equalization circuit configured to adjust a delay of a pulse of the clock pulse signal of a current symbol, based on a value of the digital stream signal of a previous symbol and a value of the digital stream signal of the current symbol.

6. The data transmission circuit system of claim 1, wherein the clock pulse generation circuit is further configured to generate a first clock pulse signal with a first phase and a second clock pulse signal with a second phase, and the data pulse generation circuit comprises:a serialization circuit configured to generate a first digital stream signal and a second digital stream signal by serializing and distributing the digital signal;a first digital-time conversion circuit configured to generate a first sub-data pulse signal by delaying the first clock pulse signal according to a time level corresponding to the first digital stream signal;a second digital-time conversion circuit configured to generate a second sub-data pulse signal by delaying the second clock pulse signal according to a time level corresponding to the second digital stream signal; anda data pulse combining circuit configured to generate the data pulse signal by combining the first sub-data pulse signal with the second sub-data pulse signal such that the data pulse signal includes a first type edge of the first sub-data pulse signal and a first type edge of the second sub-data pulse signal.

7. The data transmission circuit system of claim 1, wherein the clock pulse generation circuit is further configured to generate a first clock pulse signal with a first phase, a second clock pulse signal with a second phase, a third clock pulse signal with a third phase, and a fourth clock pulse signal with a fourth phase, and the data pulse generation circuit comprises:a serialization circuit configured to generate a first digital stream signal, a second digital stream signal, a third digital stream signal, and a fourth digital stream signal by serializing and distributing the digital signal;a first digital-time conversion circuit configured to generate a first sub-data pulse signal by delaying the first clock pulse signal according to a time level corresponding to the first digital stream signal;a second digital-time conversion circuit configured to generate a second sub-data pulse signal by delaying the second clock pulse signal according to a time level corresponding to the second digital stream signal;a third digital-time conversion circuit configured to generate a third sub-data pulse signal by delaying the third clock pulse signal according to a time level corresponding to the third digital stream signal;a fourth digital-time conversion circuit configured to generate a fourth sub-data pulse signal by delaying the fourth clock pulse signal according to a time level corresponding to the fourth digital stream signal; anda data pulse combining circuit configured to generate the data pulse signal by combining the first sub-data pulse signal, the second sub-data pulse signal, the third sub-data pulse signal, and the fourth sub-data pulse signal with each other such that the data pulse signal includes a first type edge of the first sub-data pulse signal, a first type edge of the second sub-data pulse signal, a first type edge of the third sub-data pulse signal, and a first type edge of the fourth sub-data pulse signal.

8. The data transmission circuit system of claim 1, wherein an interval between a plurality of time levels indicated by pulses of the data pulse signal is less than 1 ns.

9. The data transmission circuit system of claim 1, wherein the first type edge is one of a rising edge and a falling edge.

10. A data transmission method using an edge of a pulse signal, the data transmission method comprising: receiving a digital signal;generating a clock pulse signal with a first type edge of a base time level that is a basis of a time level;generating, based on the clock pulse signal, a data pulse signal with a first type edge of a time level corresponding to the digital signal; andtransmitting the data pulse signal,wherein a time difference between a first type edge of the clock pulse signal and a first type edge of the data pulse signal indicates the time level.

11. A data reception circuit system using an edge of a pulse signal, the data reception circuit system comprising: a reception interface circuit configured to receive a data pulse signal;a digital signal generation circuit configured to generate, based on a recovered clock pulse signal, a digital signal corresponding to a time level of a first type edge of the data pulse signal; anda clock recovery circuit configured to generate the recovered clock pulse signal with a first type edge of a base time level that is a basis of the time level,wherein a time difference between a first type edge of the recovered clock pulse signal and a first type edge of the data pulse signal determines the time level.

12. The data reception circuit system of claim 11, wherein the digital signal generation circuit comprises: a time-digital conversion circuit configured to generate a digital stream signal corresponding to a time level of the data pulse signal; anda parallelization circuit configured to generate the digital signal by parallelizing the digital stream signal.

13. The data reception circuit system of claim 12, wherein the time-digital conversion circuit comprises an equalization circuit configured to adjust a delay of a pulse of the recovered clock pulse signal of a current symbol or a delay of a pulse of the data pulse signal of the current symbol, based on a value of the digital stream signal of a previous symbol.

14. The data reception circuit system of claim 11, wherein the clock recovery circuit comprises a clock pulse separation circuit configured to separate the recovered clock pulse signal into a first sub-clock pulse signal and a second sub-clock pulse signal such that the first sub-clock pulse signal and the second sub-clock pulse signal alternately include pulses of the recovered clock pulse signal, and the digital signal generation circuit comprises:a data pulse separation circuit configured to separate the data pulse signal into a first sub-data pulse signal and a second sub-data pulse signal such that the first sub-data pulse signal and the second sub-data pulse signal alternately include pulses of the data pulse signal;a first time-digital conversion circuit configured to generate a first digital stream signal corresponding to a time level determined by a time difference between a first type edge of the first sub-clock pulse signal and a first type edge of the first sub-data pulse signal;a second time-digital conversion circuit configured to generate a second digital stream signal corresponding to a time level determined by a time difference between a first type edge of the second sub-clock pulse signal and a first type edge of the second sub-data pulse signal; anda parallelization circuit configured to generate the digital signal by merging and parallelizing the first digital stream signal and the second digital stream signal.

15. The data reception circuit system of claim 11, wherein the clock recovery circuit comprises a clock pulse separation circuit configured to separate the recovered clock pulse signal into a first sub-clock pulse signal, a second sub-clock pulse signal, a third sub-clock pulse signal, and a fourth sub-clock pulse signal such that the first sub-clock pulse signal, the second sub-clock pulse signal, the third sub-clock pulse signal, and the fourth sub-clock pulse signal alternately include pulses of the recovered clock pulse signal, and the digital signal generation circuit comprises:a data pulse separation circuit configured to separate the data pulse signal into a first sub-data pulse signal, a second sub-data pulse signal, a third sub-data pulse signal, and a fourth sub-data pulse signal such that the first sub-data pulse signal, the second sub-data pulse signal, the third sub-data pulse signal, and the fourth sub-data pulse signal alternately include pulses of the data pulse signal;a first time-digital conversion circuit configured to generate a first digital stream signal corresponding to a time level determined by a time difference between a first type edge of the first sub-clock pulse signal and a first type edge of the first sub-data pulse signal;a second time-digital conversion circuit configured to generate a second digital stream signal corresponding to a time level determined by a time difference between a first type edge of the second sub-clock pulse signal and a first type edge of the second sub-data pulse signal;a third time-digital conversion circuit configured to generate a third digital stream signal corresponding to a time level determined by a time difference between a first type edge of the third sub-clock pulse signal and a first type edge of the third sub-data pulse signal;a fourth time-digital conversion circuit configured to generate a fourth digital stream signal corresponding to a time level determined by a time difference between a first type edge of the fourth sub-clock pulse signal and a first type edge of the fourth sub-data pulse signal; anda parallelization circuit configured to generate the digital signal by merging and parallelizing the first digital stream signal, the second digital stream signal, the third digital stream signal, and the fourth digital stream signal.

16. The data reception circuit system of claim 11, wherein the clock recovery circuit is further configured to generate the recovered clock pulse signal by receiving a forward clock signal and delaying the forward clock signal such that a first type edge of the forward clock signal is located at the base time level.

17. The data reception circuit system of claim 11, wherein the clock recovery circuit comprises a delay locked loop circuit configured to receive a forward clock signal and output the recovered clock pulse signal by delaying the forward clock signal, wherein the delay locked loop circuit comprises a feedback loop, andthe delay locked loop circuit is configured to delay the forward clock signal, based on a phase difference between a feedback signal of the feedback loop and the data pulse signal.

18. The data reception circuit system of claim 11, wherein the base time level is located between two middle time levels of a plurality of time levels determined by pulses of the recovered clock pulse signal and pulses of the data pulse signal.

19. The data reception circuit system of claim 11, wherein the first type edge is one of a rising edge and a falling edge.