DATA TRANSMISSION METHOD AND TRANSMISSION CIRCUIT THEREOF

Abstract

A data transmission method and the transmission circuit thereof for transmitting data between a host and a peripheral apparatus are disclosed. The data transmission method includes the following steps. First, a clock signal is transmitted by a first pin. Then, a data signal is transmitted by a second pin according to the timing of the clock signal.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.

FIG. 1 is a diagram illustrating the data transmission format according to an embodiment of the present invention.

FIG. 2 is a waveform of the data transmission format according to an embodiment of the present invention.

FIG. 3 is a schematic diagram of a data transmission circuit according to another embodiment of the present invention.

Claims

1. A data transmission method, comprising: transmitting a clock signal by a first pin; andtransmitting a data signal by a second pin according to the timing of the clock signal.

2. The data transmission method as claimed in claim 1, wherein the clock signal is transmitted from a host to a peripheral apparatus in the step of transmitting the clock signal.

3. The data transmission method as claimed in claim 2, wherein during the step of transmitting the data signal according to the timing of the clock signal, the data signal is reset if the clock signal produces a reset pulse.

4. The data transmission method as claimed in claim 3, wherein the data signal comprises: a data reset pulse, the data signal being reset at the reset pulse;an address signal block for transmitting an address data;a reading/writing determination block for transmitting a reading/writing determination data to set the reading/writing status of the data signal; anda data block, for transmitting data between the host and the peripheral apparatus and adjusting the data transmission direction between the host and the peripheral apparatus according to the reading/writing status of the data signal.

5. The data transmission method as claimed in claim 4, wherein during the occurring period of the reset pulse, the data signal produces a data reset pulse, and the rising edge of the data reset pulse is after the rising edge of the reset pulse, the falling edge of the data reset pulse is before the falling edge of the rest pulse.

6. The data transmission method as claimed in claim 4, wherein the data signal comprises: a pre-acknowledgement block, after the peripheral apparatus having completed receiving the data reset pulse, the address data, and the reading/writing determination data, the peripheral apparatus transmitting a pre-acknowledgement data to the host in the pre-acknowledgement block; andan after-acknowledgement block, being after the data block, the peripheral apparatus transmitting an after-acknowledgement data to the host in the after-acknowledgement block.

7. The data transmission method as claimed in claim 4, wherein the data reset pulse, the address data, and the reading/writing determination bits are all transmitted from the host to the peripheral apparatus.

8. The data transmission method as claimed in claim 4, wherein the data signal comprises: a start block, being between the data reset pulse and the address block, the host transmitting a start data to the peripheral apparatus in the start block.

9. A data transmission circuit, at least comprising: a first pin, for transmitting a clock signal; anda second pin, transmitting a data signal according to the timing of the clock signal.

10. The data transmission circuit as claimed in claim 9, wherein the clock signal is transmitted to a peripheral apparatus from a host when transmitting the clock signal.

11. The data transmission circuit as claimed in claim 10, wherein the data signal is reset if the clock signal produces a reset pulse when transmitting the data signal according to the timing of the clock signal.

12. The data transmission circuit as claimed in claim 11, wherein the data signal comprises: a data reset pulse, resetting the data signal at the reset pulse;an address signal block for transmitting an address data;a reading/writing determination block for transmitting a reading/writing determination data to set the reading/writing status of the data signal; anda data block for transmitting data between the host and the peripheral apparatus and adjusting the data transmission direction between the host and the peripheral apparatus according to the reading/writing status of the data signal.

13. The data transmission circuit as claimed in claim 12, wherein during the occurring period of the reset pulse, the data signal produces a data reset pulse, and the rising edge of the data reset pulse is after the rising edge of the reset pulse, the falling edge of the data reset pulse is before the falling edge of the rest pulse.

14. The data transmission circuit as claimed in claim 12, wherein if the reading/writing determination data is logic high voltage level, the data signal is in a reading status, and if the reading/writing determination data is logic low voltage level, the data signal is in a writing status.

15. The data transmission circuit as claimed in claim 12, wherein if the reading/writing determination bit is logic low voltage level, the data signal is in a reading status, and if the reading/writing determination bit is logic high voltage level, the data signal is in a writing status.

16. The data transmission circuit as claimed in claim 15, wherein the peripheral apparatus transmits data to the host in the data block if the data signal is in the reading status, and the host transmits data to the peripheral apparatus in the data block if the data signal is in the writing status.

17. The data transmission circuit as claimed in claim 12, wherein the data signal comprises: a pre-acknowledgement block, the peripheral apparatus transmitting a pre-acknowledgement data to the host in the pre-acknowledgement block after the peripheral apparatus having completed receiving the data reset pulse, the address data, and the reading/writing determination data; andan after-acknowledgement block, being after the data block, the peripheral apparatus transmitting an after-acknowledgement data to the host in the after-acknowledgement block.

18. The data transmission circuit as claimed in claim 12, wherein the data reset pulse, the address data, and the reading/writing determination bit are all transmitted from the host to the peripheral apparatus.

19. The data transmission circuit as claimed in claim 12, wherein the data signal comprises: a start block, being between the data reset pulse and the address block, the host transmitting a start data to the peripheral apparatus in the start block.

20. The data transmission circuit as claimed in claim 11, wherein the data signal is controlled by a complex programmable logic device (CPLD).