Patent Application
20220077875
This application relates to the field of communications technologies, and in particular, to a data transmission method, an encoding method, a decoding method, an apparatus, a device, and a storage medium.
A forward error correction (FEC) code can provide error correction protection for data that is being transmitted, so that a rate and a distance of transmitting data on a channel can be increased. In a data transmission process in which the FEC code is used, a sending device may encode original data by using a specific FEC code type, and send encoded data to a receiving device. The receiving device may decode the received data by using the same FEC code type, to obtain the original data.
In some scenarios, the FEC code type may need to be converted in the data transmission process. For example, to adapt to high-rate and/or long-distance data transmission, when an original FEC code type used by an original data transmission interface cannot meet a data transmission requirement, the FEC code type needs to be converted, so that the original FEC code type is replaced with a higher-gain FEC code type. However, an FEC code type conversion process usually increases a delay in the data transmission process and power consumption of a data transmission device. This affects data transmission efficiency.
In addition, an Ethernet interface is a widely used data transmission interface worldwide. As a rate is rapidly increased, FEC plays an increasingly important role in the Ethernet. As the rate and the transmission distance are continuously increased, a requirement for FEC becomes increasingly high.
Embodiments of this application provide a data transmission method, an encoding method, a decoding method, an apparatus, a device, and a storage medium, to resolve a problem in a related technology. Technical solutions are as follows.
According to a first aspect, an embodiment of this application provides a data transmission method. The method includes: A first chip receives a first data stream sent by a second chip, where the first data stream is a data stream obtained through encoding by using a first forward error correction (FEC) code type; the first chip re-encodes the first data stream at least once, to obtain a second data stream, where the second data stream is a concatenated FEC code stream obtained through encoding by using at least the first FEC code type and a second FEC code type; and the first chip sends the second data stream to a third chip. It can be learned that, for the first data stream that is obtained through encoding by using the first FEC code type and that is sent by the second chip to the first chip, the first chip does not need to first decode the first data stream by using the first FEC code type and then re-encode original data into a higher-gain FEC code type. Instead, the first chip may re-encode the first data stream at least once by using at least the second FEC code type, to obtain the second data stream formed by concatenating at least the first FEC code type and the second FEC code type, so as to obtain a higher gain. Therefore, an FEC code type conversion process is simplified, both a delay and device power consumption that are required during FEC code type conversion are reduced, and data transmission efficiency is improved.
With reference to any implementation of the first aspect, in a first possible implementation of the first aspect, the first FEC code comprises: an RS code, a BCH code, an extended BCH (eBCH) code, a Hamming Code, or an extended Hamming Code, a staircase code, an LDPC code, a Turbo code, or a TPC. It can be learned that the first chip may support encoding based on a plurality of different first FEC code types, to obtain a concatenated FEC code stream.
With reference to any implementation of the first aspect, in a second possible implementation of the first aspect, the second FEC code comprises: a BCH code, an extended BCH (eBCH) code, a Hamming Code, or an extended Hamming Code, an RS code, a staircase code, an LDPC code, a Turbo code, or a TPC. It can be learned that the first chip may support encoding based on the first FEC code type and a plurality of different second FEC code types, to obtain a concatenated FEC code.
With reference to any implementation of the first aspect, in a third possible implementation of the first aspect, that the first chip re-encodes the first data stream at least once, to form a second data stream includes: The first chip distributes the first data stream, to form n third data streams, where data of a same codeword block in the first data stream is distributed to different third data streams; and the first chip re-encodes each of the plurality of third data streams at least once, to form the second data stream. It can be learned that the data in the same codeword block in the first data stream may be encoded into a plurality of different codeword blocks in the second data stream, so that the concatenated FEC code has a stronger error correction capability.
With reference to the third implementation of the first aspect, in a fourth possible implementation of the first aspect, k codeword blocks identified from the first data stream are distributed to the n third data streams, and data that belongs to the k codeword blocks in each of the third data streams is encoded into one codeword block in the second data stream; and a total data volume included in the k first codeword blocks in the first data stream is equal to a payload data volume included in n second codeword blocks in the second data stream. Thus, the n second codeword blocks may be directly decoded into the original data based on the second FEC code type and the first FEC code type. This helps perform decoding operations on a same chip based on the first FEC code type and the second FEC code type. In some embodiments, a total data volume included in the k first codeword blocks in the first data stream is not equal to a payload data volume included in n second codeword blocks in the second data stream.
With reference to the third implementation of the first aspect, in a fifth possible implementation of the first aspect, data in the first data stream is distributed by FEC symbol block, and data in a same FEC symbol block in the first data stream is encoded into a same codeword block in the second data stream. It can be learned that the first chip may perform distribution processing on the first data stream at a symbol block granularity.
With reference to the third implementation of the first aspect, in a sixth possible implementation of the first aspect, data in the first data stream is distributed by bit stream, and data in the third data stream is encoded by bit stream. It can be learned that the first chip may perform distribution processing on the first data stream at a bit granularity.
With reference to any implementation of the first aspect, in a seventh possible implementation of the first aspect, the first chip and the second chip are located in a first data transmission device, the third chip is located in a second data transmission device, the first chip is an electrical chip, the second chip is a component that uses an Ethernet interface, and the third chip is an electrical chip. It can be learned that the first data transmission device may encode, by using the electrical chip, the first data stream that is based on the first FEC code type and that is output by the component using the Ethernet interface into the second data stream formed by concatenating at least the first FEC code type and the second FEC code type, and then send the second data stream to the second data transmission device. In this way, data is transmitted between the first data transmission device and the second data transmission device by using the concatenated FEC code.
With reference to any possible implementation of the first aspect, in an eighth possible implementation of the first aspect, the first data stream is transmitted between the second chip and the first chip through a physical lane with interference. It can be learned that, for the first data stream in which an error occurs when the first data stream is transmitted through the physical lane with interference, the first chip may directly re-encode the first data stream at least once without performing decoding and error correction on the first data stream, to form the concatenated second data stream.
According to a second aspect, an embodiment of this application provides a data transmission method. The method includes: A first chip receives a second data stream sent by a second chip, where the second data stream is a concatenated FEC code stream obtained through encoding by using at least a first FEC code type and a second FEC code type; the first chip decodes the second data stream at least once, to form a first data stream, where the first data stream is a data stream obtained through encoding by using the first FEC code type; and the first chip sends the first data stream to a third chip. It can be learned that, for the second data stream that is formed by concatenating at least the first FEC code type and the second FEC code type and that is sent by the second chip to the first chip, the first chip may decode the second data stream by using an FEC code type other than the first FEC code type, to form the first data stream that is obtained through encoding by using the first FEC code type, and send the first data stream to the third chip. In this way, the first chip does not need to decode the second data stream into original data, then re-encode the original data into a data stream that is based on the first FEC code type, and send the data stream to the third chip. Therefore, an FEC code type conversion process is simplified, both a delay and device power consumption that are required during FEC code type conversion are reduced, and data transmission efficiency is improved.
With reference to any possible implementation of the second aspect, in a first possible implementation of the second aspect, the first FEC code comprises: an RS code, a BCH code, an extended BCH (eBCH) code, a Hamming Code, or an extended Hamming Code, a staircase code, an LDPC code, a Turbo code, or a TPC.
With reference to any possible implementation of the second aspect, in a second possible implementation of the second aspect, the second FEC code comprises: a BCH code, an extended BCH (eBCH) code, a Hamming Code, or an extended Hamming Code, an RS code, a staircase code, an LDPC code, a Turbo code, or a TPC. It can be learned that the first chip may support decoding based on a plurality of different second FEC code types.
With reference to any possible implementation of the second aspect, in a third possible implementation of the second aspect, the first data stream is used to be decoded by the third chip based on the first FEC code type. It can be learned that the first chip may support decoding of a concatenated FEC code, to output a plurality of different first FEC code types.
With reference to any possible implementation of the second aspect, in a fourth possible implementation of the second aspect, the second chip is located in a first data transmission device, the first chip and the third chip are located in a second data transmission device, the first chip is an electrical chip, the second chip is an electrical chip, and the third chip is a component that uses an Ethernet interface. It can be learned that, for the second data stream that is formed by concatenating at least the first FEC code type and the second FEC code type and that is sent by the first data transmission device to the second data transmission device, the first data transmission device may decode, by using the electrical chip based on the second FEC code type, the second data stream into the first data stream that is based on the first FEC code type, and then send the first data stream that is based on the first FEC code type to the component that uses the Ethernet interface. In this way, data is transmitted between the first data transmission device and the second data transmission device by using the concatenated FEC code.
With reference to any possible implementation of the second aspect, in a fifth possible implementation of the second aspect, the first data stream is transmitted between the first chip and the third chip by using a physical medium. It can be learned that the first chip does not decode the second data stream into the original data. Instead, the first chip may decode, by using an FEC code type other than the first FEC code type, the second data stream into the first data stream obtained through encoding by using the first FEC code type. In this way, the first data stream is transmitted to the third chip by using a physical medium with interference, and the third chip decodes the first data stream to obtain the original data. The physical medium may be, for example, an optical fiber, an optical waveguide, a circuit, air, or the like.
According to a third aspect, an embodiment of this application provides a data transmission apparatus applied to a first chip. The apparatus includes a receiver, an encoder, and a transmitter. The receiver is configured to receive a first data stream sent by a second chip, where the first data stream is a data stream obtained through encoding by using a first forward error correction (FEC) code type. The encoder is configured to re-encode the first data stream at least once, to obtain a second data stream, where the second data stream is a concatenated FEC code stream obtained through encoding by using at least the first FEC code type and a second FEC code type. The transmitter is configured to send the second data stream to a third chip.
With reference to any implementation of the third aspect, in a first possible implementation of the third aspect, the first FEC code comprises: an RS code, a BCH code, an extended BCH (eBCH) code, a Hamming Code, or an extended Hamming Code, a staircase code, an LDPC code, a Turbo code, or a TPC.
With reference to any implementation of the third aspect, in a second possible implementation of the third aspect, the second FEC code comprises: a BCH code, an extended BCH (eBCH) code, a Hamming Code, or an extended Hamming Code, an RS code, a staircase code, an LDPC code, a Turbo code, or a TPC.
With reference to any implementation of the third aspect, in a third possible implementation of the third aspect, the encoder is specifically configured to: distribute the first data stream, to form n third data streams, where data of a same codeword block in the first data stream is distributed to different third data streams; and re-encode each of the plurality of third data streams at least once, to form the second data stream.
With reference to the third implementation of the third aspect, in a fourth possible implementation of the third aspect, k codeword blocks identified from the first data stream are distributed to the n third data streams, and data that belongs to the k codeword blocks in each of the third data streams is encoded into one codeword block in the second data stream; and a total data volume included in the k codeword blocks in the first data stream is equal to a payload data volume included in n codeword blocks in the second data stream.
With reference to the third implementation of the third aspect, in a fifth possible implementation of the third aspect, data in the first data stream is distributed by FEC symbol block, and data in a same FEC symbol block in the first data stream is encoded into a same codeword block in the second data stream.
With reference to the third implementation of the third aspect, in a sixth possible implementation of the third aspect, data in the first data stream is distributed by bit stream, and data in the third data stream is encoded by bit stream.
With reference to any implementation of the third aspect, in a seventh possible implementation of the third aspect, the first chip and the second chip are located in a first data transmission device, the third chip is located in a second data transmission device, the first chip is an electrical chip, the second chip is a component that uses an Ethernet interface, and the third chip is an electrical chip.
With reference to any possible implementation of the third aspect, in an eighth possible implementation of the third aspect, the first data stream is transmitted between the second chip and the first chip by using a physical medium. It can be learned that, for the first data stream in which an error occurs when the first data stream is transmitted by using a physical medium with interference, the first chip may directly re-encode the first data stream at least once without performing decoding and error correction on the first data stream, to form the concatenated second data stream.
It may be understood that the data transmission apparatus provided in the third aspect corresponds to the data transmission method provided in the first aspect. Therefore, for technical effects of various possible implementations of the data transmission apparatus provided in the third aspect, refer to the description of the data transmission method provided in the first aspect.
According to a fourth aspect, an embodiment of this application provides a data transmission apparatus applied to a first chip. The apparatus includes a receiver, a decoder, and a transmitter. The receiver is configured to receive a second data stream sent by a second chip, where the second data stream is a concatenated FEC code stream obtained through encoding by using at least a first FEC code type and a second FEC code type. The decoder is configured to decode the second data stream at least once, to form a first data stream, where the first data stream is a data stream obtained through encoding by using the first FEC code type. The transmitter is configured to send the first data stream to a third chip.
With reference to any possible implementation of the fourth aspect, in a first possible implementation of the fourth aspect, the first FEC code comprises: an RS code, a BCH code, an extended BCH (eBCH) code, a Hamming Code, or an extended Hamming Code, a staircase code, an LDPC code, a Turbo code, or a TPC.
With reference to any possible implementation of the fourth aspect, in a second possible implementation of the fourth aspect, the second FEC code comprises: a BCH code, an extended BCH (eBCH) code, a Hamming Code, or an extended Hamming Code, an RS code, a staircase code, an LDPC code, a Turbo code, or a TPC.
With reference to any possible implementation of the fourth aspect, in a third possible implementation of the fourth aspect, the first data stream is used to be decoded by the third chip based on the first FEC code type.
With reference to any possible implementation of the fourth aspect, in a fourth possible implementation of the fourth aspect, the second chip is located in a first data transmission device, the first chip and the third chip are located in a second data transmission device, the first chip is an electrical chip, the second chip is an electrical chip, and the third chip is a component that uses an Ethernet interface.
With reference to any possible implementation of the fourth aspect, in a fifth possible implementation of the fourth aspect, the first data stream is transmitted between the first chip and the third chip by using a physical medium. It can be learned that the first chip does not decode the second data stream into original data. Instead, the first chip may decode, by using an FEC code type other than the first FEC code type, the second data stream into the first data stream obtained through encoding by using the first FEC code type. In this way, the first data stream is transmitted to the third chip by using a physical medium with interference, and the third chip decodes the first data stream to obtain the original data.
It may be understood that the data transmission apparatus provided in the fourth aspect corresponds to the data transmission method provided in the second aspect. Therefore, for technical effects of various possible implementations of the data transmission apparatus provided in the fourth aspect, refer to the description of the data transmission method provided in the second aspect.
According to a fifth aspect, an embodiment of this application further provides a communication method. The communication method includes the data transmission method according to any implementation of the first aspect and the data transmission method according to any implementation of the second aspect.
According to a sixth aspect, an embodiment of this application further provides a communications system. The communications system includes the data transmission apparatus according to any implementation of the third aspect and the data transmission apparatus according to any implementation of the fourth aspect.
According to a seventh aspect, an embodiment of this application further provides a network device. The network device includes the data transmission apparatus according to any implementation of the third aspect.
According to an eighth aspect, an embodiment of this application further provides a network device. The network device includes the data transmission apparatus according to any implementation of the fourth aspect.
According to a ninth aspect, an embodiment of this application further provides a computer program product. When the computer program product is run on a computer, the computer is enabled to perform the data transmission method according to any implementation of the first aspect or the data transmission method according to any implementation of the second aspect.
According to a tenth aspect, an embodiment of this application further provides a computer-readable storage medium. The computer-readable storage medium stores instructions. When the instructions are run on a computer or a processor, the computer or the processor is enabled to perform the data transmission method according to any possible implementation of the first aspect or the data transmission method according to any possible implementation of the second aspect.
According to an eleventh aspect, a data encoding method is provided. The method includes: A first circuit receives a first data stream transmitted by a second circuit through an Ethernet interface, where the first data stream is obtained by encoding original data by using an RS code; and the first circuit performs BCH encoding on the first data stream, to obtain a second data stream. Two-level coding is implemented based on RS code and BCH code, so that a gain is higher, and a data transmission distance and a data transmission rate are increased.
With reference to the eleventh aspect, in a first possible implementation of the eleventh aspect, that a first circuit receives a first data stream transmitted by a second circuit through an Ethernet interface includes: The first circuit receives, from a plurality of physical lanes, the first data stream transmitted by the second circuit through the Ethernet interface; and the first circuit includes one or more BCH encoders, and that the first circuit performs BCH encoding on the first data stream, to obtain a second data stream includes: When a quantity of BCH encoders included in the first circuit is consistent with a quantity of physical lanes, where one BCH encoder is corresponds to one physical lane, the first circuit performs, by using the one or more BCH encoders, BCH encoding on the first data stream transmitted on a corresponding physical lane, to obtain the second data stream. When the quantity of BCH encoders is consistent with the quantity of physical lanes, the BCH encoders may be in a one-to-one correspondence with the physical lanes, so that a plurality of BCH encoders can perform encoding in parallel. This increases an encoding speed.
With reference to the eleventh aspect, in a second possible implementation of the eleventh aspect, that a first circuit receives a first data stream transmitted by a second circuit through an Ethernet interface includes: The first circuit receives, from a plurality of physical lanes, the first data stream transmitted by the second circuit through the Ethernet interface; and the first circuit includes one or more BCH encoders and further includes a scheduler, and that the first circuit performs BCH encoding on the first data stream, to obtain a second data stream includes: When a quantity of BCH encoders included in the first circuit is inconsistent with a quantity of physical lanes, the first circuit schedules, by using the scheduler, a corresponding BCH encoder to perform BCH encoding on the first data stream, to obtain the second data stream. No matter whether the quantity of BCH encoders is less than the quantity of physical lanes or the quantity of BCH encoders is greater than the quantity of physical lanes, the BCH encoder may be scheduled by using the scheduler, so as to connect the BCH encoder to a corresponding physical lane. In this way, BCH encoding is performed on the first data stream transmitted through the physical lane.
With reference to any possible implementation of the eleventh aspect, in a third possible implementation of the eleventh aspect, the performing BCH encoding on the first data stream includes: filling data in the first data stream into a corresponding BCH codeword, where a reference quantity of consecutive symbols included in each BCH codeword are from different RS codewords.
With reference to the third possible implementation of the eleventh aspect, in a fourth possible implementation of the eleventh aspect, after the data in the first data stream is interleaved based on the reference quantity of RS codewords, to obtain symbol stream data, the symbol stream data is output to a plurality of virtual lanes, the symbol stream data is bit-multiplexed based on the quantity of physical lanes, and bit-multiplexed symbol stream data is transmitted to the first circuit through the plurality of physical lanes. Because the first data stream on the plurality of physical lanes may arrive at the first circuit at different times, before the filling data in the first data stream into a corresponding BCH codeword, the method further includes: The first circuit demultiplexes the first data stream, to restore data on all virtual lanes, and aligns the data on all the virtual lanes, to obtain aligned data; and the filling data in the first data stream into a corresponding BCH codeword includes: filling the aligned data into the corresponding BCH codeword. Before BCH encoding is performed, the data on all the virtual lanes is first aligned, and then the aligned data is filled into the corresponding BCH codeword, so as to improve accuracy of BCH encoding.
With reference to the third or the fourth possible implementation of the eleventh aspect, in a fifth possible implementation of the eleventh aspect, the first data stream includes a first quantity of RS codewords, each RS codeword includes a first target quantity of symbols, and the data in the first data stream is interleaved based on the first quantity of RS codewords. Each BCH encoder corresponds to a second quantity of BCH codewords, each BCH codeword includes a second target quantity of symbols, the second target quantity is determined based on the first target quantity, and the second quantity is determined based on the first quantity. The filling data in the first data stream into a corresponding BCH codeword includes: sequentially filling the first half of data in each row of the first data stream into the first third quantity of BCH codewords in the second quantity of BCH codewords, and sequentially filling the second half of data in each row of the first data stream into the last third quantity of BCH codewords in the second quantity of BCH codewords, where the third quantity is half of the second quantity, and a first quantity of consecutive symbols included in each BCH codeword are from different RS codewords.
With reference to the fifth possible implementation of the eleventh aspect, in a sixth possible implementation of the eleventh aspect, the first target quantity is 544, the first quantity is 2, the second quantity is 32, and the second target quantity is 360. The filling data in the first data stream into a corresponding BCH codeword includes: sequentially filling the first half of data in each row of the first data stream into the first 16 BCH codewords in 32 BCH codewords, and sequentially filling the second half of data in each row of the first data stream into the last 16 BCH codewords in the 32 BCH codewords, where two consecutive symbols included in each BCH codeword are from different RS codewords.
With reference to the third or the fourth possible implementation of the eleventh aspect, in a seventh possible implementation of the eleventh aspect, the first data stream includes a first quantity of RS codewords, each RS codeword includes a first target quantity of symbols, the data in the first data stream is interleaved based on the first quantity of RS codewords, and symbols at the beginning or the end of each column of data in the first data stream are permuted. Each BCH encoder corresponds to a second quantity of BCH codewords, each BCH codeword includes a second target quantity of symbols, the second target quantity is determined based on the first target quantity, and the second quantity is determined based on the first quantity. The filling data in the first data stream into a corresponding BCH codeword includes: sequentially filling each column of data of the first data stream into the second quantity of BCH codewords, where a first quantity of consecutive symbols included in each BCH codeword are from different RS codewords.
With reference to the seventh possible implementation of the eleventh aspect, in an eighth possible implementation of the eleventh aspect, the first target quantity is 544, the first quantity is 2, the second quantity is 32, and the second target quantity is 360. The filling data in the first data stream into a corresponding BCH codeword includes: sequentially filling each column of data of the first data stream into 32 BCH codewords, where two consecutive symbols included in each BCH codeword are from different RS codewords.
With reference to the third or the fourth possible implementation of the eleventh aspect, in a ninth possible implementation of the eleventh aspect, the first data stream includes a first quantity of RS codewords, each RS codeword includes a first target quantity of symbols, and the data in the first data stream is interleaved based on the first quantity of RS codewords. Each BCH encoder corresponds to a second quantity of BCH codewords, each BCH codeword includes a second target quantity of symbols, the second target quantity is determined based on the first target quantity, and the second quantity is determined based on the first quantity. The filling data in the first data stream into a corresponding BCH codeword includes: de-interleaving the data in the first data stream, to obtain original RS codewords; interleaving the original RS codewords based on a fourth quantity of RS codewords, to obtain interleaved data, where the fourth quantity is greater than the first quantity; and sequentially filling each row of data of the interleaved data into the second quantity of BCH codewords, where a fourth quantity of consecutive symbols included in each BCH codeword are from different RS codewords.
In the fifth to ninth possible implementations of the eleventh aspect, the first target quantity may be determined based on an RS code type. For example, for RS (544, 514), the first target quantity is 544, and each RS codeword includes 544 symbols. The second target quantity may be determined based on the first target quantity. For RS (544, 514), BCH (360, 340) may be used, and the second target quantity is 360. For another example, for RS (528, 514), the first target quantity is 528, and each RS codeword includes 528 symbols. In addition, in the method provided in this embodiment of this application, two-level coding based on RS code and BCH code is used. A specific RS code type and a specific BCH code type are not limited in this embodiment of this application. In addition, the first target quantity of symbols and the second target quantity of symbols may be 10-bit symbols, or may be 1-bit symbols or symbols having another length. A length of a symbol is not limited in this embodiment of this application.
With reference to any possible implementation of the eleventh aspect, in a tenth possible implementation of the eleventh aspect, after the first circuit performs BCH encoding on the first data stream, to obtain the second data stream, the method further includes: transmitting the second data stream to a third circuit by using a medium through the plurality of physical lanes, or transmitting the second data stream to the third circuit by using the medium through one physical lane in a time division multiplexing mode.
According to a twelfth aspect, a data decoding method is provided. The method includes: A third circuit receives second data streams transmitted by a first circuit, where the second data streams are obtained through encoding by using an RS code and a BCH code; decodes the second data streams by using the BCH code, to obtain a first data stream; and decodes the first data stream by using the RS code, to obtain original data.
The first circuit uses two-level coding that is based on RS code and BCH code. Therefore, a gain is increased, so that a data transmission distance can be longer and a data transmission rate can be higher. After data is transmitted to the third circuit, the third circuit decodes the data based on a corresponding RS code and BCH code, so that the data can be successfully decoded.
With reference to the twelfth aspect, in a first possible implementation of the twelfth aspect, that a third circuit receives second data streams transmitted by a first circuit includes: receiving, by using a medium, the second data streams transmitted by the first circuit through a plurality of physical lanes, or receiving, by using the medium, the second data streams transmitted by the first circuit through one physical lane in a time division multiplexing mode. The first circuit may flexibly use one or more physical lanes to transmit the second data streams, and the third circuit may receive the second data streams in a manner in which the first circuit sends the second data streams.
With reference to the first possible implementation of the twelfth aspect, in a second possible implementation of the twelfth aspect, before the decoding the second data streams by using the BCH code, to obtain a first data stream, the method further includes: demultiplexing the second data streams when the second data streams transmitted by the first circuit through one physical lane in a time division multiplexing mode are received by using the medium; and the decoding the second data streams by using the BCH code, to obtain a first data stream includes: decoding demultiplexed data streams by using the BCH code, to obtain the first data stream.
With reference to the second possible implementation of the twelfth aspect, in a third possible implementation of the twelfth aspect, before the decoding the second data streams by using the BCH code, to obtain a first data stream, the method further includes: aligning the demultiplexed second data streams; and the decoding demultiplexed second data streams by using the BCH code, to obtain the first data stream includes: decoding aligned second data streams by using the BCH code, to obtain the first data stream. Before BCH decoding is performed, the demultiplexed second data streams are first aligned, and then the aligned second data streams are decoded by using the BCH code, so as to ensure accuracy of BCH decoding.
According to a thirteenth aspect, a data encoding apparatus is provided. The apparatus includes: a receiving module, configured to receive a first data stream transmitted by a second circuit through an Ethernet interface, where the first data stream is obtained by encoding original data by using an RS code; and an encoding module, configured to perform BCH encoding on the first data stream, to obtain a second data stream.
With reference to the thirteenth aspect, in a first possible implementation of the thirteenth aspect, the receiving module is configured to receive, from a plurality of physical lanes, the first data stream transmitted by the second circuit through the Ethernet interface. The apparatus includes one or more BCH encoders, and the encoding module is configured to: when a quantity of included BCH encoders is consistent with a quantity of physical lanes, where one BCH encoder is corresponds to one physical lane, perform, by using the one or more BCH encoders, BCH encoding on the first data stream transmitted on a corresponding physical lane, to obtain the second data stream.
With reference to the thirteenth aspect, in a second possible implementation of the thirteenth aspect, the receiving module is configured to receive, from a plurality of physical lanes, the first data stream transmitted by the second circuit through the Ethernet interface. The apparatus includes one or more BCH encoders and further includes a scheduler, and the encoding module is configured to: when a quantity of BCH encoders included in the first apparatus is inconsistent with a quantity of physical lanes, schedule, by using the scheduler, a corresponding BCH encoder to perform BCH encoding on the first data stream, to obtain the second data stream.
With reference to any possible implementation of the thirteenth aspect, in a third possible implementation of the thirteenth aspect, the encoding module is configured to fill data in the first data stream into a corresponding BCH codeword, where a reference quantity of consecutive symbols included in each BCH codeword are from different RS codewords.
With reference to the third possible implementation of the thirteenth aspect, in a fourth possible implementation of the thirteenth aspect, after the data in the first data stream is interleaved based on the reference quantity of RS codewords, to obtain symbol stream data, the symbol stream data is output to a plurality of virtual lanes, the symbol stream data is bit-multiplexed based on the quantity of physical lanes, and bit-multiplexed symbol stream data is transmitted to the apparatus through the plurality of physical lanes. The apparatus further includes: a demultiplexing module, configured to demultiplex the first data stream, to restore data on all virtual lanes; and an alignment module, configured to align the data on all the virtual lanes, to obtain aligned data. The encoding module is configured to fill the aligned data into the corresponding BCH codeword.
With reference to the third or the fourth possible implementation of the thirteenth aspect, in a fifth possible implementation of the thirteenth aspect, the first data stream includes a first quantity of RS codewords, each RS codeword includes a first target quantity of symbols, and the data in the first data stream is interleaved based on the first quantity of RS codewords. Each BCH encoder corresponds to a second quantity of BCH codewords, each BCH codeword includes a second target quantity of symbols, the second target quantity is determined based on the first target quantity, and the second quantity is determined based on the first quantity. The encoding module is configured to: sequentially fill the first half of data in each row of the first data stream into the first third quantity of BCH codewords in the second quantity of BCH codewords, and sequentially fill the second half of data in each row of the first data stream into the last third quantity of BCH codewords in the second quantity of BCH codewords, where the third quantity is half of the second quantity, and a first quantity of consecutive symbols included in each BCH codeword are from different RS codewords.
With reference to the fifth possible implementation of the thirteenth aspect, in a sixth possible implementation of the thirteenth aspect, the first target quantity is 544, the first quantity is 2, the second quantity is 32, and the second target quantity is 360. The encoding module is configured to: sequentially fill the first half of data in each row of the first data stream into the first 16 BCH codewords in 32 BCH codewords, and sequentially fill the second half of data in each row of the first data stream into the last 16 BCH codewords in the 32 BCH codewords, where two consecutive symbols included in each BCH codeword are from different RS codewords.
With reference to the third or the fourth possible implementation of the thirteenth aspect, in a seventh possible implementation of the thirteenth aspect, the first data stream includes a first quantity of RS codewords, each RS codeword includes a first target quantity of symbols, the data in the first data stream is interleaved based on the first quantity of RS codewords, and symbols at the beginning or the end of each column of data in the first data stream are permuted. Each BCH encoder corresponds to a second quantity of BCH codewords, each BCH codeword includes a second target quantity of symbols, the second target quantity is determined based on the first target quantity, and the second quantity is determined based on the first quantity. The encoding module is configured to sequentially fill each column of data of the first data stream into the second quantity of BCH codewords, where a first quantity of consecutive symbols included in each BCH codeword are from different RS codewords.
With reference to the seventh possible implementation of the thirteenth aspect, in an eighth possible implementation of the thirteenth aspect, the first target quantity is 544, the first quantity is 2, the second quantity is 32, and the second target quantity is 360. The encoding module is configured to sequentially fill each column of data of the first data stream into 32 BCH codewords, where two consecutive symbols included in each BCH codeword are from different RS codewords.
With reference to the third or the fourth possible implementation of the thirteenth aspect, in a ninth possible implementation of the thirteenth aspect, the first data stream includes a first quantity of RS codewords, each RS codeword includes a first target quantity of symbols, and the data in the first data stream is interleaved based on the first quantity of RS codewords. Each BCH encoder corresponds to a second quantity of BCH codewords, each BCH codeword includes a second target quantity of symbols, the second target quantity is determined based on the first target quantity, and the second quantity is determined based on the first quantity. The encoding module is configured to: de-interleave the data in the first data stream, to obtain original RS codewords; interleave the original RS codewords based on a fourth quantity of RS codewords, to obtain interleaved data, where the fourth quantity is greater than the first quantity; and sequentially fill each row of data of the interleaved data into the second quantity of BCH codewords, where a fourth quantity of consecutive symbols included in each BCH codeword are from different RS codewords.
With reference to any possible implementation of the thirteenth aspect, in a tenth possible implementation of the thirteenth aspect, the apparatus further includes: a transmission module, configured to: transmit the second data stream to a third circuit by using a medium through the plurality of physical lanes, or transmit the second data stream to the third circuit by using the medium through one physical lane in a time division multiplexing mode.
According to a fourteenth aspect, a data decoding apparatus is provided. The apparatus includes: a receiving module, configured to receive second data streams transmitted by a first circuit, where the second data streams are obtained through encoding by using an RS code and a BCH code; a first decoding module, configured to decode the second data streams by using the BCH code, to obtain a first data stream; and a second decoding module, configured to decode the first data stream by using the RS code, to obtain original data.
With reference to the fourteenth aspect, in a first possible implementation of the fourteenth aspect, the receiving module is configured to: receive, by using a medium, the second data streams transmitted by the first circuit through a plurality of physical lanes, or receive, by using the medium, the second data streams transmitted by the first circuit through one physical lane in a time division multiplexing mode.
With reference to the first possible implementation of the fourteenth aspect, in a second possible implementation of the fourteenth aspect, the apparatus further includes: a demultiplexing module, configured to demultiplex the second data streams when the second data streams transmitted by the first circuit through one physical lane in a time division multiplexing mode are received by using the medium. The first decoding module is configured to decode demultiplexed data streams by using the BCH code, to obtain the first data stream.
With reference to the second possible implementation of the fourteenth aspect, in a third possible implementation of the fourteenth aspect, the apparatus further includes: an alignment module, configured to align the demultiplexed second data streams. The first decoding module is configured to decode aligned second data streams by using the BCH code, to obtain the first data stream.
According to any one of the eleventh to fourteenth aspects or the possible implementation of these aspects, the BCH code may be replaced with an extended BCH (eBCH) code, a Hamming Code, or an extended Hamming Code; accordingly, the BCH encoder can replaced with an extended eBCH code encoder, a Hamming Code encoder, or an extended Hamming Code encoder.
According to a fifteenth aspect, a data transmission device is provided. The device includes a memory and a processor. The memory stores at least one instruction, and the at least one instruction is loaded and executed by the processor, to implement the method according to any possible implementation of the eleventh aspect or the twelfth aspect of this application.
According to a sixteenth aspect, a communications apparatus is provided. The apparatus includes a transceiver, a memory, and a processor. The transceiver, the memory, and the processor communicate with each other through an internal connection path. The memory is configured to store instructions. The processor is configured to execute the instructions stored in the memory, to control the transceiver to receive a signal, and control the transceiver to send a signal. In addition, when the processor executes the instructions stored in the memory, the processor is enabled to perform the method according to any possible implementation of the eleventh aspect or the twelfth aspect.
Optionally, there are one or more processors, and there are one or more memories.
Optionally, the memory may be integrated with the processor, or the memory and the processor are separately disposed.
In a specific implementation process, the memory may be a non-transitory memory, such as a read-only memory (ROM). The memory and the processor may be integrated into one chip, or may be disposed in different chips. A type of the memory and a manner in which the memory and the processor are disposed are not limited in the embodiments of this application.
According to a seventeenth aspect, a computer program (product) is provided. The computer program (product) includes computer program code; and when the computer program code is run by a computer, the computer is enabled to perform the method according to any possible implementation of the eleventh aspect or the twelfth aspect.
According to an eighteenth aspect, a readable storage medium is provided. The readable storage medium stores a program or instructions. When the program or the instructions is/are run on a computer, the method according to any possible implementation of the eleventh aspect or the twelfth aspect is performed.
According to a nineteenth aspect, a chip is provided. The chip includes a processor. The processor is configured to invoke and run instructions stored in a memory, so that a communications device on which the chip is installed performs the method according to any possible implementation of the eleventh aspect or the twelfth aspect.
According to a twentieth aspect, another chip is provided. The chip includes an input interface, an output interface, a processor, and a memory. The input interface, the output interface, the processor, and the memory are connected to each other through an internal connection path. The processor is configured to execute code in the memory, and when the code is executed, the processor is configured to perform the method according to any possible implementation of the eleventh aspect or the twelfth aspect.
Terms used in implementations of this application are merely used to explain embodiments of this application, but are not intended to limit this application.
In a data transmission process in which an FEC code is used, a sending device may encode original data by using a specific FEC code type, and then send an FEC code obtained through encoding to a receiving device. The receiving device may decode the received FEC code by using the same FEC code type, to obtain the original data. In this way, even if an error occurs at some locations in the FEC code on a transmission channel, the receiving device may obtain the original data that exists before the error occurs by performing reverse calculation based on a parity bit in the FEC code during decoding. This implements an error correction function.
In some scenarios, the FEC code type may need to be converted in the data transmission process. For example, as an enhanced FEC code type, a concatenated FEC code is a multi-level FEC code obtained by performing code type construction on one or more basic FEC code types. This can provide stronger error correction protection for transmitted data. Therefore, the concatenated FEC code may be used to transmit data between devices, to cope with noise introduced when the data is transmitted at a high rate or over a long distance. However, an original FEC code type used by an original data transmission interface of a device is a code type specified in a standard. For example, original Ethernet interfaces of many devices support only a Reed-Solomon (RS) code. When the device is applied to a data transmission scenario with a higher rate or a longer distance than that specified in the standard, the FEC code type specified in the standard cannot meet a requirement. Therefore, the device needs to convert to-be-transmitted data from the original FEC code type to a higher-gain FEC code type. Generally, when the FEC code type is converted, data encoded by using the original FEC code type needs to be decoded into original data, and then the original data is encoded by using a new FEC code type. However, such a conversion process not only causes additional power consumption to a data transmission device, but also increases a delay in the data transmission process.
In the embodiments of this application, a concatenated FEC code is an FEC code type that can provide a high gain for high-rate and/or long-distance data transmission, and the concatenated FEC code is obtained by concatenating a plurality of levels of FEC code types. Therefore, in data transmission between two chips, when a chip receives a first data stream obtained through encoding by using a first FEC code type, the chip does not need to first decode the first data stream by using the first FEC code type and then re-encode original data into a concatenated FEC code. Instead, the chip may re-encode the first data stream at least once by using at least a second FEC code type, to obtain a second data stream formed by concatenating at least the first FEC code type and the second FEC code type, so as to obtain a higher gain. Therefore, an FEC code type conversion process is simplified, both a delay and device power consumption that are required during FEC code type conversion are reduced, and data transmission efficiency is improved.
For example, the embodiments of this application may be applied to a scenario shown in
In this application, a “physical lane” and a “physical medium” are often interchangeable. A person skilled in the art may understand that the “physical lane” is a lane for transmitting data in the “physical medium”.
It may be understood that the foregoing scenario is merely a scenario example provided in the embodiments of this application, and the embodiments of this application are not limited to this scenario.
With reference to the accompanying drawings, the following uses embodiments to describe in detail specific implementations of a data transmission method and apparatus in the embodiments of this application.
201: A chip 1 receives a first data stream sent by a chip 2, where the first data stream is a data stream obtained through encoding by using a first forward error correction (FEC) code type.
In specific implementation, the chip 2 may encode original data by using the first FEC code type, to form the first data stream, and send the first data stream to the chip 1. Therefore, the first data stream received by the chip 1 is a data stream obtained through encoding by using the first FEC code type. In other words, the first data stream is a code stream including codeword blocks of the first FEC code type.
The first FEC code type may be a code type such as an RS code, a BCH code, an extended BCH (eBCH) code, a Hamming Code, or an extended Hamming Code, a staircase code, a low density parity check (LDPC) code, a Turbo code, or a Turbo product code (TPC). For example, in an example scenario, assuming that the chip 2 communicates with the chip 1 through an Ethernet interface, the first FEC code type may be an RS code.
It may be understood that the codeword block of the first FEC code type includes an additional parity code provided for the original data, and the parity code is used to correct an error that occurs in a data transmission process. For example, the first FEC code type may be a systematic FEC code, that is, the codeword block of the first FEC code type may include the original data and the parity code provided for the original data.
The codeword block of the first FEC code type may be processed based on a finite field. The codeword block may be divided into a plurality of FEC symbol blocks, and processing on the codeword block may be performed at an FEC symbol block granularity. For example, in an RS code, a 5440-bit codeword block includes 5140-bit original data and a 300-bit parity code. If a Galois field (GFt) 210 is used for processing, and every 10 bits of data constitute one FEC symbol block, one codeword block includes 544 FEC symbol blocks, to be specific, original data including 514 FEC symbol blocks and a parity code including 30 FEC symbol blocks. For another example, in another RS code, a 5280-bit codeword block includes 5140-bit original data and a 140-bit parity code. If a GF 210 is used for processing, and every 10 bits of data constitute one FEC symbol block, one codeword block includes 528 FEC symbol blocks, to be specific, original data including 514 FEC symbol blocks and a parity code including 14 FEC symbol blocks. It may be understood that, for consecutive errors, also referred to as burst errors, multi-bit consecutive errors are equivalent to errors of only a small quantity of FEC symbol blocks. Therefore, processing an FEC codeword block at an FEC symbol block granularity provides a stronger FEC error correction capability.
It may be understood that the chip 1 and the chip 2 are two different chips, and data may be transmitted between the chip 1 and the chip 2 through a physical lane with interference. Therefore, an error occurs in the first data stream due to the interference when the first data stream sent by the chip 2 to the chip 1 is transmitted on the physical lane. It can be learned that the first data stream received by the chip 1 is a data stream in which an error has occurred.
202: The chip 1 re-encodes the first data stream at least once, to obtain a second data stream, where the second data stream is a concatenated FEC code stream obtained through encoding by using at least the first FEC code type and a second FEC code type.
In specific implementation, for the first data stream that is obtained through encoding by using the first FEC code type, the chip 1 does not need to first decode the first data stream by using the first FEC code type into original data. Instead, the chip 1 may re-encode the first data stream at least once by using at least the second FEC code type, so as to form the second data stream by concatenating at least the first FEC code type and the second FEC code type. In other words, the second data stream may be a concatenated FEC code stream that is obtained by concatenating the first FEC code type and the second FEC code type, that is, the second data stream is a two-level concatenated FEC code stream; or the second data stream may be a data stream that is obtained by concatenating one or more levels of concatenated FEC code streams based on concatenation of the first FEC code type and the second FEC code type, that is, the second data stream is a three-level concatenated FEC code stream or a concatenated FEC code stream with more than three levels. It may be understood that, if the chip 2 sends the first data stream to the chip 1 through the physical lane with interference, the first data stream received by the chip 1 is a data stream in which an error has occurred. Therefore, the chip 1 does not decode the first data stream in which an error has occurred. Instead, the chip 1 directly re-encodes, at least once, the first data stream in which an error has occurred, so as to form the second data stream by concatenating a plurality of levels of FEC code stream.
The second FEC code type may be a code such as a BCH code, an extended BCH (eBCH) code, a Hamming Code, or an extended Hamming Code, an RS code, a staircase code, an LDPC code, a Turbo code, or a TPC. It may be understood that the second FEC code type may be the same as the first FEC code type, or the second FEC code type may be different from the first FEC code type. For example, both the first FEC code and the second FEC code may be an RS code; or the first FEC code may be an RS code, and the second FEC code may be a BCH code.
It should be noted that the second data stream is a code stream including a codeword block of an FEC code type that is used for last-level coding. For example, if the second data stream is a data stream formed by concatenating the first FEC code type and the second FEC code type, the first FEC code type is used for first-level coding, and the second FEC code type is used for second-level coding, the second data stream is a code stream including a codeword block of the second FEC code type. Because the second data stream is obtained through encoding by using the second FEC code type based on the first data stream, the codeword block of the second FEC code type includes an additional parity code provided for the first data stream. If the second FEC code type is a systematic code, the codeword block of the second FEC code type includes data in the first data stream and a parity code provided for the data.
In some implementations, to make an error correction capability stronger, data in a same codeword block in the first data stream may be encoded into a plurality of different codeword blocks in the second data stream. In this way, even if a small part of codeword blocks in the second data stream cannot be correctly decoded, correct decoding of the codeword block in the first data stream is not affected. In specific implementation, the chip 1 may distribute the first data stream to n different lanes in a distribution manner, to form n third data streams, so that data in a same codeword block in the first data stream is distributed to a plurality of different third data streams, where n represents a natural number greater than 1. Then, the chip 1 may re-encode each of the third data streams on the n lanes at least once, to form the second data stream. For example, in an example in
It may be understood that the first data stream may be a data stream on one lane, or may include data streams on a plurality of lanes. In other words, the first data stream may be one code stream, or may include a plurality of code streams.
If the first data stream is a data stream on one lane, the first data stream is distributed to form third data streams. This is equivalent to that one data stream is distributed to form a plurality of data streams. For example, in an example shown in
If the first data stream includes data streams on a plurality of lanes, that the first data stream is distributed to form the third data stream is equivalent to that a plurality of data streams are distributed to form a plurality of data streams, and such distribution may be implemented according to a distribution policy such as an interleaving technology and/or a multiplexing technology. For example, in an example shown in
It should be noted that a plurality of distribution manners may be used to distribute the first data stream to form the n third data streams.
In an example, the chip 1 may perform distribution processing on the first data stream at a bit granularity, that is, data in the first data stream may be distributed to the n third data streams by bit stream. During specific implementation, the chip 1 may obtain one-bit data from the first data stream, and select a lane for the data from the n lanes according to a distribution policy, so as to distribute the data to a third data stream on the lane. Correspondingly, the chip 1 may also perform encoding processing on the third data stream at a bit granularity, that is, data in the third data stream may be encoded by bit stream.
In another example, the chip 1 may perform distribution processing on the first data stream at an FEC symbol block granularity, that is, data in the first data stream may be distributed by FEC symbol block. During specific implementation, the chip 1 may identify an FEC symbol block from the first data stream, and select a lane for the FEC symbol block from the n lanes according to a distribution policy, so as to distribute the FEC symbol block to a third data stream on the lane. Correspondingly, the chip 1 may also encode the third data stream at an FEC symbol block granularity. During specific implementation, the chip 1 may identify a specific quantity of FEC symbol blocks from the third data stream and encode the FEC symbol blocks into a same codeword block in the second data stream. Therefore, data in a same FEC symbol block in the first data stream is encoded into a same codeword block in the second data stream. The FEC symbol block may be identified by using an alignment marker (AM).
In still another example, the chip 1 may perform distribution processing on the first data stream at a granularity of a plurality of codeword blocks. During specific implementation, the chip 1 may identify a plurality of codeword blocks from the first data stream, and distribute the plurality of codeword blocks to third data streams on the n lanes according to a distribution policy. The distribution policy may be implemented, for example, by using an interleaving technology and/or a multiplexing technology. In addition, the first data stream may be one code stream, that is, the plurality of codeword blocks may be identified from one code stream; or the first data stream may include a plurality of code streams, that is, the k codeword blocks may be identified from a plurality of code streams, for example, the first data stream includes k code streams, and the plurality of codeword blocks may be k codeword blocks obtained by identifying one codeword block from each code stream.
To facilitate decoding of the second data stream into original data on a same chip, the chip 1 may use all data of the k codeword blocks in the first data stream as payloads of n codeword blocks in the second data stream, so that the k codeword blocks in the first data stream are encoded into the n codeword blocks in the second data stream. During specific implementation, the chip 1 may identify the k codeword blocks from the first data stream, and distribute the k codeword blocks to third data streams on the n lanes according to a distribution policy. Data of the k codeword blocks that is distributed to each lane may be encoded into one codeword block in the second data stream, so as to obtain the n codeword blocks in the second data stream through encoding on the n lanes. For example, in the example shown in
To enable the k codeword blocks in the first data stream to be encoded into the n codeword blocks in the second data stream, a total data volume included in the k codeword blocks in the first data stream needs to be equal to a payload data volume included in the n codeword blocks in the second data stream. For example, it is assumed that the first data stream is an RS code stream and the second data stream is a BCH code stream, an RS codeword block of the first data stream includes a 5140-bit payload and a 300-bit parity code, and a BCH codeword block of the second data stream includes a 340-bit payload and a 20-bit parity code. It can be learned that a total data volume of four RS codeword blocks is 21760 bits, and a payload data volume of 64 BCH codeword blocks is also 21760 bits. Therefore, the four RS codeword blocks of the first data stream may be encoded into the 64 BCH codeword blocks of the second data stream.
203: The chip 1 sends the second data stream to a chip 3.
After receiving the second data stream, the chip 3 may decode the second data stream. In this way, data is transmitted between the chip 1 and the chip 3 by using a concatenated FEC code.
In an example, the chip 3 may decode all FEC code types including the first FEC code type and the second FEC code type in the second data stream, to obtain the original data. In another example, the chip 3 may decode an FEC code type other than the first FEC code type in the second data stream, to obtain the first data stream, and send the first data stream to a chip 4. Then, the chip 4 decodes the first FEC code type in the first data stream, to obtain the original data. It may be understood that the chip 1 and the chip 3 are two different chips, and data may be transmitted between the chip 1 and the chip 3 through a physical lane with interference. Similarly, the chip 3 and the chip 4 are two different chips, and data may be transmitted between the chip 3 and the chip 4 through a physical lane. Therefore, an error occurs in the second data stream due to the interference of the physical lane when the second data stream sent by the chip 1 to the chip 3 is transmitted on the physical lane. The chip 3 does not decode or correct the second data stream in which an error has occurred into the original data. Instead, the chip 3 decodes the second data stream that is obtained by concatenating FEC into the first data stream that is obtained through encoding by using the first FEC code type; and sends the first data stream to the chip 4. When the first data stream sent by the chip 3 to the chip 4 is transmitted on the physical lane, an error occurs again due to the interference. In this case, the chip 4 decodes and corrects the first data stream into the original data. It can be learned that the first data stream received by the chip 1 is a data stream in which an error has occurred.
For the concatenated FEC codes in the second data stream, decoding of each level of FEC code type may be implemented by identifying a codeword block of the level of FEC code type and performing reverse calculation on the identified codeword block. For example, if the second data stream is formed by concatenating the first FEC code type and the second FEC code type, when the second data stream is decoded, a codeword block of the second FEC code type may be identified from the second data stream in a manner such as the AM, a self-synchronization technology, or the like, and reverse calculation is performed on the codeword block of the second FEC code type, to obtain the first data stream; and then a codeword block of the first FEC code type may be identified from the first data stream in a manner such as a fixed mapping relationship between the codeword block of the second FEC code type and the codeword block of the first FEC code type, the AM, or the like, and reverse calculation is performed on the codeword block of the first FEC code type, to obtain the original data.
In an example scenario, as shown in
It should be noted that the concatenated FEC code provided in this embodiment achieves a relatively good error correction effect in simulation verification. It is assumed that simulation verification is performed in the example scenario shown in
A result of simulation verification performed in the foregoing simulation environment shows that, in comparison with that the chip 1 first decodes the code stream that is based on the first FEC code type and then performs multi-level coding, to form the concatenated FEC code stream, that the chip 1 does not decode the code stream that is based on the first FEC code type, but instead, the chip 1 re-encodes, by using the second FEC code type, the code stream that is based on the first FEC code type, to form the concatenated FEC code stream can reduce a delay of 60 to 100 ns, and achieve a net coding gain (NCG) of more than 9 dB.
In this embodiment, for the first data stream that is obtained through encoding by using the first FEC code type and that is sent by the chip 2 to the chip 1, the chip 1 does not need to first decode the first data stream by using the first FEC code type and then re-encode original data into a concatenated FEC code. Instead, the chip 1 may re-encode the first data stream at least once by using at least the second FEC code type, to obtain the second data stream formed by concatenating at least the first FEC code type and the second FEC code type. Therefore, an FEC code type conversion process is simplified, both a delay and device power consumption that are required during FEC code type conversion are reduced, and data transmission efficiency is improved.
801: A chip 3 receives a second data stream sent by a chip 1, where the second data stream is a concatenated FEC code stream obtained through encoding by using at least a first FEC code type and a second FEC code type.
802: The chip 3 decodes the second data stream at least once, to form a first data stream, where the first data stream is a data stream obtained through encoding by using the first FEC code type.
803: The chip 3 sends the first data stream to a chip 4.
After receiving the first data stream, the chip 4 may decode the first data stream based on the first FEC code type, to obtain original data.
The first FEC code type may be a code type such as an RS code, a BCH code, an extended BCH (eBCH) code, a Hamming Code, or an extended Hamming Code, a staircase code, an LDPC code, a Turbo code, or a TPC. The second FEC code type may be a code type such as a BCH code, an eBCH code, a Hamming Code, or an extended Hamming Code, an RS code, a staircase code, an LDPC code, a Turbo code, or a TPC.
In an example scenario, the chip 1 may be located in a first data transmission device, the chip 3 and the chip 4 may be located in a second data transmission device, the chip 3 and the chip 1 may be electrical chips, for example, relay electrical chips or electrical chips of optical modules, and the chip 4 may be a chip that uses an Ethernet interface.
It may be understood that this embodiment corresponds to a process of decoding the second data stream, and the embodiment shown in
In this embodiment, for the second data stream that is formed by concatenating at least the first FEC code type and the second FEC code type and that is sent by the chip 1 to the chip 3, the chip 3 may decode the second data stream by using an FEC code type other than the first FEC code type, to form the first data stream that is obtained through encoding by using the first FEC code type, and send the first data stream to the chip 4. In this way, the chip 3 does not need to decode the second data stream into original data, then re-encode the original data into a data stream that is based on the first FEC code type, and send the data stream to the chip 4. Therefore, an FEC code type conversion process is simplified, both a delay and device power consumption that are required during FEC code type conversion are reduced, and data transmission efficiency is improved.
The following describes, by using a specific scenario example, an example in which the data transmission method provided in the embodiments of this application is applied to a specific scenario. In this specific scenario example, a first data transmission device includes a first PHY layer chip and a first optical module, and the first optical module has a first DSP chip; and a second data transmission device includes a second PHY layer chip and a second optical module, and the second optical module has a second DSP chip. Data is transmitted between the first data transmission device and the second data transmission device by using a concatenated FEC code, and the first PHY layer chip and the second PHY layer chip support an RS code but do not support the concatenated FEC code. In this specific scenario, as shown in
901: The first PHY chip encodes original data once by using an RS code, to form an RS code stream.
902: The first PHY chip sends the RS code stream to the first DSP.
903: The first DSP re-encodes the RS code stream once by using a BCH code, to form a BCH code stream.
The BCH code stream is actually a concatenated FEC code stream formed by concatenating the RS code and the BCH code.
904: The first DSP sends the BCH code stream to the second DSP.
905: The second DSP decodes the BCH code stream once by using the BCH code, to form the RS code stream.
906: The second DSP sends the RS code stream to the second PHY chip.
907: The second PHY chip re-decodes the RS code stream by using the RS code, to obtain the original data.
In this embodiment, the first DSP does not need to first decode the RS code stream by using the RS code and then re-encode the original data into the concatenated FEC code stream. Instead, the first DSP may re-encode the RS code stream at least once by using the BCH code, to form the concatenated FEC code stream obtained by concatenating the RS code and the BCH code. In this way, data can be transmitted between the first DSP and the second DSP by using the concatenated FEC code stream. In addition, the second DSP does not need to decode the concatenated FEC code stream into the original data and then re-encode the original data into the RS code stream. Instead, the second DSP may decode the concatenated FEC code stream once by using the BCH code, to form the RS code stream. In this way, the second PHY chip can receive the RS code stream. Therefore, an FEC code type conversion process is simplified, both a delay and device power consumption that are required during FEC code type conversion are reduced, and data transmission efficiency is improved.
1001: Identify k first codeword blocks from a first data stream.
The first data stream is a data stream obtained through encoding by using the first FEC code type. Therefore, the first codeword block in the first data stream is a codeword block of the first FEC code type. The first codeword block may be identified from the first data stream by using an AM.
1002: Distribute data of the k first codeword blocks to n lanes.
A distribution policy may be implemented by using an interleaving technology and/or a multiplexing technology. For example, k first FEC codeword blocks may be input into an interleaver, data output by the interleaver to m lanes is then input into a multiplexer such as a bit multiplexeror a symbol multiplexer, and the multiplexer outputs data on the n lanes.
1003: Encode data that is from the k first codeword blocks and that is distributed to each lane on the lane by using the second FEC code type, to form one second codeword block, so that n second codeword blocks in a second data stream are obtained on the n lanes.
On each lane, the data from the k first codeword blocks is encoded into one second codeword block as a payload, that is, the payload of the second codeword block is the data that is from the k first codeword blocks and that is distributed to the lane. Therefore, all payloads of the n second codeword blocks that are obtained through encoding on the n lanes are all data of the k first codeword blocks, that is, a total data volume of the k first codeword blocks needs to be equal to a payload data volume of the n second codeword blocks.
In this embodiment, the n second codeword blocks may be directly decoded into original data based on the second FEC code type and the first FEC code type. This helps perform decoding operations on a same chip based on the first FEC code type and the second FEC code type. In some embodiments, a total data volume included in the k first codeword blocks in the first data stream is not equal to a payload data volume included in n second codeword blocks in the second data stream.
1101: A first chip receives a first data stream sent by a second chip, where the first data stream is a data stream obtained through encoding by using a first forward error correction (FEC) code type.
1102: The first chip re-encodes the first data stream at least once, to obtain a second data stream, where the second data stream is a concatenated FEC code stream obtained through encoding by using at least the first FEC code type and a second FEC code type.
In some possible implementations, the first FEC code type is specifically: an RS code, a BCH code, an extended BCH (eBCH) code, a Hamming Code, or an extended Hamming Code, a staircase code, an LDPC code, a Turbo code, or a Turbo product code (TPC).
In some possible implementations, the second FEC code type is specifically: a BCH code, an extended BCH (eBCH) code, a Hamming Code, or an extended Hamming Code, an RS code, a staircase code, an LDPC code, a Turbo code, or a TPC.
In some possible implementations, that the first chip re-encodes the first data stream at least once, to form a second data stream includes: the first chip distributes the first data stream, to form n third data streams, where data of a same codeword block in the first data stream is distributed to different third data streams; and the first chip re-encodes each of the plurality of third data streams at least once, to form the second data stream.
In some possible implementations, k codeword blocks identified from the first data stream are distributed to the n third data streams, and data that belongs to the k codeword blocks in each of the third data streams is encoded into one codeword block in the second data stream; and a total data volume included in the k codeword blocks in the first data stream is equal to a payload data volume included in n codeword blocks in the second data stream.
In some possible implementations, data in the first data stream is distributed by FEC symbol block, and data in a same FEC symbol block in the first data stream is encoded into a same codeword block in the second data stream.
In some possible implementations, data in the first data stream is distributed by bit stream, and data in the third data stream is encoded by bit stream.
In some possible implementations, the first chip and the second chip are located in a same data transmission device, the first chip is an electrical chip, and the second chip is a chip that uses an Ethernet interface.
It may be understood that the first chip is the chip 1 mentioned in the data transmission method 200, the second chip is the chip 2 mentioned in the data transmission method 200, and a third chip is the chip 3 mentioned in the data transmission method. Therefore, for various specific implementations of operations performed by the first chip, the second chip, and the third chip in this embodiment, refer to the descriptions of the chip 1, the chip 2, and the chip 3 in the data transmission method 200 shown in
In this embodiment, for the first data stream that is obtained through encoding by using the first FEC code type and that is sent by the chip 2 to the chip 1, the chip 1 does not need to first decode the first data stream by using the first FEC code type and then re-encode original data into a concatenated FEC code. Instead, the chip 1 may re-encode the first data stream at least once by using at least the second FEC code type, to obtain the second data stream formed by concatenating at least the first FEC code type and the second FEC code type. Therefore, an FEC code type conversion process is simplified, both a delay and device power consumption that are required during FEC code type conversion are reduced, and data transmission efficiency is improved.
1201: A first chip receives a second data stream sent by a second chip, where the second data stream is a concatenated FEC code stream obtained through encoding by using at least a first FEC code type and a second FEC code type.
1202: The first chip decodes the second data stream at least once, to form a first data stream, where the first data stream is a data stream obtained through encoding by using the first FEC code type.
1203: The first chip sends the first data stream to a third chip.
In some possible implementations, the first FEC code type is specifically: an RS code, a BCH code, an extended BCH (eBCH) code, a Hamming Code, or an extended Hamming Code, a staircase code, an LDPC code, a Turbo code, or a TPC.
In some possible implementations, the second FEC code type is specifically: a BCH code, an extended BCH (eBCH) code, a Hamming Code, or an extended Hamming Code, an RS code, a staircase code, an LDPC code, a Turbo code, or a TPC.
In some possible implementations, the first data stream is used to be decoded by the third chip based on the first FEC code type.
In some possible implementations, the second chip is located in a first data transmission device, the first chip and the third chip are located in a second data transmission device, the first chip is an electrical chip, the second chip is an electrical chip, and the third chip is a chip that uses an Ethernet interface.
It may be understood that the first chip is the chip 3 mentioned in the data transmission method 200, the second chip is the chip 1 mentioned in the data transmission method 200, and the third chip is the chip 4 mentioned in the data transmission method 200. Therefore, for various specific implementations of operations performed by the first chip, the second chip, and the third chip in this embodiment, refer to the descriptions of the chip 3, the chip 1, and the chip 4 in the data transmission method 200 shown in
In this embodiment, for the second data stream that is formed by concatenating at least the first FEC code type and the second FEC code type and that is sent by the second chip to the first chip, the first chip may decode the second data stream by using an FEC code type other than the first FEC code type, to form the first data stream that is obtained through encoding by using the first FEC code type, and send the first data stream to the third chip. In this way, the first chip does not need to decode the second data stream into original data, then re-encode the original data into a data stream that is based on the first FEC code type, and send the data stream to the third chip. Therefore, an FEC code type conversion process is simplified, both a delay and device power consumption that are required during FEC code type conversion are reduced, and data transmission efficiency is improved.
In some possible implementations, the first FEC code type is specifically: an RS code, a BCH code, an extended BCH (eBCH) code, a Hamming Code, or an extended Hamming Code, a staircase code, an LDPC code, a Turbo code, or a TPC.
In some possible implementations, the second FEC code type is specifically: a BCH code, an extended BCH (eBCH) code, a Hamming Code, or an extended Hamming Code, an RS code, a staircase code, an LDPC code, a Turbo code, or a TPC.
In some possible implementations, the encoder 1302 is specifically configured to: distribute the first data stream, to form n third data streams, where data of a same codeword block in the first data stream is distributed to different third data streams; and re-encode each of the plurality of third data streams at least once, to form the second data stream.
In some possible implementations, k codeword blocks identified from the first data stream are distributed to the n third data streams, and data that belongs to the k codeword blocks in each of the third data streams is encoded into one codeword block in the second data stream; and a total data volume included in the k codeword blocks in the first data stream is equal to a payload data volume included in n codeword blocks in the second data stream.
In some possible implementations, data in the first data stream is distributed by FEC symbol block, and data in a same FEC symbol block in the first data stream is encoded into a same codeword block in the second data stream.
In some possible implementations, data in the first data stream is distributed by bit stream, and data in the third data stream is encoded by bit stream.
In some possible implementations, the first chip and the second chip are located in a same data transmission device, the first chip is an electrical chip, and the second chip is a component that uses an Ethernet interface.
It may be understood that the apparatus 1300 shown in
In this embodiment, for the first data stream that is obtained through encoding by using the first FEC code type and that is sent by the second chip to the first chip, the first chip does not need to first decode the first data stream by using the first FEC code type and then re-encode original data into a concatenated FEC code. Instead, the first chip may re-encode the first data stream at least once by using at least the second FEC code type, to obtain the second data stream formed by concatenating at least the first FEC code type and the second FEC code type. Therefore, an FEC code type conversion process is simplified, both a delay and device power consumption that are required during FEC code type conversion are reduced, and data transmission efficiency is improved.
In some possible implementations, the first FEC code type is specifically: an RS code, a BCH code, an extended BCH (eBCH) code, a Hamming Code, or an extended Hamming Code, a staircase code, an LDPC code, a Turbo code, or a TPC.
In some possible implementations, the second FEC code type is specifically: a BCH code, an extended BCH (eBCH) code, a Hamming Code, or an extended Hamming Code, an RS code, a staircase code, an LDPC code, a Turbo code, or a TPC.
In some possible implementations, the first data stream is used to be decoded by the third chip based on the first FEC code type.
In some possible implementations, the second chip is located in a first data transmission device, the first chip and the third chip are located in a second data transmission device, the first chip is an electrical chip, the second chip is an electrical chip, and the third chip is a component that uses an Ethernet interface.
It may be understood that the apparatus 1400 shown in
In this embodiment, for the second data stream that is formed by concatenating at least the first FEC code type and the second FEC code type and that is sent by the first chip to the receiver 1401, the decoder 1402 may decode the second data stream by using an FEC code type other than the first FEC code type, to form the first data stream that is obtained through encoding by using the first FEC code type, and send the first data stream to the third chip. In this way, the chip 1 does not need to decode the second data stream into original data, then re-encode the original data into a data stream that is based on the first FEC code type, and send the data stream to the third chip. Therefore, an FEC code type conversion process is simplified, both a delay and device power consumption that are required during FEC code type conversion are reduced, and data transmission efficiency is improved.
In addition, an embodiment of this application further provides a communication method. The communication method includes the foregoing data transmission method 1100 and the foregoing data transmission method 1200.
In addition, an embodiment of this application further provides a communications system. The communications system includes the foregoing data transmission apparatus 1300 and the foregoing data transmission apparatus 1400.
In addition, an embodiment of this application further provides a network device. The network device includes the foregoing data transmission apparatus 1300 or 1400.
In addition, an embodiment of this application further provides a data transmission system. The data transmission system includes the foregoing network device.
In addition, an embodiment of this application further provides a computer program product including instructions. When the computer program product is run on a computer, the computer is enabled to perform the data transmission method 1100 or 1200 in the method embodiments of this application.
In addition, an embodiment of this application further provides a computer-readable storage medium. The computer-readable storage medium stores instructions; and when the instructions are run on a computer or a processor, the computer or the processor is enabled to perform the data transmission method 1100 or 1200 in the method embodiments in the embodiments of this application.
In a data transmission process, a data transmission rate and a data transmission distance are limited by a lane loss and noise. However, FEC provides error correction protection for data that is being transmitted, so that a transmission capability of a lane gradually approaches a Shannon limit. This can increase a rate and a distance of transmitting data on the lane. In this application, a multi-level FEC code concatenation manner is used to further increase a gain, so as to increase a data transmission rate and a data transmission distance. The Shannon limit refers to the maximum rate of error-free data that can theoretically be transferred over the channel if the link is subject to random data transmission errors, for a particular noise level. This is proved by Shannon theorem.
FEC is an error control manner, and a principle of FEC is to provide an additional parity bit for transmitted data by using a method. There are a plurality of types of FEC codes, such as a Reed-Solomon forward error correction (RS-FEC) code, a Bose-Chaudhuri-Hocquenghem (BCH) forward error correction (Bose-Chaudhuri-Hocquenghem FEC, BCH FEC) code, an extended BCH (eBCH) code, a Hamming Code, or an extended Hamming Code, a Fire code, a Turbo code, and a low density parity check (LDPC) code. These FEC codes can obtain different gains based on different code lengths and different overhead ratios.
In addition, there are different calculation methods for different FEC codes. In some FEC codes, original data is not changed and only a parity bit is added. Such an FEC code is called a systematic code (systematic FEC). For the systematic code, a parity code and original data are sent together on the lane to a receive end. When the parity code and the original data are transmitted on the lane, an error may occur in some locations in the original data or the parity code, and the original data that exists before the errors occur may be obtained at the receive end through reverse calculation.
FEC is widely applied to a data transmission technology because FEC can increase the data transmission rate and the data transmission distance. Ethernet interfaces are widely used data transmission interfaces worldwide. As a rate is rapidly increased, FEC plays an important role in the Ethernet. For example, for a 10 Gigabit Ethernet (GbE) interface, an FEC code is added, and the FEC code is a cyclic code, has a data length of 2080 bits, and has a parity bit of 32 bits. The FC Fire Code (2112, 2080) consists of 2080 information bits and 32 parity bits. The encoding can correct common errors occurring in backplane transmission. For example, a length of a code block of the Fire code includes 2080 bits of data and 32 bits of a parity code. Based on an error correction capability of the Fire code, common errors that the Fire code can correct are burst errors up to 11 bits at most. In a process of formulating the 100 GbE standard, a stronger FEC code such as RS-FEC is introduced in the industry. For example, KR4 FEC and KP4 FEC are both RS-FEC, and code types of the KR4 FEC and the KP4 FEC are respectively RS (528, 514) and RS (544, 514). The KR4 FEC and the KP4 FEC are both calculated based on a GF (210) field. Each symbol includes 10-bit data, and all calculation is performed based on symbols. Each codeword of the KP4 FEC includes 514 FEC symbols corresponding to original data information and 30 FEC symbols corresponding to a parity bit, that is, 5140-bit original data information and a 300-bit parity bit. Each codeword of the KR4 FEC includes 514 FEC symbols corresponding to original data information and 14 FEC symbols corresponding to a parity bit, that is, 5140-bit original data information and a 140-bit parity bit. An advantage of using an FEC symbol is that an error correction capability is strong for consecutive errors (also referred to as burst errors). For example, 20-bit consecutive errors do not extend to more than three symbols. For a decoder, the 20-bit consecutive errors are only three error symbols at most.
The KP4 FEC is used as an example. The KP4 FEC has a net gain (net coding gain, NCG) of about 6.5 dB when a post-correction bit error ratio Post-FEC BER=1×10-13. That is, when the FEC is used, if data reaches this bit error ratio (BER), a required signal-to-noise ratio (SNR) is lower than an SNR required when the FEC is not used. For example, it is generally considered in the industry that the required signal-to-noise ratio is about 6.5 dB lower than the SNR required when the FEC is not used. This greatly increases a distance over which a signal can be transmitted.
However, as a rate and a transmission distance are continuously increased, a requirement for FEC becomes increasingly high. On the other hand, stronger FEC often requires more parity bits, and consequently, data requires higher bandwidth. A serializer/deserializer (serializer/deserializer) rate is limited, and different designs may even have different frequency requirements. This also imposes limitations on selection of FEC. For example, on an interface of a transmission rate of 100 Gb/s, a rate of 103.125 G or 106.25 G is usually used in the industry.
For the KR4 FEC and the KP4 FEC that are mentioned above, RS (544, 514) is also used on a 400 GbE interface. A manner in which two codewords are interleaved for retransmission is used to cope with burst errors. In this manner, there is a relatively high probability that burst errors occurring on a link can be allocated to two FEC symbols, and then allocated to two codewords, to reduce a quantity of incorrect symbols in each codeword. This manner can enhance FEC performance and correct an error that cannot be corrected by using a single codeword. Interleaving is particularly effective for a lane on which burst errors occur. However, when an Ethernet interface is connected to an optical module, a design of the optical module needs to be considered. Therefore, no complicated data processing is required on the optical module side.
In view of this, an embodiment of this application provides a data encoding method. The method may be applied to a current Ethernet interface and an Ethernet interface that may emerge in the future. For example, the Ethernet interfaces to which this application is applied include an electrical interface or an optical interface of a rate such as 10GBASE-T, 100GBASE-LR4, or 200GBASE-SR4, further include an attachment unit interface (AUI), and also include an interface of a rate such as 100GBASE-CR1 or 400GBASE-KR4. In addition, the method provided in this embodiment of this application is applicable to either a single-segment lane or a multi-segment lane. A difference between a single-segment lane and a multi-segment lane lies in whether data passes through an active circuit or data is propagated all through mediums in an entire data transmission process. If the data is transmitted from a transmit end to a receive end all through passive mediums, such as a PCB circuit board and an optical fiber, the lane is considered as a single-segment lane. If the data is transmitted from a transmit end to a receive end through another circuit, a photoelectric conversion apparatus, or the like, the another circuit, the photoelectric conversion apparatus, or the like is used as a demarcation point to divide the lane into a plurality of lane segments. Different lanes may have different lane features, including burst error behavior.
Refer to
The second circuit obtains RS original data received from a media access control (MAC) layer, and transmits the RS original data to a physical coding sublayer (PCS) through a media independent interface (MII). After encoding and rate matching is performed on the original data at the PCS, 256B (bits)/257B transcoding is performed on the original data. After the transcoding, scrambling and alignment symbol insertion are sequentially performed on transcoded data. The alignment symbol insertion is to insert an alignment marker (AM) into scrambled data, and perform alignment by using the AM. AMs of different virtual lanes may be different, so that data on different virtual lanes can be distinguished based on the AMs. During subsequent encoding, a boundary of an FEC codeword or a boundary of an FEC symbol may be determined through AM alignment. After alignment, data distribution is performed before FEC encoding, to distribute data to a corresponding RS encoder. The second circuit includes one or more RS encoders. The 400 GbE interface is used as an example. After FEC encoding is performed on the RS original data received by the MAC layer of the second circuit, two RS (544, 514) codewords, for example, an FEC-CW1 and an FEC-CW2 in
Further, after the two RS codewords are interleaved, interleaved data is distributed to a virtual lane (which is referred to as a PCS lane in the standard, or may be referred to as a logical lane). 16 virtual lanes are used as an example. A 16×25 G output mode, an 8×50 G output mode, or a 4×100 G output mode is supported. The interleaved data is transmitted to a physical medium attachment sublayer (PMA) through the virtual lane, and the PMA performs bit multiplexing, so that data transmitted on a plurality of virtual lanes is multiplexed onto one or more physical lanes.
After multiplexing from the virtual lane to the physical lane is performed, the second circuit transmits a first data stream to the first circuit through the physical lane, that is, transmits the first data stream to the first circuit through the Ethernet interface. The first data stream is RS-encoded data. After receiving the first data stream, the first circuit may perform BCH encoding on the first data stream by using a BCH encoder, to obtain a second data stream. Then, the second data stream is distributed to a logic lane, and is transmitted to a medium through the PMA and a physical media dependent (PMD) layer. The medium transmits the second data stream to another receive end, for example, a third circuit. The medium includes but is not limited to an optical fiber, a backplane, a copper cable, or the like.
In the implementation environment shown in
In an optional implementation environment, in a case in which the second circuit transmits the first data stream to the first circuit through a plurality of physical lanes, a skew exists in data between the plurality of physical lanes. For example, when the first data stream arrives at the first circuit from the second circuit through a circuit board or a cable, times at which simultaneously sent data arrives at the first circuit on all physical lanes are different. Therefore, in the method provided in this embodiment of this application, before BCH encoding is performed on the first data stream, the data is first re-aligned. In this case, the implementation environment may be shown in
Regardless of the implementation environment shown in
Step 1701: The second circuit obtains original data, encodes the original data by using an RS code, and obtains a first data stream based on an encoded RS codeword.
As described in the description of the implementation environment shown in
Step 1702: The second circuit transmits the first data stream to the first circuit through an Ethernet interface.
As described in the description of the implementation environment shown in
Step 1703: The first circuit receives the first data stream transmitted by the second circuit through the Ethernet interface.
Based on the foregoing manner in which the second circuit transmits the first data stream, in a possible implementation, that the first circuit receives the first data stream transmitted by the second circuit through the Ethernet interface includes: The first circuit receives, from a plurality of physical lanes, the first data stream transmitted by the second circuit through the Ethernet interface.
Step 1704: The first circuit performs BCH encoding on the first data stream, to obtain a second data stream.
After receiving the first data stream, the first circuit may perform FEC encoding on the first data stream again, for example, perform BCH encoding, to increase a gain by using a concatenated coding scheme. In a possible implementation, the first circuit includes one or more BCH encoders, and the first circuit receives the first data stream through one or more physical lanes. A quantity of BCH encoders is consistent with a quantity of physical lanes. After the first circuit receives the first data stream, each physical lane sends, to a BCH encoder connected to the physical lane, the first data stream transmitted on the physical lane; and the BCH encoder performs BCH encoding.
A data transmission implementation environment shown in
A light FEC encoder, such as a BCH encoder, is added to the optical module to implement concatenated coding, and a further gain can be obtained in a concatenated manner, so that a data transmission distance can be further increased or a single-wavelength rate can be higher. The light FEC encoder, that is, the BCH encoder, may use a BCH (360, 340) encoding scheme. Certainly, another type of BCH encoder may alternatively be used. This is not limited in this embodiment of this application.
In addition to a case in which the quantity of BCH encoders is consistent with the quantity of physical lanes, there is a case in which the quantity of BCH encoders included in the first circuit is less than the quantity of physical lanes. In this case, that the first circuit performs BCH encoding on the first data stream, to obtain a second data stream includes: The first circuit performs BCH encoding on the first data stream by using one or more BCH encoders in a time division multiplexing mode, to obtain the second data stream. Because the quantity of BCH encoders included in the first circuit is less than the quantity of physical lanes, one or more BCH encoders are multiplexed in a time division multiplexing mode, to implement BCH encoding on all of the first data stream.
In a possible implementation, when the quantity of BCH encoders included in the first circuit is inconsistent with the quantity of physical lanes, the first circuit further includes a scheduler, and that the first circuit performs BCH encoding on the first data stream, to obtain a second data stream includes: The first circuit schedules, by using the scheduler, a corresponding BCH encoder to perform BCH encoding on the first data stream, to obtain the second data stream. Because the quantity of BCH encoders is greater than or less than the quantity of physical lanes, a BCH encoder for encoding may be selected through scheduling by using the scheduler from a plurality of BCH encoders. In other words, the scheduler is configured to connect a physical lane to a corresponding BCH encoder, and the BCH encoder performs BCH encoding on the first data stream. In this case, the first circuit may further include a buffer. The first data stream transmitted on the physical lane is first stored in the buffer, and then the corresponding BCH encoder is scheduled by using the scheduler to perform BCH encoding.
A data transmission implementation environment shown in
Further, regardless of a structure shown in
It should be understood that if the first data stream is transmitted through only one physical lane, there is no data skew. Therefore, BCH encoding is directly performed on the first data stream without a need to identify a codeword boundary or a symbol boundary and change any existing or future manner of outputting data through an Ethernet interface. In addition to the foregoing examples shown in
However, in the case in which the first data stream is carried by a plurality of physical lanes, skew between the lanes may cause the data blocks of the first data stream sent at the same time to arrive with different delays, so deskew of the data may be needed before encoding the first data stream. In a possible implementation, after the data in the first data stream is interleaved based on the reference quantity of RS codewords, to obtain symbol stream data, the symbol stream data is output to a plurality of virtual lanes, the symbol stream data is bit-multiplexed based on the quantity of physical lanes, and bit-multiplexed symbol stream data is transmitted to the first circuit through the plurality of physical lanes; before the filling data in the first data stream into a corresponding BCH codeword, the method further includes: The first circuit demultiplexes the first data stream, to restore data on all virtual lanes, and aligns the data on all the virtual lanes, to obtain aligned data; and the filling data in the first data stream into a corresponding BCH codeword includes: filling the aligned data into the corresponding BCH codeword.
Regardless of whether an alignment operation needs to be performed, manners of filling data in the first data stream into the corresponding BCH codeword include but are not limited to the following three manners.
Manner 1: For example, the first data stream includes a first quantity of RS codewords, each RS codeword includes a first target quantity of symbols, and the data in the first data stream is interleaved based on the first quantity of RS codewords; and each BCH encoder corresponds to a second quantity of BCH codewords, each BCH codeword includes a second target quantity of symbols, the second target quantity is determined based on the first target quantity, and the second quantity is determined based on the first quantity. The filling data in the first data stream into a corresponding BCH codeword includes: sequentially filling the first half of data in each row of the first data stream into the first third quantity of BCH codewords in the second quantity of BCH codewords, and sequentially filling the second half of data in each row of the first data stream into the last third quantity of BCH codewords in the second quantity of BCH codewords, where the third quantity is half of the second quantity, and a first quantity of consecutive symbols included in each BCH codeword are from different RS codewords. The first quantity may be determined based on an RS code type, or determined based on an application scenario or experience. This is not limited in this embodiment of this application.
For example, the first target quantity is 544, the first quantity is 2, the second quantity is 32, and the second target quantity is 360. The filling data in the first data stream into a corresponding BCH codeword includes: sequentially filling the first half of data in each row of the first data stream into the first 16 BCH codewords in 32 BCH codewords, and sequentially filling the second half of data in each row of the first data stream into the last 16 BCH codewords in the 32 BCH codewords, where two consecutive symbols included in each BCH codeword are from different RS codewords.
A BCH encoding process shown in
Manner 2: For example, the first data stream includes a first quantity of RS codewords, each RS codeword includes a first target quantity of symbols, the data in the first data stream is interleaved based on the first quantity of RS codewords, and symbols at the beginning or the end of each column of data in the first data stream are permuted; and each BCH encoder corresponds to a second quantity of BCH codewords, each BCH codeword includes a second target quantity of symbols, the second target quantity is determined based on the first target quantity, and the second quantity is determined based on the first quantity. The filling data in the first data stream into a corresponding BCH codeword includes: sequentially filling each column of data of the first data stream into the second quantity of BCH codewords, where a first quantity of consecutive symbols included in each BCH codeword are from different RS codewords.
For example, the first target quantity is 544, the first quantity is 2, the second quantity is 32, and the second target quantity is 360. The filling data in the first data stream into a corresponding BCH codeword includes: sequentially filling each column of data of the first data stream into 32 BCH codewords, where two consecutive symbols included in each BCH codeword are from different RS codewords.
A BCH encoding process shown in
It should be noted that Manner 1 and Manner 2 are merely used as examples to implement that two consecutive symbols included in each BCH codeword are from different RS codewords. In addition, another manner may alternatively be used to implement that two consecutive symbols included in each BCH codeword are from different RS codewords, that is, a case in which two consecutive symbols are from a same RS codeword does not exist. This is not limited in this embodiment of this application.
In addition, both Manner 1 and Manner 2 are used to implement BCH encoding when the first circuit does not modify an interleaving manner after the data in the first data stream is interleaved. Then, to increase an interleaving depth, in the method provided in this embodiment of this application, the first circuit may further re-interleave the data in the first data stream after receiving the first data stream. For details of a BCH encoding method in this manner, refer to Manner 3 in the following.
Manner 3: The first data stream includes a first quantity of RS codewords, each RS codeword includes a first target quantity of symbols, and the data in the first data stream is interleaved based on the first quantity of RS codewords; and each BCH encoder corresponds to a second quantity of BCH codewords, each BCH codeword includes a second target quantity of symbols, the second target quantity is determined based on the first target quantity, and the second quantity is determined based on the first quantity. The filling data in the first data stream into a corresponding BCH codeword includes: de-interleaving the data in the first data stream, to obtain original RS codewords; interleaving the original RS codewords based on a fourth quantity of RS codewords, to obtain interleaved data, where the fourth quantity is greater than the first quantity; and sequentially filling each row of data of the interleaved data into the second quantity of BCH codewords, where a fourth quantity of consecutive symbols included in each BCH codeword are from different RS codewords.
Because the data in the first data stream has been interleaved, according to the method provided in this embodiment of this application, after the first data stream is obtained, the data in the first data stream is first de-interleaved, to obtain the original RS codewords. Then, re-interleaving is performed. More codewords are used for interleaving. This increases the interleaving depth. Then, each row of data of re-interleaved data is sequentially filled into the second quantity of BCH codewords. In this manner, the fourth quantity may be determined based on an RS code type, or determined based on an application scenario or experience. This is not limited in this embodiment of this application. Because a re-interleaving depth is greater than the previous interleaving depth in the first data stream, the fourth quantity is greater than the first quantity. In addition, the first circuit may be disposed with a buffer, so as to perform interleaving after the first circuit receives a fourth quantity of codewords.
For example, the first target quantity is 544, the first quantity is 2, the fourth quantity is 4, and the second target quantity is 360. The first circuit further de-interleaves the first data stream, to restore original RS-FEC codewords. In this way, more RS-FEC codewords can be accumulated for stronger interleaving, for example, four codewords are used for interleaving. When receiving the first data stream, the first circuit buffers the first data stream, and performs interleaving after receiving all four codewords. BCH encoding processes shown in
It should be noted that, in the foregoing three implementations of filling data in the first data stream into a corresponding BCH codeword, the first target quantity may be determined based on an RS code type. For example, for RS (544, 514), the first target quantity is 544, and each RS codeword includes 544 symbols. The second target quantity may be determined based on the first target quantity. For RS (544, 514), BCH (360, 340) may be used, and the second target quantity is 360. For another example, for RS (528, 514), the first target quantity is 528, and each RS codeword includes 528 symbols. In addition, in the method provided in this embodiment of this application, two-level coding based on RS code and BCH code is used. A specific RS code type and a specific BCH code type are not limited in this embodiment of this application. In other words, for different code types, the first target quantity and the second target quantity may alternatively have other values. In addition, the first target quantity of symbols and the second target quantity of symbols may be 10-bit symbols, or may be 1-bit symbols or symbols having another length. A length of a symbol is not limited in this embodiment of this application.
In addition, no matter which manner is used to fill the data in the first data stream into the corresponding BCH codeword, for a BCH encoding scheme, a polynomial p(x)=x10+x3+x+1 may be used. In other words, the BCH encoder may perform encoding according to the polynomial p(x)=x10+x3+x+1, to obtain the second data stream. Certainly, in addition to the polynomial P(x), another polynomial used for BCH encoding may alternatively be used. This is not limited in this application.
In a possible implementation, after the first circuit performs BCH encoding on the first data stream, to obtain the second data stream, the method further includes: transmitting the second data stream to the third circuit by using a medium through the plurality of physical lanes, or transmitting the second data stream to the third circuit by using the medium through one physical lane in a time division multiplexing mode. The medium includes but is not limited to an optical fiber, a backplane, or a copper cable. A 100 GbE Ethernet port is used as an example. Data may be sent in a manner that one wavelength carries a rate of 100 Gbps, and is transmitted through an optical fiber. Alternatively, one electrical port transmits a signal at a rate of 100 Gbps through a backplane or a copper cable. Alternatively, an 800 GbE port that may emerge in the future is used as an example. There may be various solutions such as 8×100 G and 4×200 G, and transmission may be performed through an optical fiber, a backplane, or a copper cable.
Refer to
Block 2401: The third circuit receives second data streams transmitted by a first circuit, where the second data streams are obtained through encoding by using an RS code and a BCH code.
In a possible implementation, that the third circuit receives second data streams transmitted by a first circuit includes: receiving, by using a medium, the second data streams transmitted by the first circuit through a plurality of physical lanes, or receiving, by using the medium, the second data streams transmitted by the first circuit through one physical lane in a time division multiplexing mode. The medium includes but is not limited to an optical fiber, a backplane, or a copper cable. Because the first circuit uses the encoding method shown in
Block 2402: The third circuit decodes the second data streams by using the BCH code, to obtain the first data stream.
The BCH code used by the third circuit to decode the second data streams is consistent with a code type used by the first circuit to perform BCH encoding on the first data stream, so as to ensure that the third circuit can successfully decode the second data streams to obtain the first data stream.
The first circuit may transmit the second data streams through one physical lane in a time division multiplexing mode, or through a plurality of physical lanes. Therefore, in a possible implementation, before the decoding the second data streams by using the BCH code, to obtain a first data stream, the method further includes: demultiplexing the second data streams when the second data streams transmitted by the first circuit through one physical lane in a time division multiplexing mode are received by using the medium; and the decoding the second data streams by using the BCH code, to obtain a first data stream includes: decoding demultiplexed data streams by using the BCH code, to obtain the first data stream.
For a manner in which the second data streams are transmitted through a plurality of physical lanes, to avoid a skew when data in the second data streams reaches the third circuit, in a possible implementation, before the decoding the second data streams by using the BCH code, the method further includes: aligning the demultiplexed second data streams; and the decoding demultiplexed second data streams by using the BCH code, to obtain the first data stream includes: decoding aligned second data streams by using the BCH code, to obtain the first data stream. Because an AM character is not changed during BCH encoding, when the demultiplexed second data streams are to be aligned, an existing AM character in the second data streams may be reused to align the demultiplexed second data streams.
Block 2403: The third circuit decodes the first data stream by using the RS code, to obtain original data.
The RS code used by the third circuit to decode the first data stream is consistent with an RS code type used for encoding data in the first data stream, so as to ensure that the third circuit can successfully decode the first data stream to obtain the original data.
Based on the foregoing data encoding method and data decoding method, in this embodiment of this application, modeling is performed to verify the solution on a field programmable gate array (FPGA). As shown in
According to the foregoing interleaving process, a gain is increased. As shown in a comparison diagram in
Refer to
In a possible implementation, the receiving module 271 is configured to receive, from a plurality of physical lanes, the first data stream transmitted by the second circuit through the Ethernet interface; and the apparatus includes one or more BCH encoders, and the encoding module 272 is configured to: when a quantity of included BCH encoders is consistent with a quantity of physical lanes, where one BCH encoder is corresponds to one physical lane, perform, by using the one or more BCH encoders, BCH encoding on the first data stream transmitted on a corresponding physical lane, to obtain the second data stream.
In a possible implementation, the receiving module 271 is configured to receive, from a plurality of physical lanes, the first data stream transmitted by the second circuit through the Ethernet interface; and the apparatus includes one or more BCH encoders and further includes a scheduler, and the encoding module 272 is configured to: when a quantity of BCH encoders included in the apparatus is inconsistent with a quantity of physical lanes, schedule, by using the scheduler, a corresponding BCH encoder to perform BCH encoding on the first data stream, to obtain the second data stream.
In a possible implementation, the encoding module 272 is configured to fill data in the first data stream into a corresponding BCH codeword, where a reference quantity of consecutive symbols included in each BCH codeword are from different RS codewords.
In a possible implementation, after the data in the first data stream is interleaved based on the reference quantity of RS codewords, to obtain symbol stream data, the symbol stream data is output to a plurality of virtual lanes, the symbol stream data is bit-multiplexed based on the quantity of physical lanes, and bit-multiplexed symbol stream data is transmitted to the data encoding apparatus through the plurality of physical lanes;
Refer to
In a possible implementation, the first data stream includes a first quantity of RS codewords, each RS codeword includes a first target quantity of symbols, and the data in the first data stream is interleaved based on the first quantity of RS codewords. Each BCH encoder corresponds to a second quantity of BCH codewords, each BCH codeword includes a second target quantity of symbols, the second target quantity is determined based on the first target quantity, and the second quantity is determined based on the first quantity.
The encoding module 272 is configured to: sequentially fill the first half of data in each row of the first data stream into the first third quantity of BCH codewords in the second quantity of BCH codewords, and sequentially fill the second half of data in each row of the first data stream into the last third quantity of BCH codewords in the second quantity of BCH codewords, where the third quantity is half of the second quantity, and a first quantity of consecutive symbols included in each BCH codeword are from different RS codewords.
In a possible implementation, the first target quantity is 544, the first quantity is 2, the second quantity is 32, and the second target quantity is 360.
The encoding module 272 is configured to: sequentially fill the first half of data in each row of the first data stream into the first 16 BCH codewords in 32 BCH codewords, and sequentially fill the second half of data in each row of the first data stream into the last 16 BCH codewords in the 32 BCH codewords, where two consecutive symbols included in each BCH codeword are from different RS codewords.
In a possible implementation, the first data stream includes a first quantity of RS codewords, each RS codeword includes a first target quantity of symbols, the data in the first data stream is interleaved based on the first quantity of RS codewords, and symbols at the beginning or the end of each column of data in the first data stream are permuted. Each BCH encoder corresponds to a second quantity of BCH codewords, each BCH codeword includes a second target quantity of symbols, the second target quantity is determined based on the first target quantity, and the second quantity is determined based on the first quantity.
The encoding module 272 is configured to sequentially fill each column of data of the first data stream into the second quantity of BCH codewords, where a first quantity of consecutive symbols included in each BCH codeword are from different RS codewords.
In a possible implementation, the first target quantity is 544, the first quantity is 2, the second quantity is 32, and the second target quantity is 360.
The encoding module 272 is configured to sequentially fill each column of data of the first data stream into 32 BCH codewords, where two consecutive symbols included in each BCH codeword are from different RS codewords.
In a possible implementation, the first data stream includes a first quantity of RS codewords, each RS codeword includes a first target quantity of symbols, and the data in the first data stream is interleaved based on the first quantity of RS codewords. Each BCH encoder corresponds to a second quantity of BCH codewords, each BCH codeword includes a second target quantity of symbols, the second target quantity is determined based on the first target quantity, and the second quantity is determined based on the first quantity.
The encoding module 272 is configured to: de-interleave the data in the first data stream, to obtain original RS codewords; interleave the original RS codewords based on a fourth quantity of RS codewords, to obtain interleaved data, where the fourth quantity is greater than the first quantity; and sequentially fill each row of data of the interleaved data into the second quantity of BCH codewords, where a fourth quantity of consecutive symbols included in each BCH codeword are from different RS codewords.
Refer to
Refer to
In a possible implementation, the receiving module 161 is configured to: receive, by using a medium, the second data streams transmitted by the first circuit through a plurality of physical lanes, or receive, by using the medium, the second data streams transmitted by the first circuit through one physical lane in a time division multiplexing mode.
In a possible implementation, as shown in
In a possible implementation, as shown in
It should be understood that, when the apparatus provided in the foregoing implements functions of the apparatus, division into the foregoing functional modules is merely used as an example for description. During actual application, the foregoing functions may be allocated to different functional modules for implementation based on a requirement. In other words, a device is divided into different functional modules in terms of an inner structure, to implement all or a part of the functions described above. In addition, the apparatus in the foregoing embodiments and the method embodiments are based on a same concept. For a specific implementation process, refer to the method embodiments, and details are not described herein again.
It should be noted that the first circuit, the second circuit, the third circuit, the data encoding apparatus, and the data decoding apparatus may be implemented in one or more chips.
Based on a same concept, an embodiment of this application further provides a data transmission device. Refer to
An embodiment of this application further provides a data transmission device. Refer to
An embodiment of this application further provides a data transmission system. The system includes the data encoding apparatus shown in any one of
The data encoding apparatus and the data decoding apparatus in this embodiment of this application may be personal computers (PCs), servers, or network devices. For example, the data encoding device and the data decoding device may be routers, switches, servers, or the like.
An embodiment of this application further provides a computer-readable storage medium. The storage medium stores at least one instruction, and the instruction is loaded and executed by a processor, to implement either of the foregoing data encoding method and data decoding method provided in the embodiments of this application.
An embodiment of this application further provides a circuit. The circuit includes a processor. The processor is configured to invoke and run instructions stored in a memory, so that a communications device that is installed with the circuit performs either of the foregoing data encoding method and data decoding method.
An embodiment of this application further provides a circuit. The circuit includes an input interface, an output interface, a processor, and a memory. The input interface, the output interface, the processor, and the memory are connected to each other through an internal connection path. The processor is configured to execute code in the memory, and when the code is executed, the processor is configured to perform either of the foregoing data encoding method and data decoding method.
It should be understood that the processor may be a central processing unit (CPU), or may be another general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA) or another programmable logic device, a discrete gate or transistor logic device, or a discrete hardware component, or the like. The general-purpose processor may be a microprocessor, any conventional processor, or the like. It should be noted that the processor may be a processor that supports an advanced reduced instruction set computing machines (advanced RISC machines, ARM) architecture.
Further, in an optional embodiment, there are one or more processors, and there are one or more memories. Optionally, the memory may be integrated with the processor, or the memory and the processor are separately disposed. The memory may include a read-only memory and a random access memory, and provide instructions and data to the processor. The memory may further include a nonvolatile random access memory. For example, the memory may further store information about a device type.
In some embodiments, in the case where the first level FEC is RS and the second level FEC is BCH code, the BCH code may be replaced with an extended BCH (eBCH) code, a Hamming Code, or an extended Hamming Code; accordingly, the BCH encoder can replaced with an extended eBCH code encoder, a Hamming Code encoder, or an extended Hamming Code encoder.
The memory may be a volatile memory or a nonvolatile memory, or may include both a volatile memory and a nonvolatile memory. The nonvolatile memory may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The volatile memory may be a random access memory (RAM) and is used as an external cache. For example but not limitation, many forms of RAMs are available, for example, a static random access memory (SRAM), a dynamic random access memory (DRAM), a synchronous dynamic random access memory (SDRAM), a double data rate synchronous dynamic random access memory (DDR SDRAM), an enhanced synchronous dynamic random access memory (ESDRAM), a synchlink dynamic random access memory (SLDRAM), and a direct rambus random access memory (DR RAM).
This application provides a computer program. When the computer program is executed by a computer, a processor or the computer is enabled to perform corresponding steps and/or procedures in the foregoing method embodiments.
All or a part of the foregoing embodiments may be implemented by using software, hardware, firmware, or any combination thereof. When the software is used to implement the embodiments, all or a part of the embodiments may be implemented in a form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on the computer, the procedures or functions according to this application are all or partially generated. The computer may be a general-purpose computer, a dedicated computer, a computer network, or another programmable apparatus. The computer instructions may be stored in a computer-readable storage medium or may be transmitted from a computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions may be transmitted from a website, computer, server, or data center to another web site, computer, server, or data center in a wired (for example, a coaxial cable, an optical fiber, or a digital subscriber line) or wireless (for example, infrared, radio, or microwave) manner. The computer-readable storage medium may be any usable medium accessible by the computer, or a data storage device, for example, a server or a data center, integrating one or more usable mediums. The usable medium may be a magnetic medium (for example, a floppy disk, a hard disk, or a magnetic tape), an optical medium (for example, a DVD), a semiconductor medium (for example, a solid-state drive), or the like.
Ordinal numbers such as “1”, “2”, “3”, “first”, “second”, and “third” in the embodiments of this application are used to distinguish between a plurality of objects, but are not used to limit a sequence of the plurality of objects.
It can be learned from the foregoing descriptions of the implementations that, a person skilled in the art may clearly understand that a part or all of the steps of the methods in the foregoing embodiments may be implemented by using software and a universal hardware platform. Based on such an understanding, the technical solutions of this application may be implemented in a form of a software product. The computer software product may be stored in a storage medium, for example, a read-only memory (ROM)/RAM, a magnetic disk, or an optical disc, and include several instructions for instructing a computer device (which may be a personal computer, a server, or a network communications device such as a router) to perform the methods described in the embodiments or some parts of the embodiments of this application.
The embodiments in this specification are all described in a progressive manner, for same or similar parts in the embodiments, refer to these embodiments, and each embodiment focuses on a difference from other embodiments. Especially, the apparatus embodiment is basically similar to the method embodiment, and therefore is described briefly. For related parts, refer to the description part of the method embodiment. The described device and system embodiments are merely examples. The modules described as separate parts may or may not be physically separate, and parts displayed as modules may or may not be physical modules, may be located in one position, or may be distributed on a plurality of network units. A part or all of the modules may be selected based on an actual requirement to achieve the objectives of the solutions of the embodiments. A person of ordinary skill in the art may understand and implement the embodiments without creative efforts.
The foregoing descriptions are merely the embodiments of this application, but are not intended to limit this application. Any modification, equivalent replacement, or improvement made without departing from the spirit and principle of this application shall fall within the protection scope of this application.
This application is a continuation of International Application No. PCT/CN2019/096055, filed on Jul. 15, 2019, which claims priority to International Application No. PCT/CN2019/087058, filed on May 15, 2019. The disclosures of the aforementioned applications are hereby incorporated by reference in their entireties.
| Number | Date | Country | |
|---|---|---|---|
| Parent | PCT/CN2019/096055 | Jul 2019 | US |
| Child | 17525189 | US |
