This Application claims priority of Taiwan Patent Application No. 99112467, filed on Apr. 21, 2010, the entirety of which is incorporated by reference herein.
1. Field of the Invention
The invention relates to memories, and more particularly to flash memories.
2. Description of the Related Art
A flash memory comprises a plurality of blocks. Each block comprises a plurality of pages for data storage. Each block also maps to a unique address. When a host wants to access data stored in the flash memory, the host sends an access command to a controller of the flash memory, wherein the access command comprises an address of the block storing the data to be accessed. The controller then accesses data from the flash memory according to the address. For example, when the flash memory receives a write command from the controller, the flash memory writes data to the block corresponding to the address. When the flash memory receives a read command from the controller, the flash memory reads data from the block corresponding to the address and sends the read data back to the controller.
After data is written to all pages of a block of a flash memory, other data cannot be written to the block again. A plurality of blocks of a flash memory is therefore divided into data blocks of a data area and spare blocks of a spare area. Data blocks of the data area have stored data, and spare blocks of the spare area have no stored data. When the host wants to write data into a write address corresponding to a data block of the data area, because update data cannot be written to the data block again, the controller obtains a spare block from the spare area, changes the address of the spare block to the write address, and then writes the update data to the spare block. Because the data block originally mapped to the write address is useless, the controller erases data from the data block to convert the data block to a spare block.
Ordinarily, when a controller selects a spare block from the spare area, a first-in first-out (FIFO) method is used to select the spare block. In other words, the controller selects a spare block with the earliest erase time index in comparison with those of other spare blocks from the spare area. Referring to
Referring to
The conventional data writing method 200 shown in
The invention provides a data writing method for a memory. In one embodiment, the memory comprises a data area and a spare area, the data area comprises a plurality of data blocks storing data, and the spare area comprises a plurality of spare blocks having no data stored therein. First, a write command for writing a write data to a first data block of the memory is received from a host. The spare blocks of the spare area are then sorted according to the erase counts of the spare blocks. A first spare block with the least erase counts is then selected from the spare blocks of the spare area. The write data is then written to the first spare block. Data is then erased from the first data block to convert the first data block to a spare block.
The invention also provides a data storage device. In one embodiment, the data storage device comprises a memory and a controller. The memory comprises a data area and a spare area, wherein the data area comprises a plurality of data blocks storing data, and the spare area comprises a plurality of spare blocks having no data stored therein. The controller receives a write command for writing a write data to a first data block of the memory from a host, sorts the spare blocks of the spare area according to the erase counts of the spare blocks, selects a first spare block with the least erase counts from the spare blocks of the spare area, writes the write data to the first spare block, and erases data from the first data block to convert the first data block to a spare block.
A detailed description is given in the following embodiments with reference to the accompanying drawings.
The invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein:
The following description is of the best-contemplated mode of carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims.
Referring to
When the controller 402 receives a write command from the host 406, the controller 402 searches the memory 404 for a block corresponding to the address comprised by the write command. If the block corresponding to the address is a data block of the data area 410, because the data block has stored data, the controller 402 cannot write update data to the data block. The controller 402 then obtains a target spare block from the spare area 420 for storing the update data in place of the data block. When the controller selects a spare block as the target spare block, the controller first sorts all of the spare blocks in the spare area 420, and then selects the spare block with the least erase counts in comparison with those of other spare blocks in the spare area 420 as the target spare block. Thus, whenever the controller 402 executes a write command for writing update data to a data block, the controller 402 always selects a spare block with the least erase counts from the spare area 420 as a target spare block for storing the update data in place of the data block. The controller 402 therefore avoids the use of a spare block with a higher erase count for holding update data of a data block, thereby lowering the risk of increasing a total number of the worn-out blocks. Thus, lifespan of the memory 404 of the data storage device 408 is lengthened, and the performance of the data storage device 408 is improved.
Referring to
Referring to
Assume that the controller 402 further receives a write command for writing second update data to the data block 41P of the data area 410. Because the second update data cannot be written to the data block 41P which has stored data, the controller 402 sorts the spare blocks of the spare area 420 according to the erase counts of the spare blocks, and selects a spare block 425 with the least amount of erase counts 9 from the spare area 420 to hold the second update data in place of the data block 41P. The controller 402 then writes the second update data to the target spare block 425. After the spare block 425 stores the second update data, the spare block 425 is moved to the data area 410, as shown in
The wear-leveling process of the method 500 is illustrated in the following. At step 506, the controller 402 calculates a total number of worn-out blocks in the spare area 420, and determines whether the total number of the worn-out blocks is greater than the specific number. If the total number of the worn-out blocks is greater than the specific number, the controller 402 searches the data area 410 for at least one data block with a low erase count to replace at least one spare block with a high erase count in the spare area 420. In one embodiment, the specific number is a natural number greater than 2. If the total number of the worn-out blocks is greater than the specific number (step 506), the controller 402 searches the spare area 420 for a second spare block with the largest erase count (step 514). The controller 402 then searches the data area 410 for a second data block with an erase count less than a second threshold (step 516). In one embodiment, the second threshold is lower than half of the first threshold. The controller 402 then writes the data of the second data block to the second spare block (step 518), sets the address of the second spare block to the logical address of the second data block, and then moves the second spare block to the data area 410. The second data block is now replaced by the second spare block. The controller 402 then erases data from the second data block to convert the second data block to a spare block (step 520). The description of the wear-leveling process comprising steps 514˜520 is now completed.
Referring to
The controller 402 first selects a spare block 724 with the largest erase count 32 from the spare area 720 for replacement with data blocks of the data area 710. The controller 402 then searches a data block 713 with an erase count 12 lower than a second threshold 15 for replacement with the spare block 724. The controller 402 then writes the data of the data block 713 to the spare block 724, sets the address of the spare block 724 to the logical address of the data block 713, and moves the spare block 724 to the data area 710, as shown in
When the controller 402 performs the wear-leveling process at step 518, if the erase counts of all data blocks of the data area 410 are greater than the second threshold, the controller 402 can not find a data block with an erase count less than the second threshold in the data area 410. The controller 402 then subtracts a value from the erase counts of all data blocks of the data area 410, thereby decreasing the erase counts of all data blocks of the data area 410. In one embodiment, the value is equal to half of the first threshold or the second threshold. When the erase counts of the data blocks of the data area 710 are decreased, the controller 402 can then search the data area 410 for data blocks with erase counts less than the second threshold again to perform the wear-leveling process.
While the invention has been described by way of example and in terms of preferred embodiment, it is to be understood that the invention is not limited thereto. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.
Number | Date | Country | Kind |
---|---|---|---|
99112467 A | Apr 2010 | TW | national |
Number | Name | Date | Kind |
---|---|---|---|
7984231 | Maeda et al. | Jul 2011 | B2 |
8117382 | Yeh et al. | Feb 2012 | B2 |
8606987 | Yang et al. | Dec 2013 | B2 |
20030227804 | Lofgren et al. | Dec 2003 | A1 |
20080177927 | Hsiao et al. | Jul 2008 | A1 |
20090089485 | Yeh | Apr 2009 | A1 |
20090106484 | Yeh et al. | Apr 2009 | A1 |
20090122949 | Reid et al. | May 2009 | A1 |
20090164702 | Kern | Jun 2009 | A1 |
20090172255 | Yeh et al. | Jul 2009 | A1 |
20090198875 | Chu et al. | Aug 2009 | A1 |
20090265505 | Yang et al. | Oct 2009 | A1 |
20100017555 | Chang et al. | Jan 2010 | A1 |
20100023675 | Chen et al. | Jan 2010 | A1 |
20100077132 | Hung | Mar 2010 | A1 |
20100115194 | Suzuki | May 2010 | A1 |
Number | Date | Country |
---|---|---|
200919474 | May 2009 | TW |
200926183 | Jun 2009 | TW |
200926196 | Jun 2009 | TW |
Entry |
---|
Zertal, S., Harrison, P.G. Investigating Flash Memory Wear Levelling and Execution Codes. Jul. 13-16, 2009. Performance Evaluation of Computer & Telecommunication Systems, 2009. SPECTS 2009. International Symposium on (vol. 41). pp. 81-88. |
Chang, L., Du, C. Design and Implementation of an Efficient Wear-Leveling Algorithm for Solid-State-Disk Microcontrollers. Dec. 2009. ACM Transactions on Design Automation of Electronic Systems (TODAES) TODAES Homepage archive vol. 15 Issue 1, Dec. 2009 Article No. 6. |
English language translation of abstract of TW 200919474 (published May 1, 2009). |
English language translation of abstract of TW 200926183 (published Jun. 16, 2009). |
English language translation of abstract of TW 200926196 (published Jun. 16, 2009). |
Number | Date | Country | |
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20110264847 A1 | Oct 2011 | US |