Patent Application
20240289029
This application claims the priority benefit of Chinese application no. 202310184408.8, filed on Feb. 24, 2023. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification.
The disclosure relates to a memory management technology. In particular, the disclosure relates to a data writing method, a memory storage device, and a memory control circuit unit.
Mobile phones, tablet computers, and notebook computers have grown rapidly in the past few years, which has led to a rapid increase in consumer demands for storage media. Since a rewritable non-volatile memory module (e.g., flash memory) has properties of non-volatile data, power saving, small size, and non-mechanical structure, it is thus well suitable for being built into the above-mentioned examples of portable electronic devices.
Some types of memory storage devices support a data splitting mechanism to write single pieces of write data with different data amounts into corresponding memory blocks. For example, data whose data amount is less than a predetermined data amount is written into a small data block, and data whose data amount is not less than the predetermined data amount is written into a large data block. Although this data splitting mechanism may improve data writing efficiency, it is also likely to scatteredly store continuous data to discontinuous physical addresses, accordingly leading to troubles in subsequent management.
The disclosure provides a data writing method, a memory storage device, and a memory control circuit unit, in which data writing efficiency and writing continuity may be achieved.
An exemplary embodiment of the disclosure provides a data writing method for a rewritable non-volatile memory module. The rewritable non-volatile memory module includes a plurality of physical units. The data writing method includes the following. A write command is received from a host system. The write command instructs storing of first data belonging to a first logical unit. In response to the first data being first type data, the first data is stored in a first type physical unit among the plurality of physical units according to the write command and first count information corresponding to a first logical range is updated. The first logical unit belongs to the first logical range. In response to the first count information meeting a preset condition, the first data is moved from the first type physical unit to a second type physical unit among the plurality of physical units.
An exemplary embodiment of the disclosure also provides a memory storage device. The memory storage device includes a connection interface unit for coupling to a host system, a rewritable non-volatile memory module, and a memory control circuit unit. The rewritable non-volatile memory module comprises a plurality of physical units. The memory control circuit unit is coupled to the connection interface unit and the rewritable non-volatile memory module. The memory control circuit unit is configured to: receive a write command from the host system, the where write command instructs storing of first data belonging to a first logical unit; in response to the first data being first type data, store the first data in a first type physical unit among the plurality of physical units according to the write command and update first count information corresponding to a first logical range, where the first logical unit belongs to the first logical range; and in response to the first count information meeting a preset condition, move the first data from the first type physical unit to a second type physical unit among the plurality of physical units.
An exemplary embodiment of the disclosure also provides a memory control circuit unit configured to control a rewritable non-volatile memory module. The rewritable non-volatile memory module includes a plurality of physical units. The memory control circuit unit includes a host interface for coupling to a host system, a memory interface for coupling to the rewritable non-volatile memory module, and a memory management circuit. The memory management circuit is coupled to the host interface and the memory interface. The memory management circuit is configured to: receive a write command from the host system, where the write command instructs storing of first data belonging to a first logical unit; in response to the first data being first type data, store the first data in a first type physical unit among the plurality of physical units according to the write command and update first count information corresponding to a first logical range, where the first logical unit belongs to the first logical range; and in response to the first count information meeting a preset condition, move the first data from the first type physical unit to a second type physical unit among the plurality of physical units.
Based on the foregoing, after receiving the write command instructing storing of the first data belonging to the first logical unit from the host system, in response to the first data being the first type data, the first data may be stored in the first type physical unit, and the first count information corresponding to the first logical range may be updated. Afterward, in response to the first count information meeting a preset condition, the first data may be moved from the first type physical unit to the second type physical unit. Accordingly, data writing efficiency and writing continuity may be effectively achieved.
To make the aforementioned more comprehensible, several embodiments accompanied with drawings are described in detail as follows.
The accompanying drawings are included to provide a further understanding of the disclosure, and are incorporated in and constitute a part of this specification. The drawings illustrate exemplary embodiments of the disclosure and, together with the description, serve to explain the principles of the disclosure.
Generally speaking, a memory storage device (also referred to as a memory storage system) includes a rewritable non-volatile memory module and a controller (also referred to as a control circuit). The memory storage device may be used together with a host system for the host system to write data into the memory storage device or read data from the memory storage device.
With reference to
In an exemplary embodiment, the host system 11 may be coupled to a memory storage device 10 through the data transmission interface 114. For example, the host system 11 may store data into the memory storage device 10 or read data from the memory storage device 10 through the data transmission interface 114. In addition, the host system 11 may be coupled to an I/O device 12 through the system bus 110. For example, the host system 11 may transmit an output signal to the I/O device 12 or receive an input signal from the I/O device 12 through the system bus 110.
In an exemplary embodiment, the processor 111, the random access memory 112, the read only memory 113, and the data transmission interface 114 may be disposed on a motherboard 20 of the host system 11. The data transmission interface 114 may include one or more data transmission interfaces. Through the data transmission interface 114, the motherboard 20 may be coupled to the memory storage device 10 in a wired or wireless manner.
In an exemplary embodiment, the memory storage device 10 may be, for example, a flash drive 201, a memory card 202, a solid state drive (SSD) 203, or a wireless memory storage device 204. The wireless memory storage device 204 may be, for example, a near-field communication (NFC) memory storage device, a Wireless Fidelity (WiFi) memory storage device, a Bluetooth memory storage device, a Bluetooth Low Energy memory storage device (e.g., iBeacon), or any other memory storage device based on various modes of wireless communication technology. In addition, the motherboard 20 may also be coupled to various I/O devices such as a Global Positioning System (GPS) module 205, a network interface card 206, a wireless transmission device 207, a keyboard 208, a screen 209, or a speaker 210 through the system bus 110. For example, in an exemplary embodiment, the motherboard 20 may access the wireless memory storage device 204 through the wireless transmission device 207.
In an exemplary embodiment, the host system 11 is a computer system. In an exemplary embodiment, the host system 11 may be any system that substantially works with a memory storage device to store data. In an exemplary embodiment, the memory storage device 10 and the host system 11 may respectively include a memory storage device 30 and a host system 31 in
The connection interface unit 41 is configured to couple the memory storage device 10 with the host system 11. The memory storage device 10 may communicate with the host system 11 through the connection interface unit 41. In an exemplary embodiment, the connection interface unit 41 is compatible with Peripheral Component Interconnect Express (PCI Express). In an exemplary embodiment, the connection interface unit 41 may also be compatible with the Serial Advanced Technology Attachment (SATA) standard, Parallel Advanced Technology Attachment (PATA) standard, Institute of Electrical and Electronic Engineers (IEEE) 1394 standard, Universal Serial Bus (USB) Standard, SD interface standard, Ultra High Speed-I (UHS-I) interface standard, Ultra High Speed-II (UHS-II) interface standard, Memory Stick (MS) interface standard, MCP interface standard, MMC interface standard, eMMC Interface standard, Universal Flash Storage (UFS) interface standard, eMCP interface standard, CF interface standard, Integrated Device Electronics (IDE) standard, or other suitable standards. The connection interface unit 41 may be packaged into the same chip with the memory control circuit unit 42. Alternatively, the connection interface unit 41 may be arranged outside a chip including the memory control circuit unit 42.
The memory control circuit unit 42 is coupled to the connection interface unit 41 and the rewritable non-volatile memory module 43. The memory control circuit unit 42 is configured to execute a plurality of logic gates or control instructions implemented in a hardware form or firmware form and performs operations such as writing, reading, and erasing data in the rewritable non-volatile memory module 43 according to instructions of the host system 11.
The rewritable non-volatile memory module 43 is configured to store data written by the host system 11. The rewritable non-volatile memory module 43 may include a single-level cell (SLC) NAND-type flash memory module (i.e., a flash memory module that stores 1 bit in one memory cell), a multi-level cell (MLC) NAND-type flash memory module (i.e., a flash memory module that stores 2 bits in one memory cell), a triple-level cell (TLC) NAND-type flash memory module (i.e., a flash memory module that stores 3 bits in one memory cell), a quad-level cell (QLC) NAND-type flash memory module (i.e., a flash memory module that stores 4 bits in one memory cell), other flash memory modules, or other memory modules with the same properties.
In the rewritable non-volatile memory module 43, each memory cell stores one or more bits by a voltage change (hereinafter also referred to as a threshold voltage). Specifically, in each memory cell, an electric charge trapping layer is present between a control gate and a channel. By applying a write voltage to the control gate, the amount of electrons in the electric charge trapping layer may be changed, further changing the threshold voltage of the memory cell. This operation of changing the threshold voltage of the memory cell is also referred to as “writing data into the memory cell” or “programming the memory cell”. As the threshold voltage changes, each memory cell in the rewritable non-volatile memory module 43 may be in a plurality of storage states. By applying a read voltage, the storage state to which a memory cell belongs may determined, thereby obtaining one or more bits stored in the memory cell.
In an exemplary embodiment, the memory cells of the rewritable non-volatile memory module 43 may constitute a plurality of physical programming units, and the physical programming units may constitute a plurality of physical erasing units. Specifically, the memory cells on the same word line may form one or more physical programming units. If each memory cell stores more than 2 bits, the physical programming units on the same word line may be at least classified into a lower physical programming unit and an upper physical programming unit. For example, the least significant bit (LSB) of a memory cell belongs to the lower physical programming unit, and the most significant bit (MSB) of a memory cell belongs to the upper physical programming unit. Generally speaking, in MLC NAND-type flash memory, the write speed of the lower physical programming unit is greater than the write speed of the upper physical programming unit, and/or the reliability of the lower physical programming unit is higher than the reliability of the upper physical programming unit.
In an exemplary embodiment, the physical programming units are the minimum unit for programming. That is, the physical programming units are the minimum unit for data write. For example, the physical programming units may include a physical page or a physical sector. If the physical programming units are physical pages, the physical programming units may include a data bit region and a redundancy bit region. The data bit region includes a plurality of physical sectors configured to store user data, and the redundancy bit region is configured to store system data (e.g., error correcting codes or other management data). In an exemplary embodiment, the data bit region includes 32 physical sectors, and the size of a physical sector is 512 bytes (B). However, in other exemplary embodiments, the data bit region may also include 8, 16, or more or less physical sectors, and the size of each physical sector may also be greater or smaller. On the other hand, the physical erasing units are the minimum unit of erase. That is, each physical erasing unit includes the minimum number of memory cells that are erased together. For example, the physical erasing units include a physical block.
The memory management circuit 51 is configured to control the overall operation of the memory control circuit unit 42. Specifically, there exist a plurality of control instructions in the memory management circuit 51. During operation of the memory storage device 10, the control instructions are executed to perform operations such as writing, reading, and erasing data. Hereinafter, when the operation of the memory management circuit 51 is descried, the operation of the memory control circuit unit 42 is equivalently described.
In an exemplary embodiment, the control instructions of the memory management circuit 51 are implemented in a firmware form. For example, the memory management circuit 51 is provided with a microprocessor unit (not shown) and read only memory (not shown), and the control instructions are programmed into the read only memory. During operation of the memory storage device 10, the control instructions are executed by the microprocessor unit to perform operations such as writing, reading, and erasing data.
In an exemplary embodiment, the control instructions of the memory management circuit 51 may also be stored in a specific area (e.g., a system region dedicated to storing system data in the memory module) of the rewritable non-volatile memory module 43. In addition, the memory management circuit 51 is provided with a microprocessor unit (not shown), read only memory (not shown), and random access memory (not shown). In particular, there exists a boot code in the read only memory. When the memory control circuit unit 42 is enabled, the microprocessor unit first executes the boot code to load the control instructions stored in the rewritable non-volatile memory module 43 into the random access memory of the memory management circuit 51. After that, the microprocessor unit operates the control instructions to perform operations such as writing, reading, and erasing data.
In an exemplary embodiment, the control instructions of the memory management circuit 51 may also be implemented in a hardware form. For example, the memory management circuit 51 includes a microcontroller, a memory cell management circuit, a memory write circuit, a memory read circuit, a memory erase circuit, and a data processing circuit. The memory cell management circuit, the memory write circuit, the memory read circuit, the memory erase circuit, and the data processing circuit are coupled to the microcontroller. The memory cell management circuit is configured to manage a memory cell or a memory cell group of the rewritable non-volatile memory module 43. The memory write circuit is configured to issue a write command sequence to the rewritable non-volatile memory module 43 to write data into the rewritable non-volatile memory module 43. The memory read circuit is configured to issue a read instruction sequence to the rewritable non-volatile memory module 43 to read data from the rewritable non-volatile memory module 43. The memory erase circuit is configured to issue an erase instruction sequence to the rewritable non-volatile memory module 43 to erase data from the rewritable non-volatile memory module 43. The data processing circuit is configured to process data to be written to the rewritable non-volatile memory module 43 and data read from the rewritable non-volatile memory module 43. The write command sequence, the read instruction sequence, and the erase instruction sequence may each include one or more programming codes or instruction codes and are configured to instruct the rewritable non-volatile memory module 43 to perform corresponding write, read, and erase operations among other operations. In an exemplary embodiment, the memory management circuit 51 may also issue other types of instruction sequences to the rewritable non-volatile memory module 43 to instruct the rewritable non-volatile memory module 43 to perform corresponding operations.
The host interface 52 is coupled to the memory management circuit 51. The memory management circuit 51 may communicate with the host system 11 through the host interface 52. The host interface 52 may be configured to receive and identify instructions and data transmitted by the host system 11. For example, the instructions and data transmitted by the host system 11 may be transmitted to the memory management circuit 51 through the host interface 52. In addition, the memory management circuit 51 may transmit data to the host system 11 through the host interface 52. In this exemplary embodiment, the host interface 52 is compatible with the PCI Express standard. However, it should be understood that the disclosure is not limited thereto. The host interface 52 may also be compatible with the SATA standard, PATA standard, IEEE 1394 standard, USB standard, SD standard, UHS-I standard, UHS-II standard, MS standard, MMC standard, eMMC standard, UFS standard, CF standard, IDE standard or other suitable data transmission standard.
The memory interface 53 is coupled to the memory management circuit 51 and configured to access the rewritable non-volatile memory module 43. For example, the memory management circuit 51 may access the rewritable non-volatile memory module 43 through the memory interface 53. In other words, data to be written into the rewritable non-volatile memory module 43 is converted through the memory interface 53 into a format acceptable by the rewritable non-volatile memory module 43. Specifically, when the memory management circuit 51 is to access the rewritable non-volatile memory module 43, the memory interface 53 will transmit corresponding instruction sequences. For example, the instruction sequences may include a write command sequence commanding data be written, a read instruction sequence commanding data be read, an erase instruction sequence indicating data be erased, and corresponding instruction sequences commanding various memory operations (e.g., changing the read voltage level or performing a garbage collection operation, etc.). The instruction sequences are, for example, generated by the memory management circuit 51 and transmitted through the memory interface 53 to the rewritable non-volatile memory module 43. The instruction sequences may include one or more signals, or data on a bus. The signals or data may include instruction codes or programming codes. For example, in the read instruction sequence, information such as a read identification code or a memory address is included.
In an exemplary embodiment, the memory control circuit unit 42 further includes an error detection and correction circuit 54, a buffer memory 55, and a power management circuit 56.
The error detection and correction circuit 54 is coupled to the memory management circuit 51 and configured to perform error detection and correction operations to ensure data correctness. Specifically, when the memory management circuit 51 receives a write command from the host system 11, the error detection and correction circuit 54 generates a corresponding error correcting code (ECC) and/or error detecting code (EDC) for data corresponding to the write command. In addition, the memory management circuit 51 writes the data corresponding to the write command and the corresponding error correcting code and/or error detecting code into the rewritable non-volatile memory module 43. Later, while reading data from the rewritable non-volatile memory module 43, the memory management circuit 51 also reads the error correcting code and/or error detecting code corresponding to the data. Moreover, the error detection and correction circuit 54 performs error detection and correction operations on the read data according to the error correcting code and/or error detecting code.
The buffer memory 55 is coupled to the memory management circuit 51 and configured to temporarily store data. The power management circuit 56 is coupled to the memory management circuit 51 and configured to control the power of the memory storage device 10.
In an exemplary embodiment, the rewritable non-volatile memory module 43 in
In an exemplary embodiment, one physical unit includes one or more physical blocks. One physical unit may includes a plurality of physical nodes. In an exemplary embodiment, each physical node may store data with a data length of 4 KB. In an exemplary embodiment, each physical node may also store more or less data, which is not limited by the disclosure.
The physical units 610(0) to 610(A) in the storage region 601 are configured to store user data (e.g., user data from the host system 11 in
The memory management circuit 51 may be provided with logical units 612(0) to 612(C) to be mapped to the physical units 610(0) to 610(A) in the storage region 601. In an exemplary embodiment, each logical unit corresponds to one logical address. For example, one logical address may include one or more logical block addresses (LBA) or other logical management units. In an exemplary embodiment, one logical unit may also correspond to one logical programming unit or may be formed by a plurality of continuous or discontinuous logical addresses.
Note that one logical unit may be mapped to one or more physical units. If a certain physical unit is currently mapped to a certain logical unit, it means that data currently stored in this physical unit includes valid data. Comparatively, if a certain physical unit is currently not mapped to any logical unit, it means that data currently stored in this physical unit is invalid data.
The memory management circuit 51 may record mapping information (also referred to as logical-to-physical mapping information) describing the mapping relationship between logical units and physical units in at least one mapping table (also referred to as a logical-to-physical mapping table). When the host system 11 is to read data from the memory storage device 10 or write data into the memory storage device 10, the memory management circuit 51 may access the rewritable non-volatile memory module 43 according to the information (i.e., mapping information) in the mapping table.
In an exemplary embodiment, in response to the data 701 being first type data, the memory management circuit 51 may instruct the rewritable non-volatile memory module 43 to store the data 701 in a first type physical unit 71 according to the write command. For example, the memory management circuit 51 may retrieve at least one physical unit from the spare region 602 in
On the other hand, in response to the data 701 being first type data, the memory management circuit 51 may also update count information (also referred to as first count information) corresponding to a specific logical range (also referred to as a first logical range). In particular, the first logical unit belongs to the first logical range. For example, assuming that the first logical unit corresponds to a logical block address LBA(20), then the first logical range may cover logical block addresses LBA(0) to LBA(1023). The size of each logical range may be adjusted depending on practical requirements.
After storing the data 701 in the first type physical unit 71 and updating the first count information, the memory management circuit 51 may determine whether the first count information meets a preset condition. In response to the first count information meeting the preset condition, the memory management circuit 51 may instruct the rewritable non-volatile memory module 43 to move the data 701 from the first type physical unit 71 to a second type physical unit 72. For example, the memory management circuit 51 may retrieve at least one physical unit from the spare region 602 in
In an exemplary embodiment, in response to the data 701 being second type data, the memory management circuit 51 may instruct the rewritable non-volatile memory module 43 to store the data 701 in the second type physical unit 72 according to the write command. In other words, in the case where the data 701 is second type data, the data 701 may be directly stored in the second type physical unit 72 instead of being first stored in the first type physical unit 71 and then moved to the second type physical unit 72. From another point of view, according to whether the data 701 is first type data or second type data, the data 701 may be directly stored in one of the first type physical unit 71 and the second type physical unit 72.
In an exemplary embodiment, the memory management circuit 51 may determine whether the data 701 belongs to first type data or second type data according to a data amount of the data 701. For example, the memory management circuit 51 may determine whether the data amount of the data 701 is less than a critical data amount. In response to the data amount of the data 701 being less than the critical data amount, the memory management circuit 51 may determine that the data 701 belongs to first type data. Alternatively, in response to the data amount of the data 701 being not less than (i.e., greater than or equal to) the critical data amount, the memory management circuit 51 may determine that the data 701 belongs to second type data. The critical data amount may be set depending on practical requirements, and is not limited by the disclosure.
In an exemplary embodiment, the first type physical unit 71 may be dedicated to storing data whose data amount is less than the critical data amount, and the second type physical unit 72 may be dedicated to storing data whose data amount is not less than the critical data amount. Accordingly, regardless of the data amount of the data 701 currently received from the host system 11, the data 701 may be stored in the corresponding type of physical unit in an appropriate manner, accordingly improving storage efficiency of the data 701.
In an exemplary embodiment, the first count information includes a count value. The memory management circuit 51 may determine whether the first count information meets a preset condition according to the count value. For example, the memory management circuit 51 may determine whether the count value reaches a critical value. In response to the count value reaching the critical value, the memory management circuit 51 may determine that the first count information meets the preset condition. Alternatively, in response to the count value not reaching the critical value, the memory management circuit 51 may determine that the first count information does not meet the preset condition.
In an exemplary embodiment, the first count information (or the count value) may reflect how much data belonging to the first logical range has currently been stored in the first type physical unit 71. In an exemplary embodiment, if the count value reaches the critical value, it means that at least part of the data belonging to the first logical range has currently been stored in the first type physical unit 71. As a result, in response to the count value reaching the critical value (i.e., the first count information meeting the preset condition), the memory management circuit 51 may instruct the rewritable non-volatile memory module 43 to move the data (including the first data) originally scatteredly stored in the first type physical unit 71 and belonging to the first logical range to the second type physical unit 72 for continuous and/or centralized storage. Accordingly, subsequent management efficiency of data belonging to the first logical range may be effectively improved. Nonetheless, if the count value does not reach the critical value (i.e., the first count information does not meet the preset condition), it is possible to temporarily not move the data belonging to the first logical range (i.e., retain the first data in the first type physical unit 71).
In an exemplary embodiment, in response to the first count information meeting the preset condition, the memory management circuit 51 may move the data 701 together with another data (also referred to as second data) in the first type physical unit 71 to the second type physical unit 72. In particular, the second data belongs to a specific logical unit (also referred to as a second logical unit), and the second logical unit also belongs to the first logical range. In addition, after the first data and the second data are moved to the second type physical unit 72, the first data and the second data still stored in the first type physical unit 71 may be labeled as invalid data.
Note that, in the first type physical unit 81, the data D(R1.1), D(R1.2), and D(R1.3) are scatteredly stored in a plurality of discontinuous entity sub-units (e.g., physical pages, physical sectors, or physical nodes). In this case, the storage (i.e., discontinuous storage) of the data D(R1.1), D(R1.2), and D(R1.3) in the first type physical unit 81 is not beneficial to continuous reading of the data D(R1.1), D(R1.2), and D(R1.3).
In an exemplary embodiment, in response to the count information corresponding to the first logical range (i.e., the first count information) meeting the preset condition, the data D(R1.1), D(R1.2), and D(R1.3) may be moved from the first type physical unit 81 to a second type physical unit 82 for continuous and/or centralized storage. For example, in the second type physical unit 82, the data D(R1.1), D(R1.2), and D(R1.3) may be stored in a plurality of continuous entity sub-units (e.g., physical pages, physical sectors, or physical nodes). In particular, the storage (i.e., continuous storage) of the data D(R1.1), D(R1.2), and D(R1.3) in the second type physical unit 82 is beneficial to subsequent continuous reading of the data D(R1.1), D(R1.2), and D(R1.3). In addition, after the data D(R1.1), D(R1.2), and D(R1.3) are moved to the second type physical unit 82, the data D(R1.1), D(R1.2), and D(R1.3) still stored in the first type physical unit 81 may be labeled as invalid data.
In an exemplary embodiment, the memory management circuit 51 may store count information corresponding to a plurality of logical ranges in one or more count tables. Afterward, the memory management circuit 51 may dynamically update the count information according to the data storage conditions corresponding to these logical ranges.
In an exemplary embodiment, the memory management circuit 51 may dynamically update the information in the count table 91 according to the current data writing conditions. For example, in response to the first type data that belongs to the first logical range being stored in the first type physical unit, the count value C1 (i.e., the first count information) corresponding to the first logical range may be updated to reflect the latest data storage conditions of the first logical range.
In an exemplary embodiment, after moving the data 701 from the first type physical unit 71 to the second type physical unit 72, the memory management circuit 51 may clear or reset the first count information. In addition, the memory management circuit 51 may also adopt various table management and optimization techniques such as competition and/or coding to improve efficiency of recording information in the count table 91, which will not be repeatedly described here.
In an exemplary embodiment, during or after moving the data 701 from the first type physical unit 71 to the second type physical unit 72, the memory management circuit 51 may detect abnormal power failure of the memory storage device 10. In response to the abnormal power failure, after the memory storage device 10 is powered on again, the memory management circuit 51 may reconstruct management data corresponding to the first type physical unit 71 (also referred to as first management data) and management data corresponding to the second type physical unit 72 (also referred to as second management data). For example, the first management data includes a timestamp corresponding to the data 701 being written into the first type physical unit 71, and/or the second management data includes a timestamp corresponding to the data 701 being written into the second type physical unit 72. Then, the memory management circuit 51 may determine whether the data 701 in the first type physical unit 71 is valid data according to the first management data and the second management data.
In an exemplary embodiment, it is assumed that abnormal power failure of the memory storage device 10 occurs during or after moving the data D(R1.2). After the memory storage device 10 is powered on again, in response to the abnormal power failure, the memory management circuit 51 may reconstruct the management data corresponding to the first type physical unit 81 (i.e., the first management data) and the management data corresponding to the first type physical unit 82 (i.e., the second management data). For example, the first management data may include the timestamp TS(1) corresponding to the data D(R1.2), and the second management data may include the timestamp TS(2) corresponding to the data D(R1.2).
In an exemplary embodiment, the memory management circuit 51 may determine whether the data D(R1.2) in the first type physical unit 81 is valid data according to the timestamps TS(1) and TS(2) in the reconstructed management data. For example, in response to the value of the timestamp TS(2) being greater than the value of TS(1), it means that the time point when the data D(R1.2) is stored in the second type physical unit 82 is later than the time point when the data D(R1.2) is stored in the first type physical unit time point of 81. As a result, the memory management circuit 51 may determine that data movement of the data D(R1.2) has been completed previously and the data D(R1.2) in the first type physical unit 81 is invalid data.
On the other hand, if the value of the timestamp TS(2) is not greater than the value of TS(1) or the timestamp TS(2) is not present in the second management data, it means that previous data movement of the data D(R1.2) has not been completed or has failed. As a result, the memory management circuit 51 may determine that the data D(R1.2) in the first type physical unit 81 is still valid data. Accordingly, regardless of whether abnormal power failure occurs or not, the memory management circuit 51 may manage the data (i.e., valid data) in the first type physical unit 81 normally. In addition, once the data (i.e., valid data) in the first type physical unit 81 have been moved to the second type physical unit 82, the first type physical unit 81 may be associated with the spare region 602 in
In step S1105, it is determined whether the first count information meets a preset condition. If the first count information meets the preset condition, in step S1106, the first data is moved from the first type physical unit to a second type physical unit. Comparatively, if the first count information does not meet the preset condition, step S1101 may be performed repeatedly to subsequently process the next command (e.g., the write command) from the host system. On the other hand, in step S1102, if it is determined that the first data does not belong to first type data (for example, the first data belongs to second type data), in step S1107, the first data is stored in a second type physical unit according to the write command.
Nonetheless, the steps in
In summary of the foregoing, the data writing method, the memory storage device, and the memory control circuit unit proposed by the exemplary embodiments of the disclosure may ensure continuity of data belonging to the same logical range in the physical storage space by performing subsequent data moving and merging on the premise of satisfying predetermined data split storage. Accordingly, data writing efficiency and writing continuity may be achieved.
It will be apparent to those skilled in the art that various modifications and variations can be made to the disclosed embodiments without departing from the scope or spirit of the disclosure. In view of the foregoing, it is intended that the disclosure covers modifications and variations provided that they fall within the scope of the following claims and their equivalents.
| Number | Date | Country | Kind |
|---|---|---|---|
| 202310184408.8 | Feb 2023 | CN | national |
