Claims
- 1. An apparatus for performing predicate evaluation, said apparatus comprising
- instruction table means for storing a predicate evaluation program, the instruction table means comprising means for receiving the predicate evaluation program from an external processor;
- instruction register means, coupled with the instruction table means, for receiving an instruction to be executed from the instruction table means, said instruction register means including a field for storing a branching condition and a field for storing a branching address;
- internal processor means coupled with the instruction table means, coupled with the instruction register means, for controlling a sequence of operations within the predicate evaluation apparatus in accordance with the predicate evaluation program, said internal processor being programmable by said predicate evaluation program;
- next field branching means, coupled with the instruction register means and responsive to a branch condition stored in said field for storing a branch condition, for determining when a processing operation of a predicate evaluation query causing processing of records in operations on sequential portions produces a result matching said branch condition, without processing the entire record, and for causing the internal processor means to branch to said branch address and around unnecessary instructions for processing the rest of the record in the predicate evaluation program for processing the query;
- a stack for temporarily holding data during the processing of the predicate evaluation program, said data being other than said predicate evaluation program; and
- comparator means, coupled with the internal processor means, for comparing a first value from the top of the stack with a second value obtained from the working storage.
- 2. The apparatus of claim 1 wherein said instruction register means comprises flag bits which control said next field branching means, a first next field which specifies an instruction address to be branched to if execution of said instruction results in true, and a second next field which specifies an instruction address to be branched to if execution of said instruction results in false.
- 3. An apparatus, as recited in claim 1 wherein said predicate evaluation program utilizes a postfix processing.
- 4. An apparatus for performing predicate evaluation, said apparatus comprising
- instruction table means for storing a predicate evaluation program, the instruction table means comprising means for receiving the predicate evaluation program from an external processor;
- instruction register means, coupled with the instruction table means, for receiving an instruction to be executed from the instruction table means, said instruction register means including a field for storing a branching condition and a field for storing a branching address;
- internal processor means having a pipeline length coupled with the instruction table means, coupled with the instruction register means, for controlling a sequence of operations within the predicate evaluation apparatus in accordance with the predicate evaluation program, said internal processor being programmable by said predicate evaluation program;
- next field branching means, coupled with the instruction register means and responsive to a branch condition in said field for storing a branch condition, for determining when a processing operation of a predicate evaluation query causing processing of records in portions has been resolved by producing an operation result which matches said branch condition, allowing an early exit out of the current predicate term or out of the entire predicate and for causing the internal processor means to branch around unnecessary instructions in the predicate evaluation program for processing the query if the number of instructions to said branch address exceeds said pipeline length;
- a stack for temporarily holding data during the processing of the predicate evaluation program, said data being other than said predicate evaluation program; and
- comparator means, coupled with the internal processor means, for comparing a first value from the top of the stack with a second value obtained from the working storage.
Parent Case Info
This is a continuation of application Ser. No. 08/243,729 filed May 7, 1994, which was a continuation of application Ser. No. 07/993,729 filed Dec. 18, 1992, now abandoned, which is a divisional of application Ser. No. 07/499,849 filed on Mar. 27, 1990, now U.S. Pat. No. 5,082,740.
US Referenced Citations (3)
Number |
Name |
Date |
Kind |
4674066 |
Kucera |
Jun 1987 |
|
5050075 |
Herman et al. |
Sep 1991 |
|
5239663 |
Faudemay et al. |
Aug 1993 |
|
Foreign Referenced Citations (4)
Number |
Date |
Country |
0066061 |
Dec 1982 |
EPX |
0070119 |
Jan 1983 |
EPX |
2235798 |
Mar 1991 |
GBX |
8912277 |
Dec 1989 |
WOX |
Non-Patent Literature Citations (3)
Entry |
Patent Abstracts of Japan, vol. 13, No. 448, p. 942, Oct. 9, 1989. Abstract only. |
Patent Abstracts of Japan, vol. 14, No. 179, p. 1034, Apr. 10, 1990. Abstract only. |
"Microprocessors and Microcomputer Development Systems: Designing Microprocessor-Based Systems", by Rafiquzzaman, 1984, pp. 66-85 and 610-611. |
Divisions (1)
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Number |
Date |
Country |
Parent |
499849 |
Mar 1990 |
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Continuations (2)
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Number |
Date |
Country |
Parent |
243729 |
May 1994 |
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Parent |
993170 |
Dec 1992 |
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