DC-AC converter

Abstract

A DC-AC converter has two half-bridge circuits using an input feedback signal and an input clock signal together with time delay circuits, wherein one of the half-bridge circuits drives one pair of corresponding FETs and the other half-bridge circuit drives the other pair of corresponding FETs. The DC-AC converter includes: a Direct Current (DC) power source; a switching unit which includes a plurality of Field Effect Transistors (FETs) for changing paths of Direct Current (DC), so as to convert the DC to Alternating Current (AC); a transformer for transforming a voltage input from the switching unit; a load unit connected to the transformer; and a signal control unit for simultaneously parallel control of the FETs in the switching unit.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other objects, features and advantages of the present invention will be more apparent from the following detailed description taken in conjunction with the accompanying drawings, in which:

FIG. 1 is a circuit diagram illustrating a conventional DC-AC converter;

FIG. 2 a is a block diagram illustrating a DC-AC converter according to the present invention;

FIG. 2 b is a block diagram illustrating a feedback control unit, a signal control unit, and an FET driver in the DC-AC converter of FIG. 2a;

FIG. 3 is a circuit diagram of a logic circuit for a signal control unit of a DC-AC converter according to an embodiment of the present invention;

FIG. 4 a illustrates waveforms of signals by each FET of a conventional DC-AC converter; and

FIG. 4 b illustrates waveforms of signals by each FET of a DC-AC converter according to an embodiment of the present invention.

Claims

1. A Direct Current to Alternating Current (DC-AC) converter comprising: a Direct Current (DC) power source;a switching unit which includes a plurality of Field Effect Transistors (FETs) for changing paths of Direct Current (DC), so as to convert the DC to Alternating Current (AC);a transformer for transforming a voltage input from the switching unit;a load unit connected to the transformer; anda signal control unit for simultaneously parallel control of the FETs in the switching unit.

2. The DC-AC converter as claimed in claim 1, wherein the FETs in the switching unit include a first P channel FET and a first N channel FET, which are interconnected in series and connected in parallel to the DC power source, and a second P channel FET and a second N channel FET, which are interconnected in series and connected in parallel to the DC power source.

3. The DC-AC converter as claimed in claim 2, further comprising a feedback control unit connected between the switching unit and the load unit, so as to generate and output a predetermined signal by using a feedback signal from the load unit and a clock signal from the oscillator.

4. The DC-AC converter as claimed in claim 3, wherein the signal control unit outputs four control signals by using the predetermined signal from the feedback control unit and the clock signal of the oscillator, so as to simultaneously control the first P channel FET, the first N channel FET, the second P channel FET, and the second N channel FET in parallel.

5. The DC-AC converter as claimed in claim 4, further comprising a FET driver unit which includes a first driver and a second driver, wherein the first driver receives two control signals from the signal control unit and then outputs driving signals to the first P channel FET and the first N channel FET of the switching unit, and the second driver receives the other two control signals from the signal control unit and then outputs driving signals to the second P channel FET and the second N channel FET of the switching unit.

6. The DC-AC converter as claimed in claim 5, wherein the transformer includes a first coil and a second coil, the first coil has one end connected to a line between the second P channel FET and the second N channel FET of the switching unit and has the other end connected to a line between the first P channel FET and the first N channel FET, and both ends of the second coil are connected to the load unit while one end of the second coil is connected to the second N channel FET of the switching unit.

7. The DC-AC converter as claimed in claim 6, wherein the signal control unit forms a first current path through the first coil by turning on the first P channel FET P1 and the second N channel FET together during a predetermined time interval, and then forms a second current path through the first coil by turning on the second P channel FET and the first N channel FET together during a predetermined time interval, the first current path being opposite to the second current path.

8. The DC-AC converter as claimed in claim 7, wherein the signal control unit controls a time interval for simultaneous turning-on of both the first P channel FET and the second N channel FET and a time interval for simultaneous turning-on of both the second P channel FET and the first N channel FET based on a reference signal from the feedback control unit.

9. The DC-AC converter as claimed in claim 7, wherein the signal control unit comprises a first half-bridge circuit for controlling the first P channel FET and the first N channel FET and a second half-bridge circuit for controlling the second P channel FET and the second N channel FET.

10. The DC-AC converter as claimed in claim 7, wherein, in order to control the first P channel FET, the signal control unit comprises: a toggle switch to which a clock signal of the oscillator is input;a first AND gate to which the reference signal output from the feedback control unit and the clock signal output from the toggle switch are input;a time delay unit which delays a signal from the first AND gate for a predetermined time interval and then outputs a delayed signal;a first inverter for inverting a signal from the time delay unit and outputting an inverted signal;a second AND gate to which a signal from the first AND gate and the inverted signal from the first inverter are input; anda second inverter to which a signal from the second AND gate is input.

11. The DC-AC converter as claimed in claim 10, wherein the time delay unit comprises: a P channel FET, a gate voltage of which is controlled by an input signal;a static current source connected to a drain of the P channel FET;a comparator having an inverting node connected to a line between the P channel FET and the static current source and a non-inverting node connected to a reference voltage source; anda capacitor connected to a line between a grounding node and the non-inverting node of the comparator.

12. The DC-AC converter as claimed in claim 7, wherein, in order to control the first N channel FET, the signal control unit comprises: a toggle switch to which a clock signal of the oscillator is input;a first AND gate to which the reference signal output from the feedback control unit and the clock signal output from the toggle switch are input;a first inverter for inverting a signal from the first AND gate and outputting an inverted signal;a time delay unit which delays a signal from the first inverter for a predetermined time interval and then outputs a delayed signal;a second inverter for inverting a signal from the time delay unit and outputting an inverted signal;a second AND gate to which the inverted signal from the first inverter and the inverted signal from the second inverter are input;a third inverter to which a signal from the second AND gate is input; anda fourth inverter to which a signal from the third AND gate is input.

13. The DC-AC converter as claimed in claim 12, wherein the time delay unit comprises: a P channel FET, a gate voltage of which is controlled by an input signal;a static current source connected to a drain of the P channel FET;a comparator having an inverting node connected to a line between the P channel FET and the static current source and a non-inverting node connected to a reference voltage source; anda capacitor connected to a line between a grounding node and the non-inverting node of the comparator.

14. The DC-AC converter as claimed in claim 7, wherein, in order to control the second P channel FET, the signal control unit comprises: a toggle switch to which a clock signal of the oscillator is input;a first inverter to which a signal output from the toggle switch is input;a first AND gate to which the reference signal output from the feedback control unit and a signal output from the first inverter are input;a time delay unit which delays a signal from the first AND gate for a predetermined time interval and then outputs a delayed signal;a second inverter for inverting a signal from the time delay unit and outputting an inverted signal;a second AND gate to which a signal from the first AND gate and a signal from the second inverter are input; anda third inverter to which a signal from the second AND gate is input.

15. The DC-AC converter as claimed in claim 14, wherein the time delay unit comprises: a P channel FET, a gate voltage of which is controlled by an input signal;a static current source connected to a drain of the P channel FET;a comparator having an inverting node connected to a line between the P channel FET and the static current source and a non-inverting node connected to a reference voltage source; anda capacitor connected to a line between a grounding node and the non-inverting node of the comparator.

16. The DC-AC converter as claimed in claim 7, wherein, in order to control the second N channel FET, the signal control unit comprises: a toggle switch to which a clock signal of the oscillator is input;a first inverter to which a signal output from the toggle switch is input;a first AND gate to which the reference signal output from the feedback control unit and a signal output from the first inverter are input; a second inverter for inverting and outputting a signal from the first AND gate;a time delay unit which delays a signal from the second inverter for a predetermined time interval and then outputs a delayed signal;a third inverter for inverting a signal from the time delay unit and outputting an inverted signal;a second AND gate to which a signal from the second inverter and a signal from the third inverter are input;a fourth inverter to which a signal from the second AND gate is input; anda fifth inverter to which a signal from the fourth inverter is input.

17. The DC-AC converter as claimed in claim 16, wherein the time delay unit comprises: a P channel FET, a gate voltage of which is controlled by an input signal;a static current source connected to a drain of the P channel FET;a comparator having an inverting node connected to a line between the P channel FET and the static current source and a non-inverting node connected to a reference voltage source; anda capacitor connected to a line between a grounding node and the non-inverting node of the comparator.