Patent Application
20140111177
1. Technical Field
The present disclosure relates to a direct current (DC) converter/conversion circuit and a method for driving the same.
2. Description of Related Art
DC-DC conversion circuits, such as buck converters, are used to provide DC voltages to electronic components. The buck converter is usually controlled by a controlling integrated circuit (IC) and a driving IC. The controlling IC generates a first control signal and provides the first control signal to the driving IC, and the driving IC generates a second control signal according to the first control signal. The buck converter receives the first control signal and the second control signal and converts a first DC voltage into a second DC voltage under the control of the first control signal and the second control signal. A voltage value of the second DC voltage relates to a duty ratio of the first control signal and the second control signal. However, the duty ratios of both the first control signal and the second control signal generally are not less than 10% due to the limitations of fabricating abilities of the controlling IC and driving IC, that may cause a voltage value of the second DC voltage may not achieve a lower value. This means, a range of regulating the output voltage of the DC-DC converter may be limited.
Therefore, what is needed is a means that can overcome the above-described limitations.
The components in the drawings are not necessarily drawn to scale, the emphasis instead placed upon clearly illustrating the principles of at least one embodiment. In the drawings, like reference numerals designate corresponding parts throughout the various views, and all the views are schematic.
The disclosure, including the accompanying drawings, is illustrated by way of example and not by way of limitation. It should be noted that references to “an” or “one” embodiment in this disclosure are not necessarily to the same embodiment, and such references mean “at least one.”
The first signal generating unit 10 can be a controlling IC (such as a PWM IC) and is configured to provide a first PWM signal to the signal processing unit 30. In the embodiment, the first PWM signal is a square signal, which periodically changes at a first frequency, a time period DH, and a duty ratio TH. A duty ratio of the first PWM signal is in a range from 0 to 1 (0<DH<1), and the duty ratio of the first PWM signal is regulated by the first signal generating unit 10.
The signal processing unit 30 further includes a first logic unit 33, a second logic unit 35, and a second signal generating unit 31. The signal processing unit 30 serves as a driving IC and is configured to receive the first PWM signal and a second PWM signal generated by the second signal generating unit 31, generates a first control signal in response to receiving the first PWM signal and the second PWM signal, generates a second control signal in response to receiving the first control signal, and provides the first control signal and the second control signal to the voltage converting unit 50. In the embodiment, the second signal generating unit 31 is embedded in the signal processing unit 30.
The second signal generating unit 31 is connected to the first logic unit 33, and the first logic unit 33 is connected between the second signal generating unit 31 and the second logic unit 35. The second signal generating unit 31 provides the second PWM signal to the first logic unit 33. In the embodiment, the second PWM signal is a square signal, which periodically changes at a second frequency, a time period DL and a duty ratio TL. A duty ratio of the second PWM signal is in a range from 0 to 1 (0<DL<1), and the duty ratio of the second PWM signal is regulated by the second signal generating unit 31. In the embodiment, the second frequency is different from the first frequency. The duty ratio of the second PWM signal is substantially equal to the duty ratio of the first PWM signal. In other embodiments, the duty ratio of the second PWM signal is different from the duty ratio of the first PWM signal.
In the embodiment, the first logic unit 33 is an AND gate and is configured to generate a first control signal by performing an AND operation in response to receiving the first PWM signal and the second PWM signal. The first control signal is provided to the voltage converting unit 50 and the second logic unit 35.
The second logic unit 35 may be a NOT gate and is configured to generate a second control signal by performing a NOT operation in response to receiving the first control signal. The second control signal is also provided to the voltage converting unit 50.
The voltage converting unit 50 receives the first control signal and the second control signal output from the signal processing unit 30 and converts a first DC voltage into a second DC voltage. In the embodiment, the voltage converting unit 50 is a buck converter. The voltage converting unit 50 includes a source supply 51, a first switch 53, a second switch 55, a first energy storing unit 57, a second energy storing unit 59, a first voltage output terminal “a,” and a second voltage output terminal “b.” The source supply 51 is connected between the second voltage output terminal “b” and the first switch 53. The first switch 53 is connected to the first voltage output terminal “a” via the first energy storing unit 57. The second switch 55 is connected between the second voltage output terminal “b” and a node between the first switch 53 and the first energy storing unit 57. The second energy storing unit 59 is connected between the first voltage output terminal “a” and the second voltage output terminal “b”.
The source supply 51 is configured to generate the first DC voltage. The source supply 51 includes a first output terminal 511 and a second output terminal 513 and outputs the first DC voltage via the first output terminal 511 and the second output terminal 513.
The first switch 53 receives the first control signal and is switched on or off under the control of the first control signal. The first switch 53 includes a control terminal 531, a first switching terminal 532, and a second switching terminal 533. The control terminal 531 receives the first control signal and controls the first switching terminal 532 and the second switching terminal 533 to switch the first switch 53 on or off. The second switching terminal 533 is connected to the first output terminal 511, and the first switching terminal 532 is connected to the first energy storing unit 57. In the embodiment, the first switch 53 is an n-channel metal-oxide semiconductor field effect transistor (NMOSFET), the control terminal 531 is a gate of the NMOSFET, the first switching terminal 532 is a source of the NMOSFET, and the second switching terminal 533 is a drain of the NMOSFET.
The second switch 55 receives the second control signal and is switched on or off under the control of the second control signal. In the embodiment, the second switch 55 and the first switch 53 are switched on alternately. The second switch 55 includes a control terminal 551, a first switching terminal 552, and a second switching terminal 553. The control terminal 551 receives the second control signal and controls the first switching terminal 552 and the second switching terminal 553 to switch the second switch 55 on or off. The first switching terminal 552 is connected to the second voltage output terminal “b.” The second switching terminal 553 is connected to a node formed between the first switch 53 and the first energy storing unit 57. In the embodiment, the second switch 55 is an NMOSFET. The control terminal 551 is a gate of the NMOSFET, the first switching terminal 552 is a source of the NOMFET, and the second switching terminal 553 is a drain of the NMOSFET.
The first energy storing unit 57 stores energy by being charged by the first DC voltage when the first switch 53 is switched on and discharges the energy to the second energy storing unit 57 when the first switch 53 is switched off. In the embodiment, the first energy storing unit 57 is an inductor.
The second energy storing unit 59 stores energy by being charged by the first energy storing unit 57 and discharges the energy to the load 200. In this process, the energy stored in the second energy storing unit 59 is converted into the second DC voltage. In the embodiment, the second energy storing unit 59 is a capacitor.
In the present disclosure, the first logic unit 33 performs an AND operation in response to receiving the first PWM signal and the second PWM signal, such that a duty ratio of the first control signal is less than both the duty ratio of the first PWM signal and the duty ratio of the second PWM signal. Thus, the voltage converting unit 50 is capable of outputting the second DC voltage having a lower voltage value, even though the duty ratio of the first PWM signal is not less than a predetermined value, such as 10%.
In step S100, a first PWM signal and a second PWM signal are provided.
In step S200, an AND operation is performed to the first PWM signal and the second PWM signal so as to obtain a first control signal.
In step S300, the first control signal is inverted to obtain a second control signal.
In step S400, the first control signal and the second control signal are sent to the voltage converting unit 50. The voltage converting unit 50 converts a first DC voltage into a second DC voltage under the control of the first control signal and the second control signal.
Although certain embodiments of the present disclosure have been specifically described, the present disclosure is not to be construed as being limited thereto. Various changes or modifications may be made to the present disclosure without departing from the scope and spirit of the present disclosure.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2012104051412 | Oct 2012 | CN | national |
