DC-DC converter with modular stages

Description

FIELD OF DISCLOSURE

This disclosure relates to power supplies, and in particular to power converters.

BACKGROUND

Many power converters include switches and one or more capacitors that are used, for example, to power portable electronic devices and consumer electronics. Switch-mode power converters regulate the output voltage or current by switching energy storage elements (i.e. inductors and capacitors) into different electrical configurations using a switch network. Switched capacitor converters are switch-mode power converters that primarily use capacitors to transfer energy. In such converters, the number of capacitors and switches increases as the transformation ratio increases. Switches in the switch network are usually active devices that are implemented with transistors. The switch network may be integrated on a single or on multiple monolithic semiconductor substrates, or formed using discrete devices.

Typical DC-DC converters perform voltage transformation and output regulation. This is usually done in a single-stage converter such as a buck converter. However it is possible to split these two functions into two specialized stages, namely a transformation stage, such as a switching network, and a separate regulation stage, such as a regulating circuit. The transformation stage transforms one voltage into another, while the regulation stage ensures that the voltage and/or current output of the transformation stage maintains desired characteristics.

SUMMARY

In one aspect, the invention features an apparatus for electric power conversion. Such an apparatus includes a converter having an input terminal and an output terminal. The converter includes a regulating circuit having an inductance, and switching elements connected to the inductance. These switching elements are controllable to switch between switching configurations. The regulating circuit maintains an average DC current through the inductance. The converter also includes a switching network having an input port and an output port. This switching network includes charge-storage elements and switching elements connected to the charge-storage elements. These switching elements are controllable to switch between switch configurations. In one switch configuration, the switching elements form a first arrangement of charge-storage elements in which a charge-storage element is charged through one of the input port and the output port of the switching network. In another configuration, the switching elements form a second arrangement of charge-storage elements in which a charge-storage element is discharged through one of the input port and output port of the switching network. The switching network and regulating circuit also satisfy at least one of the following configurations: (1) the regulating circuit is connected between the output terminal of the converter and the switching network, the switching network being an adiabatically charged switching network; (2) the regulating circuit is connected between the output terminal of the converter and the switching network, wherein either the switching network is a multi-phase switching network, the switching network and the regulating circuit are bidirectional, or the regulating circuit is multi-phase; (3) the regulating circuit is connected between the input terminal of the converter and an input port of the switching network, the switching network being an adiabatically charged switching network; (4) the regulating circuit is connected between the input terminal of the converter and an input port of the switching network, and either the switching network is a multi-phase switching network, the switching network and the regulating circuit are bidirectional, or the regulating circuit is multi-phase; (5) the switching network is connected between the regulating circuit and an additional regulating circuit; or (6) the regulating circuit is connected between the switching network and an additional switching network.

Embodiments of the invention include those in which the switching network includes a reconfigurable switching network and those in which the switching network includes a multi-phase switching network.

Other embodiments include those in which the regulating circuit includes a bidirectional regulating circuit those in which the regulating circuit includes a multi-phase regulating circuit, those in which the regulating circuit is bidirectional and includes a switch-mode power converter, those in which the regulating circuit is bi-directional regulating circuit and includes a resonant power converter, those in which the regulating circuit is connected to an output of the switching network, and those in which the regulating circuit is connected between the output terminal of the converter and the switching network, the switching network being an adiabatically charged switching network.

In other embodiments, the regulating circuit is connected between the output terminal of the converter and a switching network, and either the switching network is a multi-phase switching network, the switching network and the regulating circuit are bidirectional, or the regulating circuit is multi-phase.

In other embodiments, the regulating circuit is connected between the input terminal of the converter and an input port of the switching network, the switching network being an adiabatically charged switching network.

In yet other embodiments, the regulating circuit is connected between the input terminal of the converter and an input port of the switching network, and either the switching network is a multi-phase switching network, the switching network and the regulating circuit are bidirectional, or the regulating circuit is multi-phase.

Among the embodiments of the invention are those in which the switching network is connected between the regulating circuit and an additional regulating circuit, and those in which the regulating circuit is connected between the switching network and an additional switching network.

In additional embodiments, the switching network is configured as an AC switching network. Among these embodiments are those that also include a power-factor correction circuit connected to the AC switching network. Among these embodiments are those in which this power-factor correction circuit is connected between the AC switching network and the regulating circuit.

In another aspect, the invention features an apparatus including a converter having an input terminal and an output terminal. The converter includes a switching network having an input port and output port. This switching network includes charge-storage elements, and switching elements connected to the charge-storage elements. The switching elements are controllable to arrange the charge-storage elements into a selected configuration. In at least one configuration, the switching elements form a first group of charge-storage elements for discharging the charge-storage elements through the output port of the switching network. In another, the switching elements form a second group of charge-storage elements for charging the charge-storage elements through the input port of the switching network. The converter also includes a bi-directional regulating circuit connected between at least one of an input terminal of the converter and an input port of the switching network and an output terminal of the converter and an output port of the switching network.

In some embodiments, the switching network includes a multi-phase switching network.

Also included among the embodiments are those in which the bi-directional regulating circuit includes a buck/boost circuit and those in which the bi-directional regulating circuit includes a split-pi circuit.

In another aspect, the invention features a converter having an input terminal and an output terminal. The converter includes a switching network having an input port and output port, charge-storage elements, and switching elements connected to the charge-storage elements for arranging the charge-storage elements into one of a plurality of configurations. In one configuration, the switching elements form a first group of charge storage-elements for discharging the charge-storage elements through the output port of the switching network. In another configuration, the switching elements form a second group of charge-storage elements for charging the charge-storage elements through the input port of the switching network. The converter further includes a regulating circuit configured to provide a stepped-up voltage and connected between the output terminal of the converter and an output port of the switching network.

In yet another aspect, the invention features an apparatus having an input terminal and output terminal, and a switching network having an input port and output port, charge-storage elements, and switching elements connected to the charge-storage elements. The switching elements are controllable for causing the switching elements to be arranged in a plurality of configurations. In one configuration, the switching elements form a first group of charge-storage elements for discharging the charge-storage elements through the output port of the switching network. In another configuration the switching elements form a second group of charge-storage elements for charging the charge-storage elements through the input port of the switching network. The apparatus further includes a source regulating circuit connected between an input terminal of the converter and an input port of the switching network.

Some embodiments also include a load regulating circuit connected between an output terminal of the converter and an output port of the switching network.

In another aspect, the invention features a manufacture including multiple switching networks and regulating circuits having inputs and outputs that permit modular interconnections thereof for assembly of a DC-DC converter.

In some embodiments, at least one switching network includes a switched capacitor network. Among these are those in which the switched capacitor network includes an adiabatically charged switched capacitor network. These embodiments also include those in which the adiabatically charged switched capacitor network includes a cascade multiplier. In some of these embodiments, the cascade multiplier is driven by complementary clocked current sources.

In other embodiments, at least one regulating circuit includes a linear regulator.

Embodiments also include those in which the DC-DC converter includes series-connected switched capacitor networks, and those in which the DC-DC converter includes multiple regulating circuits that share a common switching network.

In another aspect, the invention features an apparatus for electric power conversion. Such an apparatus includes a converter having an input terminal and an output terminal. The converter includes a regulating circuit, and a switching network. The regulating circuit maintains an average DC current through an inductance thereof. The switching network, which has an input port and an output port, has charge-storage elements. Switching elements of the switching network connect to these charge-storage elements. The switching elements are controllable to switch between switch configurations. In one switch configuration, the switching elements form a first arrangement of charge-storage elements in which a charge-storage element is charged through a first port of the switching network and in another configuration, the switching elements form a second arrangement of charge-storage elements in which a charge-storage element is discharged through a second port of the switching network. The first and second ports are chosen from the input and output ports.

There are six converter configurations within the scope of the invention. In a first configuration, the regulating circuit is connected between the output terminal of the converter and the switching network is an adiabatically charged switching network. In a second configuration, the regulating circuit is connected between the output terminal of the converter and the switching network, and the converter satisfies one or more second-configuration properties to be defined below. In a third configuration, the regulating circuit is connected between the input terminal of the converter and an input port of the switching network, and the switching network is an adiabatically charged switching network. In a fourth configuration, the regulating circuit is connected between the input terminal of the converter and an input port of the switching network, and the converter satisfies one or more fourth-configuration properties to be described below. In a fifth configuration, the switching network is connected between the regulating circuit and an additional regulating circuit. Finally, in a sixth configuration, the regulating circuit is connected between the switching network and an additional switching network. The properties, one or more of which are satisfied in the second and fourth configurations, are as follows: the first property is that the switching network is a multi-phase switching network, the second property is that the switching network and the regulating circuit are bidirectional, and the third property is that the regulating circuit is multi-phase.

In some embodiments, the switching network comprises a reconfigurable switching network. In others, it comprises a multi-phase switching network.

Embodiments also include those in which the regulating circuit comprises a bidirectional regulating circuit. Among these are embodiments in which the regulating circuit comprises a switch-mode power converter, and those in which it comprises a resonant power converter.

Also among the embodiments are those in which the regulating circuit comprises a multi-phase regulating circuit, those in which the regulating circuit is configured to operate as a magnetic filter, and those in which the regulating circuit is connected to an output of the switching network.

In some embodiments, the converter is in the first configuration. In others, the converter is in the second configuration. In yet others, the converter is in the third configuration. Also included within the scope of the invention are embodiments in which the converter is in the fourth configuration, and embodiments in which the converter is in the sixth configuration.

In yet other embodiments, the converter is in the fifth configuration. Among these are the embodiments in which the additional regulating circuit of the fifth configuration is configured to operate as a magnetic filter. These can be implemented by using a buck converter as a regulator and making the duty cycle very long, so that the series inductor is virtually always connected. In the limiting case, the switch can be eliminated altogether.

Further embodiments include those in which the switching network is configured as an AC switching network.

Some embodiments feature a power-factor correction circuit connected to the AC switching network. Among these are embodiments in which the power-factor correction circuit is connected between the AC switching network and the regulating circuit.

In one aspect, the invention features an apparatus for processing electric power. Such an apparatus includes a power-converter having a path for power flow between a first power-converter terminal and a second power-converter terminal. During operation of the power-converter, the first power-converter terminal is maintained at a first voltage and the second power-converter terminal is maintained at a second voltage that is lower than the first voltage. The power-converter includes first and second regulating-circuits, and a switching network, all of which are disposed on the path. The switching network includes switches, a first charge-storage-element, and first and second switching-network-terminals. The first regulating-circuit includes a first magnetic-storage-element and a first-regulating-circuit terminal. The second regulating-circuit includes a second-regulating-circuit terminal. The power path includes the first-regulating-circuit terminal, the second-regulating-circuit terminal, the first switching-network-terminal, and the second switching-network-terminal. The first-regulating-circuit terminal is connected to the first switching-network-terminal and the second-regulating-circuit terminal is connected to the second switching-network-terminal. The switching network is configured to transition between a first switch-configuration and a second switch-configuration. When the switching network is in the first switch-configuration, charge accumulates in the first charge-storage-element at a first rate. Conversely, when the switching network is in the second switch configuration charge is depleted from the first charge-storage-element at a second rate. These two rates are constrained by the first magnetic-storage-element.

In some embodiments, the switching network further includes a second charge-storage-element. When the switching network is in the first switch-configuration, charge is depleted from the second charge-storage-element at a rate constrained by the first magnetic-storage-element. Conversely, when the switching network is in the second configuration, charge accumulates in the second charge-storage-element at a rate constrained by the first magnetic-storage-element. These rates can be equal or different.

In other embodiments, the second regulating-circuit includes a second magnetic-storage-element, and a switch connected to the magnetic-storage element, the switch being controllable to switch between at least two switching configurations.

Also included are embodiments in which the second regulating-circuit further includes a feedback loop for controlling operation of the switch in response to a measured output of the power converter.

In yet other embodiments, the first magnetic-storage-element includes a filter. In some of these embodiments, the filter has a resonant frequency.

Other embodiments include a third regulating-circuit, that is also connected to the switching network. Both the second and third regulating circuits have inductors. These inductors are coupled to each other. Another embodiment includes an inductor core that is shared by inductors in the second and third regulating circuits.

Also among the embodiments are those in which the first and second rates of charge transfer are equal.

In another aspect, the invention features a method for causing a power converter to process electric power. Such a method includes, on a power path for power flow between a first power-converter terminal and a second power-converter terminal, connecting a first-regulating-circuit terminal of a first regulating-circuit to a first switching-network-terminal of a first switching-network, and connecting a second-regulating-circuit terminal of the first regulating-circuit to a second switching-network-terminal of the first switching-network, using the second regulating-circuit, maintaining the first power-converter terminal at a first voltage, thereby maintaining the second power-converter terminal at a second voltage that is lower than the first voltage, using switches in the first switching-network, placing the first switching-network in a configuration for allowing charge to accumulate in the first charge-storage-element of the first switching-network, using energy stored in a magnetic field by a first magnetic-storage-element in the first regulating-circuit, constraining a rate of charge accumulation in a first charge-storage-element of the first switching-network, using the switches in the first switching-network, placing the first switching-network in a configuration for allowing charge to be depleted from the first charge-storage-element of the first switching-network, and, using energy stored by the first magnetic-storage-element in the first regulating-circuit, constraining a rate of charge depletion from the first charge-storage-element of the first switching-network.

Some practices include, while constraining a rate of charge depletion from the first charge-storage-element, constraining a rate of charge accumulation in a second charge-storage-element, and, while constraining a rate of charge accumulation into the first charge-storage-element, constraining a rate of charge depletion from the second charge-storage-element.

Yet other practices include controlling a switch connected to a magnetic-storage element of the second regulating-circuit in response to measured output of the power converter.

In some practices, the first magnetic-storage-element includes a filter. Among these, are practices of the invention in which the filter has a resonant frequency. An example of such a filter is an LC filter or an RLC filter.

Some practices involve a third regulating-circuit in addition to the two that are already present. The third regulating-circuit is connected to the switching network, and includes an inductor that is coupled to an inductor of the first regulating-circuit. In another embodiments, a third regulating-circuit connected to the switching network has an inductor that couples to an inductor in the first regulating-circuit with a common core.

Many kinds of switching network can be selected, including a reconfigurable switching-network, a multi-phase switching-network, a multi-phase series-parallel switching-network, a multi-phase multiple-stage switching network, a cascade multiplier, and a multiple stage switching network.

In addition, a variety of different regulating circuits can be used for at least one of the first and second regulating circuits. These include a bidirectional regulating-circuit, a multi-phase regulating-circuit, a switch-mode power converter, a resonant power converter, a buck converter, a boost converter, a buck/boost converter, a linear regulator, a Cuk converter, a fly-back converter, a forward converter, a half-bridge converter, a full-bridge converter, a magnetic-storage element, and a magnetic filter.

The fly-back converter can more specifically be a quasi-resonant fly-back converter, or an active-clamp fly-back converter, or an interleaved fly-back converter, or a two-switch fly-back converter. Likewise, the forward converter can be more specifically a multi-resonant forward converter, or an active-clamp forward converter, or an interleaved forward converter, or a two-switch forward converter. Lastly, the half-bridge converter can more specifically be an asymmetric half-bridge converter, or a multi-resonant half-bridge converter, or a LLC resonant half-bridge.

Some practices include configuring the switching network to be an AC switching network. These practices include those that also include controlling a power-factor of an output of the AC switching network, and those that also include connecting a power-factor correction circuit between the AC switching network and the first regulating-circuit.

Other practices also include varying switch configurations of the switching network at a frequency that is different from a frequency at which switching configuration of at least one of the first and second regulating-circuits is varied.

In another aspect, the invention features a non-transitory computer-readable medium that stores a data structure that is to be operated upon by a program executable on a computer system, wherein, when operated upon by such a program, the data structure causes at least a portion of a process for fabricating an integrated circuit that includes circuitry described by the data structure, wherein the circuitry described by the data structure includes a switching network that has been configured to be used with a power-converter having a path for power flow between a first power-converter terminal and a second power-converter terminal, wherein, during operation of the power-converter, the first power-converter terminal is maintained at a first voltage and the second power-converter terminal is maintained at a second voltage that is lower than the first voltage, wherein the power-converter comprises first and second regulating-circuits, and the switching network, all of which are disposed on the path, wherein the switching network comprises switches, and first and second switching-network-terminals, wherein the first regulating-circuit comprises a first magnetic-storage-element and a first-regulating-circuit terminal, wherein the second regulating-circuit comprises a second-regulating-circuit terminal, wherein the power path comprises the first-regulating-circuit terminal, the second-regulating-circuit terminal, the first switching-network-terminal, and the second switching-network-terminal, wherein the first-regulating-circuit terminal is to be connected to the first switching-network-terminal and the second-regulating-circuit terminal is to be connected to the second switching-network-terminal, wherein the switching network is configured to transition between a first switch-configuration and a second switch-configuration, wherein, when the switching network is in the first switch-configuration, charge accumulates in the first charge-storage-element at a first rate, wherein, when the switching network is in the second switch configuration charge is depleted from the first charge-storage-element at a second rate, and wherein the first rate and the second rate are constrained by the first magnetic-storage-element.

In one aspect, the invention features an apparatus for processing electric power. Such an apparatus includes a power-converter having a power path for power flow between first and second power-converter terminals maintained at corresponding first and second voltages during operation thereof. The second voltage is less than the first. A first regulating-circuit and a switching network are both on the power path. The switching network includes a first charge-storage-element, and first and second switching-network-terminals. The first regulating-circuit includes a first magnetic-storage-element and a first-regulating-circuit terminal. The power path includes the first-regulating-circuit terminal, the first switching-network-terminal, and the second switching-network-terminal with the first-regulating-circuit terminal being connected to the first switching-network-terminal. The switching network transitions between first and second switch-configurations. In the first charge accumulates in the first charge-storage-element at a first rate, and in the second switch configuration charge is depleted from the first charge-storage-element at a second rate. The first magnetic-storage-element constrains both of these rates. In some cases, the constraint is such that the rates are equal, whereas in others, the rates are different.

Some embodiments also include a second regulating-circuit disposed on the path. In these embodiments, the second regulating-circuit includes a second-regulating-circuit terminal that is also on the power path. This second-regulating-circuit terminal connects to the second switching-network-terminal.

In some embodiments, the switching network further includes a second charge-storage-element. Placing the switching network in the first switch-configuration depletes charge from the second charge-storage-element at a first rate. Placing the switching network in the second configuration accumulates charge in the second charge-storage-element at a second rate. The first magnetic-storage element constrains both of these rates.

Among the embodiments that have a second regulating-circuit are those in which the second regulating circuit includes a second magnetic-storage-element and a switch connected to the second magnetic-storage-element, the switch being controllable to switch between at least two switching configurations. Also among these embodiments are those in which the second regulating-circuit further includes a feedback loop for controlling operation of the switch in response to a measured output of the power converter.

In other embodiments, the first magnetic-storage-element includes a filter. Among these are embodiments in which the filter has a resonant frequency.

Among the embodiments that have two regulating circuits are those that have a third regulating circuit. In some of these embodiments, the third regulating-circuit connects to the switching network and has an inductor coupled to an inductor, and the second regulating-circuit includes an inductor that is coupled to the inductor of the third regulating-circuit. In others, the third regulating-circuit connects to the switching network and both the second and third regulating circuits include inductors that share the same inductor core. In embodiments that have coupled inductors, the inductors can be coupled such that the product of voltage and current at both inductors has the same sign or opposite signs.

The invention can be implemented with many kinds of switching networks. For example, in some embodiments, the switching network includes a reconfigurable switching network. As used herein, a reconfigurable switching network is one that has a set of switch configurations {α₁, α₂, . . . α_n} where n>2 and the switching network is able to transition between α_band α_nfor all m, n.

In others, it includes a multi-phase switching-network. In yet others, it includes a multi-phase multiple stage switching network, or a multiple stage switching network. Still other embodiments have switching networks that include a cascade multiplier.

The invention can also be implemented with many kinds of regulating circuit. These include bidirectional regulating-circuits, multi-phase regulating-circuits, switch-mode power converters, resonant power converters, a buck converter, a boost converter, a buck/boost converter, a linear regulator, a Cuk converter, a fly-back converter, a forward converter, a half-bridge converter, a full-bridge converter, a magnetic-storage element, and a magnetic filter.

In some embodiments, the switching network receives charge at an input thereof and outputs the charge at an output thereof. In these embodiments, transport of charge from the input to the output is carried out in more than one switching cycle.

Among the embodiments that feature a fly-back converter are those that include a quasi-resonant fly-back converter, an active-clamp fly-back converter, an interleaved fly-back converter, or a two-switch fly-back converter.

Among the embodiments that feature a forward converter are those that include a multi-resonant forward converter, an active-clamp forward converter, an interleaved forward converter, or a two-switch forward converter.

Among the embodiments that include a half-bridge converter are those that include an asymmetric half-bridge converter, a multi-resonant half-bridge converter, or a LLC resonant half-bridge.

The invention is not restricted to DC applications. For example, in some embodiments, the switching network is an AC switching network. These include embodiments with a power-factor correction circuit connected to the AC switching network. Among these are embodiments in which the power-factor correction circuit is between the AC switching network and the first regulating-circuit.

In some embodiments, the power-converter varies switch configurations of the switching network at a frequency that is different from a frequency at which switching configuration of at least one of the first and second regulating-circuits is varied.

In other embodiments, the switching network includes an asymmetric cascade multiplier having a plurality of DC nodes, each of which is available to deliver power at a voltage that is a multiple of the first voltage.

Yet other embodiments include a power-management integrated circuit into which the first regulating circuit is incorporated. In these embodiments, the power path includes a power-path section that extends out of the power-management integrated circuit and into the switching network.

Other embodiments include switches that have different physical areas.

Also among the embodiments are those in which the switch-widths of the switches are selected such that a time constant of charge transfer between charge-storage elements of the switching network is greater than or equal to a switching frequency at which the switching network changes state.

Yet other embodiments improve efficiency by having higher resistance switches. In these embodiments, the switching network is configured such that, at the switching-frequency of the switching network, increasing resistance of the switches reduces loss associated with current flowing within the switching network.

The various components of the apparatus need not share the same ground. In fact, one ground can float relative to the other.

As an example, in some embodiments, the first-regulating-circuit receives a first voltage difference and the second power-converter terminal outputs a second voltage difference. The first voltage difference is a difference between a first voltage and a second voltage that is less than the first voltage; the second voltage difference is a difference between a third voltage and a fourth voltage that is less than the third voltage. In these embodiments, a difference between the fourth voltage and the second voltage is non-zero. In other embodiments, the first-regulating-circuit receives a DC voltage difference, and the power converter receives an AC voltage difference. The DC voltage is a difference between a first voltage and a second voltage that is less than the first voltage; the AC voltage difference is a difference between a time-varying voltage and a constant voltage. A difference between the constant voltage and the second voltage is non-zero.

In another aspect, the invention features a method for causing a power converter to process electric power. Such a method includes, on a power path for power flow between a first power-converter terminal and a second power-converter terminal, connecting a first-regulating-circuit terminal of a first regulating-circuit to a first switching-network-terminal of a first switching-network, placing the first switching-network in a configuration for allowing charge to accumulate in the first charge-storage-element of the first switching-network, using energy stored in a magnetic field by a first magnetic-storage-element in the first regulating-circuit, constraining a rate of charge accumulation in a first charge-storage-element of the first switching-network, using the switches in the first switching-network, placing the first switching-network in a configuration for allowing charge to be depleted from the first charge-storage-element of the first switching-network, and, using energy stored by the first magnetic-storage-element in the first regulating-circuit, constraining a rate of charge depletion from the first charge-storage-element of the first switching-network.

Some practices further include connecting a second-regulating-circuit terminal of a second regulating-circuit to a second switching-network-terminal of the first switching-network, and using the second regulating-circuit, maintaining the first power-converter terminal at a first voltage, thereby maintaining the second power-converter terminal at a second voltage that is lower than the first voltage, using switches in the first switching-network.

Other practices include, while constraining a rate of charge depletion from the first charge-storage-element, constraining a rate of charge accumulation in a second charge-storage-element, and, while constraining a rate of charge accumulation into the first charge-storage-element, constraining a rate of charge depletion from the second charge-storage-element.

Yet other practices include controlling a switch connected to a magnetic-storage element of the second regulating-circuit in response to measured output of the power converter.

In some practices, the first magnetic-storage-element includes a filter. Among these are practices in which this filter has a resonant frequency.

Among the practices that use a second regulating circuit are those that include including a third regulating-circuit that is connected to the switching network. The third regulating-circuit includes an inductor, and the first regulating-circuit includes an inductor that is coupled to the inductor of the third regulating-circuit. The two inductors can be positively or negatively coupled.

Also among practices that use a second regulating circuit are those in which the second regulating circuit has an inductor core, and an inductor in a third regulating-circuit, which is connected to the switching network, shares this inductor core.

Some practices include constraining the rate of change so that the first rate and the second rate are equal. Others include constraining the rate of change so that the first rate and the second rate are unequal.

Practices of the invention contemplate a variety of switching networks. For example, practices of the invention include selecting the switching network to be reconfigurable switching-network, selecting it to be a multi-phase switching-network, selecting it to be a multi-phase series-parallel switching-network, selecting it to be a multi-phase multiple-stage switching network, selecting it to be a cascade multiplier, or selecting it to be a multiple stage switching network.

A variety of regulating circuits can be used in different practices. For example, practices of the invention include selecting a regulating circuit to be bidirectional, to be multi-phase, to be a switch-mode power converter, to be a resonant power converter, to be a magnetic-storage element, or to be a magnetic filter.

Other practices include selecting the switching network to be an AC switching network. Among these are practices that include controlling a power-factor of an output of the AC switching network. These include practices that include connecting a power-factor correction circuit between the AC switching network and the first regulating-circuit.

Yet other practices include varying switch configurations of the switching network at a frequency that is different from a frequency at which switching configuration of at least one of the first and second regulating-circuits is varied.

Practices that rely on a fly-back converter include those that rely on a quasi-resonant fly-back converter, an active-clamp fly-back converter, an interleaved fly-back converter, or a two-switch fly-back converter. Practices that rely on a forward converter include those that rely on a multi-resonant forward converter, an active-clamp forward converter, an interleaved forward converter, or a two-switch forward converter. Practices that rely on a half-bridge converter include those that rely on an asymmetric half-bridge converter, a multi-resonant half-bridge converter, or a LLC resonant half-bridge.

In another aspect, the invention features a non-transitory computer-readable medium that stores a data structure that is to be operated upon by a program executable on a computer system. When operated upon by such a program, the data structure causes at least a portion of a process for fabricating an integrated circuit. This integrated circuit includes circuitry described by the data structure. Such circuitry includes a switching network that has been configured to be used with a power-converter having a path for power flow between a first power-converter terminal and a second power-converter terminal. During the power-converter's operation of the power-converter, the first power-converter terminal is maintained at a first voltage and the second power-converter terminal is maintained at a second voltage that is lower than the first voltage. The power-converter includes a first regulating-circuit and the above-mentioned switching network, both of which are disposed on the path. The switching network includes switches, and first and second switching-network-terminals. Meanwhile, the first regulating-circuit includes a first magnetic-storage-element and a first-regulating-circuit terminal. The power path includes the first-regulating-circuit terminal, the first switching-network-terminal, and the second switching-network-terminal. The first-regulating-circuit terminal is to be connected to the first switching-network-terminal, and the switching network is configured to transition between first and second switch-configurations. When the switching network is in the first switch-configuration, charge accumulates in the first charge-storage-element at a first rate. When the switching network is in the second switch configuration, charge is depleted from the first charge-storage-element at a second rate. The first magnetic-storage element constrains these rates.

The invention also includes circuitry that is described by the foregoing data structure. Such circuitry includes a switching network having first and second switching terminals, and configured for disposition, along with first and second regulating circuits, at least one of which includes a magnetic storage element, on a power-flow path between first and second power converter terminals of a power converter, the first and second power converter terminals of which are maintained at corresponding first and second voltages, the second voltage being lower than the first voltage. The switching network is configured to transition between switch configurations during each of which an amount of charge in a charge-storage element in the power converter changes at a rate that is constrained by the magnetic storage element. The power path includes a first-regulating-circuit terminal associated with the first regulating circuit and connected to the first switching network terminal.

These and other features of the invention will be apparent from the following detailed description and the accompanying figures, in which:

DESCRIPTION OF THE FIGURES

FIG. 1A shows a known DC-DC converter with a separate regulating circuit and switching network;

FIG. 1B shows a bidirectional version of FIG. 1A;

FIGS. 2-4 show DC-DC converters with alternate configurations of regulating circuits and switching networks;

FIG. 5 shows a particular implementation of the power converter illustrated in FIG. 4;

FIGS. 6A and 6B show embodiments with multiple regulating circuits;

FIG. 7 shows an RC circuit;

FIG. 8 shows a model of a switched capacitor DC-DC converter;

FIGS. 9A and 9B show a series-parallel SC converter operating in charge phase and discharge phase, respectively;

FIG. 10 shows a series pumped symmetric cascade multiplier with diodes;

FIG. 11 shows a parallel pumped symmetric cascade multiplier with diodes;

FIG. 12 shows charge pump signals;

FIG. 13 shows a two-phase symmetric series pumped cascade multiplier with switches;

FIG. 14 shows a two-phase symmetric parallel pumped cascade multiplier with switches;

FIG. 15 shows four different cascade multipliers along with corresponding half-wave versions;

FIG. 16 shows output impedance of a switched capacitor converter as a function of frequency;

FIG. 17 shows a particular implementation of the DC-DC converter illustrated in FIG. 1B with a full-wave adiabatically charged switching network;

FIG. 18 shows the DC-DC converter illustrated in FIG. 17 during phase A;

FIG. 19 shows the DC-DC converter illustrated in FIG. 17 during phase B;

FIG. 20 shows various waveforms associated with a 4:1 adiabatically charged converter;

FIG. 21 shows adiabatic charging of series connected stages;

FIG. 22 shows a particular implementation of the power converter illustrated in FIG. 21;

FIG. 23 shows an AC voltage rectified using a reconfigurable switched capacitor stage;

FIG. 24 shows an AC-DC power converter architecture;

FIG. 25 shows a particular implementation of the AC-DC converter illustrated in FIG. 24;

FIG. 26 shows the AC-DC converter illustrated in FIG. 25 during the positive portion of the AC cycle;

FIG. 27 shows the AC-DC converter illustrated in FIG. 25 during the negative portion of the AC cycle;

FIG. 28 shows an AC-DC power converter architecture with power-factor correction;

FIGS. 29 and 30 show particular implementations of the DC-DC converter illustrated in

FIGS. 1A-1B;

FIGS. 31 and 32 show particular implementations of the DC-DC converter illustrated in FIG. 3;

FIGS. 33 and 34 show particular implementations of the DC-DC converter illustrated in FIG. 2;

FIGS. 35 and 36 show particular implementations of the DC-DC converter illustrated in FIG. 4; and

FIG. 37 shows an implementation of a DC-DC converter similar to that shown in FIG. 6B.

DETAILED DESCRIPTION

FIG. 1A shows a converter 10 having a switching network 12A connected to a voltage source 14 at an input end thereof. An input of a regulating circuit 16A is then connected to an output of the switching network 12A. A load 18A is then connected to an output of the regulating circuit 16A. Power flows between the voltage source 14 and the load 18A in the direction indicated by the arrows.

Embodiments described herein rely at least in part on the recognition that in a multi-stage DC-DC converter, the various constituent components can be made essentially modular and can be mixed and matched in a variety of different ways. These constituent components include switching networks and regulating circuits, the latter being made to function either as regulators or magnetic filters by simply varying the duty cycle. This modularity simplifies the assembly of such converters. As such, the configuration shown in FIG. 1A represents only one of multiple ways to configure one or more switching networks 12A with one or more regulating circuits 16A. FIG. 1B shows a bidirectional version of FIG. 1A, where power can flow along a power-flow path either from a voltage source 14 to a load 18A or from the load 18A to the voltage source 14, as indicated by the arrows.

There are two fundamental elements described in connection with the following embodiments: switching networks 12A, 12B and regulating circuits 16A, 16B. Assuming series connected elements of the same type are combined, there are a total of four basic building blocks. These are shown in FIGS. 1A-4. The embodiments disclosed herein include at least one of the four basic building blocks shown in FIGS. 1A-4. More complex converter can be realized by combining the fundamental building blocks. In general, a controller, not shown for clarity, will control and coordinate operation of the overall system.

Additional embodiments further contemplate the application of object-oriented programming concepts to the design of DC-DC converters by enabling switching networks 12A, 12B and regulating circuits 16A, 16B to be “instantiated” in a variety of different ways, so long as their inputs and outputs continue to match in a way that facilitates modular assembly of DC-DC converters having various properties.

In many embodiments, the switching network 12A is instantiated as a switched charge-storage network of charge-storage elements, such as capacitors. Among the more useful topologies of this kind of network are: Ladder, Dickson, Series-Parallel, Fibonacci, and Doubler, all of which can be adiabatically charged and configured into multi-phase networks. A switched charge-storage network is also known as a switched capacitor network when the charge-storage elements are capacitors. A particularly useful switched capacitor network is an adiabatically charged version of a full-wave cascade multiplier. However, diabatically charged versions can also be used.

During operation, charge periodically accumulates and is depleted from the charge-storage elements in a switched charge-storage network. As used herein, changing the charge on a capacitor adiabatically means causing an amount of charge stored in that capacitor to change by passing the charge through a non-capacitive element. A positive adiabatic change in charge on the capacitor is considered adiabatic charging while a negative adiabatic change in charge on the capacitor is considered adiabatic discharging. Examples of non-capacitive elements include inductors, magnetic-storage elements, such as magnetic filters, resistors, and combinations thereof.

In some cases, a capacitor can be charged adiabatically for part of the time and diabatically for the rest of the time. Such capacitors are considered to be adiabatically charged. Similarly, in some cases, a capacitor can be discharged adiabatically for part of the time and diabatically for the rest of the time. Such capacitors are considered to be adiabatically discharged.

Diabatic charging includes all charging that is not adiabatic and diabatic discharging includes all discharging that is not adiabatic.

As used herein, an adiabatically charged switching network is a switching network 12A having at least one capacitor that is both adiabatically charged and adiabatically discharged. A diabatically charged switching network is a switching network 12A that is not an adiabatically charged switching network.

The regulating circuit 16A can be instantiated by circuitry that plays a role in somehow constraining the electrical characteristics of the system in some desirable way. For example, such a circuit might constrain the characteristic to be at some value or range of values, or constrain it to change at some rate, or constraint it to change in some direction. A common example would be a regulator that constrains an output voltage or current to be at a particular value, or to be within some range of values. A buck converter, when combined with an appropriate feedback loop, would be an attractive candidate for such a role due to its high efficiency and speed. Such a converter is also advantageous because of its ability to seamlessly transition from constraining an output voltage to be some desired value to constraining a rate of charge transfer within a switching network 12A to be within some desired range, effectively functioning as a magnetic filter, by adjustment of its duty cycle.

Other suitable regulating circuits 16A include boost converters, buck/boost converters, fly-back converters, forward converters, half-bridge converters, full-bridge converters, Cuk converters, resonant converters, and linear regulators. The fly-back converter can be a quasi-resonant fly-back converter, an active-clamp fly-back converter, an interleaved fly-back converter, or a two-switch fly-back converter. Likewise, the forward converter can be a multi-resonant forward converter, an active-clamp forward converter, an interleaved forward converter, or a two-switch forward converter. The half-bridge converter can be an asymmetric half-bridge converter, a multi-resonant half-bridge converter, or a LLC resonant half-bridge.

In one embodiment, shown in FIG. 2, a voltage source 14 provides an input to a first switching network 12A, which is instantiated as a switched capacitor network. The output of the first switching network 12A is a lower voltage than the input voltage that is provided to a regulating circuit 16A (e.g. a buck, a boost, or a buck/boost converter). This regulating circuit 16A provides a regulated input voltage to a second switching network 12B, such as another switched capacitor network. A high-voltage output of this second switching network 12B is then applied to a load 18A.

An embodiment such as that shown in FIG. 2 can be configured to regulate the load 18A or to regulate the voltage source 14 depending on the direction of energy flow along the power-flow path.

In another embodiment, shown in FIG. 3, a low-voltage source 14 connects to an input of a regulating circuit 16A, the output of which is provided to an input of a switching network 12A to be boosted to a higher DC value. The output of the switching network is then provided to a load 18A.

An embodiment such as that shown in FIG. 3 can be used to regulate the voltage source 14 or the load 18A depending on the direction of energy flow along the power-flow path.

Referring now to FIG. 4, another embodiment of a converter 100 includes a first regulating circuit 16A connected to an input 102 thereof and a second regulating circuit 16B connected to an output 104 thereof. Between the first and second regulating circuits 16A, 16B is a switching network 12A having an input 202 and an output 204. The switching network 12A includes charge-storage elements 210 interconnected by switches 212. These charge-storage elements 210 are divided into first and second groups 206, 208. As discussed above, either one of the regulating circuits 16A, 16B can be a buck converter, which can be either configured to control a voltage or to function as a magnetic filter, a boost converter, a buck/boost converter, a fly-back converter, a Cuk converter, a resonant converter, or a linear regulator. The regulating circuits 16A, 16B can be operated at a duty cycle required to achieve a desired result. For example, in the case of a buck converter, the duty cycle can be adjusted so that the buck converter's main switch maintains an indefinitely extended connection to its magnetic-storage element while its accompanying synchronous rectifier remain open indefinitely. Alternatively, one of the two regulating circuits 16A, 16B can be replaced by a magnetic filter, thus avoiding the need for additional switches. Such a magnetic filter includes a magnetic-storage element, such as an inductor, that resists rapid changes in current and thus promotes adiabatic charging of capacitors in the switching network 12A.

In some embodiments, the switching network 12A can be a bidirectional switched capacitor network such as that shown in FIG. 5. The switched capacitor network in FIG. 5 features a first capacitor 20 and a second capacitor 22 in parallel. A first switch 24 selectively connects one of the first and second capacitors 20, 22 to a first regulating circuit 16A, and a second switch 26 selectively connects one of the first and second capacitors 20, 22 to a second regulating circuit 16B. Like the regulators shown in FIG. 4, the first and second regulating circuits 16A, 16B can be operated at variable duty cycles. Alternatively, one of the regulating circuits 16A, 16B can be replaced by a magnetic filter having an inductor that resists rapid changes in current and thus promotes adiabatic charging of capacitors within the switching network 12A. Both the first and second switches 24, 26 can be operated at high frequency, thus facilitating the adiabatic charging and discharging of the first and second capacitors 20, 22.

The particular embodiment shown in FIG. 5 has a two-phase switching network 12A. However, other types of switching networks 12A can be used instead.

In yet another embodiment, shown in FIG. 6A, first, second, and third regulating circuits 16A, 16B, 16C, which could be incorporated into one or more separate power management ICs, are provided at an output of a first switching network 12A for driving first, second, and third loads 18A, 18B, 18C. For the third load 18C, a second switching network 12B is provided between the third load 18C and the third regulating circuit 16C thus creating a pathway similar to that shown in FIG. 2. Thus, FIG. 6A provides an example of how the modular construction of regulating circuits and switching networks facilitates the ability to mix and match components to provide flexibility in DC-DC converter construction.

Additional flexibility can be had by coupling components that are in different modules. For example, in FIG. 6B, the configuration shown in FIG. 6A has been reversed: first, second, and third regulating circuits 16A, 16B, 16C in FIG. 6A are replaced with first, second, and third switching networks 12A, 12B, 12C in FIG. 6B; and first and second switching networks 12A, 12B in FIG. 6A are replaced with fourth and third regulating circuits 16D, 16C in FIG. 6B. However, the first and second loads 18A, 18B in FIG. 6A have been consolidated into a first load 18A and into first and second regulating circuits 16A, 16B, in the form of magnetic filters, that have been added to constrain charge transfer within the first and second switching networks 12A, 12B. The first and second regulating circuits 16A, 16B are implemented by buck converters with appropriately selected duty cycles. In FIG. 6B, the first and second regulating circuits 16A, 16B have an inductor that shares the same core, thus coupling them together. This provides a way to save space in the circuit's overall footprint.

A switched capacitor (SC) DC-DC power converter includes a network of switches and capacitors. By cycling the network through different topological states using these switches, one can transfer energy from an input to an output of the SC network. Some converters, known as “charge pumps,” can be used to produce high voltages in FLASH and other reprogrammable memories.

FIG. 7 shows a capacitor C initially charged to some value V_C(0). At t=0 the switch S is closed. At that instant, a brief surge of current flows as the capacitor C charges to its final value of V_in. The rate of charging can be described by a time constant τ=RC, which indicates the time it takes the voltage to either rise or fall to within 1/e of its final value. The exact capacitor voltage v_c(t) and current i_c(t) are given by the following equations:

v_c(t)=v_c(0)+[V_in−v_c(0)](1−e^−t/RC), (1.1)

and

$\begin{matrix} i_{c} (t) = C \frac{{dv}_{c}}{dt} = \frac{V_{in} - v_{c} (0)}{R} e^{- t / RC} . & (1.2) \end{matrix}$

The energy loss incurred while charging the capacitor can be found by calculating the energy dissipated in resistor R, which is

E_loss(t)=∫_t=0^∞i_R(t)×v_R(t)dt=∫_t=0^∞[i_c(t)]²Rdt. (1.3)

The equation can be further simplified by substituting the expression for i_c(t) from equation (1.2) into equation (1.3). Evaluating the integral then yields

E_loss(t)=½[V_in−v_c(0)]²C[1−e^−2t/RC].

If the transients are allowed to settle (i.e. t→∞), the total energy loss incurred in charging the capacitor is independent of its resistance R. In that case, the amount of energy loss is equal to

E_loss(∞)=½CΔv_c²

A switched capacitor converter can be modeled as an ideal transformer, as shown in FIG. 8, with a finite output resistance R_othat accounts for the power loss incurred in charging or discharging of the energy transfer capacitors, as shown in FIG. 8. This loss is typically dissipated in the ON resistance of the MOSFETs and equivalent series resistance of the capacitors.

The output voltage of the switched capacitor converter is given by

$V_{o} = V_{in} \frac{N_{2}}{N_{1}} - I_{o} R_{o} .$

There are two limiting cases where the operation of switched capacitor converters can be simplified and R_oeasily found. These are referred to as the “slow-switching limit” and the “fast-switching limit.”

In the fast-switching limit (τ>>T_sw), the charging and discharging currents are approximately constant, resulting in a triangular AC ripple on the capacitors. Hence, R_ois sensitive to the series resistance of the MOSFETs and capacitors, but is not a function of the operating frequency. In this case, R_oof the converter operating in the fast-switching limit is a function of parasitic resistance.

In the slow-switching limit, the switching period T_swis much longer than the RC time constant τ of the energy transfer capacitors. Under this condition, there is systemic energy loss irrespective of the resistance of the capacitors and switches. This systemic energy loss arises in part because the root mean square (RMS) of the charging and discharging current is a function of the RC time constant. If the effective resistance R_effof the charging path is reduced (i.e. reduced RC), the RMS current increases and it so happens that the total charging energy loss (E_loss=I_RMS²R_eff=½C×ΔV_C2) is independent of R_eff. One solution to minimize this energy loss is to increase the size of the pump capacitors in the switched capacitor network.

It is desirable for a switched capacitor network to have a common ground, large transformation ratio, low switch stress, low DC capacitor voltage, and low output resistance. Among the more useful topologies are: Ladder, Dickson, Series-Parallel, Fibonacci, and Doubler.

One useful converter is a series-parallel switched capacitor converter. FIGS. 9A and 9B show a 2:1 series-parallel switched capacitor converter operating in charge phase and in discharge phase, respectively. During the charge phase, the capacitors are in series. In the discharge phase, the capacitors are in parallel. In its charge phase, capacitor voltages v_C1and v_C2add up to V₁while in its discharge phase, v_C1and v_C2equal V₂, which means that V₂=V_1/2.

Other useful topologies are cascade multiplier topologies, as shown in FIGS. 10 and 11. In both charge pumps, a source is located at V₁and a load is located at V₂. In these types of charge pumps, packets of charge are pumped along a diode chain as the coupling capacitors are successively charged and discharged. As shown in FIG. 12, clock signals v_clkand v_clk with amplitude v_pumpare 180 degrees out of phase. The coupling capacitors can either be pumped in series or in parallel.

It takes n clock cycles for the initial charge to reach the output. The charge on the final pump capacitor is n times larger than the charge on the initial pump capacitor and thus V₂for the converters is V₁+(n−1)×v_pumpin both pumping configurations.

Although the foregoing topologies are suitable for stepping up voltage, they can also be used to step down voltage by switching the location of the source and the load. In such cases, the diodes can be replaced with controlled switches such as MOSFETs and BJTs.

The foregoing cascade multipliers are half-wave multipliers in which charge is transferred during one phase of the of the clock signal. This causes a discontinuous input current. Both of these cascade multipliers can be converted into full-wave multipliers by connecting two half-wave multipliers in parallel and running the half-wave multipliers 180 degrees out of phase. FIG. 13 shows a full-wave symmetric series pumped cascade multiplier version while FIG. 14 shows a full-wave symmetric parallel pumped cascade multiplier version. Unlike the diodes in the half-multiplier, the switches in FIG. 13 and FIG. 14 are bidirectional. As a result, in both of these cascade multipliers, power can flow either from the source to the load or from the load to the source. Asymmetric multipliers can also be converted into full-wave multipliers

FIG. 15 shows four different step-down versions of full-wave multipliers along with their corresponding half-wave versions. Furthermore, it is possible to combine N phases in parallel and run them 180 degrees/N out of phase to reduce output voltage ripple and increase output power handling capability. The asymmetric multipliers have a special property: they contain DC nodes that are at voltage levels that are multiples of V₂. These DC nodes can serve as tap points for delivering or drawing power. They also provide convenient locations at which to reference V₁. This permits one to separate the grounds.

The basic building blocks in the modular architecture shown FIGS. 1A-4 can either be connected as independent entities or coupled entities. In the situation where switching networks and regulating circuits are tightly coupled, it is possible to prevent and/or reduce the systemic energy loss mechanism of the switching networks through adiabatic charging. This generally includes using the regulating circuit to control the charging and discharging of the capacitors in the switching network. Furthermore, the output voltage of the regulating circuit and thus the total converter can be regulated in response to external stimuli. One approach to regulating the output voltage is by controlling the average DC current in a magnetic-storage element, such as that found in a magnetic filter.

A desirable feature of the regulating circuit is to constrain the root mean square (RMS) current through the capacitors in the switching network to be below some limit. A regulating circuit achieves such a constraint by using either resistive or magnetic-storage elements. Unfortunately, resistive elements would consume power so their use is less desirable. Therefore, embodiments described herein rely on a magnetic-storage element with optional switches in the regulating circuit. The regulating circuit limits the RMS current by forcing the capacitor current through the magnetic-storage element in the regulating circuit that has an average DC current. In those regulating circuits that include switches, the switches are operated so as to maintain an average DC current through the magnetic-storage element. This can be achieved by varying the duty cycle of a switch in series with the magnetic-storage element. In one embodiment, the duty cycle approaches zero so that at least one switch is effectively always on. In the limiting case, at least one switch can be eliminated altogether.

The regulating circuit may limit both the RMS charging current and the RMS discharging current of at least one capacitor in the switching network. One single regulating circuit may limit the current in or out of the switching network by sinking and/or sourcing current. Therefore, there are four fundamental configurations, which are shown in FIGS. 1A-4. Assuming power flows from the source to load then, in FIG. 1A, the regulating circuit 16A may sink both the charging and discharging current of the switching network 12A. In FIG. 3, the regulating circuit 16A may source both the charging and discharging current of the switching network 12A. In FIG. 4, the regulating circuit 16A may source the charging current of the switching network 12A and the regulating circuit 16B may sink the discharging current of the same switching network 12A and vice-versa. In FIG. 2, the regulating circuit 16A may source both the charging and discharging current of the switching network 12B while also sinking both the charging and discharging current of the switching network 12A. Furthermore, if both the switching networks 12A, 12B and the regulating circuits 16A, 16B allow power to flow in both directions then bidirectional power flow is possible (source to load and load to source).

One embodiment relies on at least partially adiabatically charging full-wave cascade multipliers. A particularly preferred switching network, because of its superior fast-switching limit impedance, the ease with which it can be scaled up in voltage, and its low switch stress, is the cascade multiplier.

In cascade multipliers, the coupling capacitors are typically pumped with a clocked voltage source v_clk& v_clk. However, if the coupling capacitors are pumped with a clocked current source i_clk& i_clk instead, then the RMS charging and discharging current in the coupling capacitor may be limited. In this case, the capacitors are at least partially charged adiabatically thus lowering, if not eliminating, the ½C×ΔV_c²loss that is associated with a switched capacitor converter when operated in the slow-switching limit. This has the effect of lowering the output impedance to the fast-switching limit impedance. As shown by the black dotted line in FIG. 16, which depicts adiabatic operation, under full adiabatic charging, the output impedance would no longer be a function of switching frequency.

With all else being equal, an adiabatically charged switched capacitor converter can operate at a much lower switching frequency than a conventionally charged switched capacitor converter, but at higher efficiency. Conversely, an adiabatically charged switched capacitor converter can operate at the same frequency and with the same efficiency as a conventionally charged switched capacitor converter, but with much smaller coupling capacitors, for example, between four and ten times smaller.

FIG. 17 shows a step-down converter consistent with the architecture shown in FIG. 1B. In this embodiment, the switching network 12A is adiabatically charged using the regulating circuit 16A. The clocked current sources i_clk& i_clk are emulated by four switches and the regulating circuit 16A. The output capacitor C_Ohas also been removed so as to allow V_Xto swing. In this example, the regulating circuit 16A is a boost converter that behaves as constant source with a small AC ripple. Any power converter that has a non-capacitive input impedance at the frequency of operation would have allowed adiabatic operation. Although switch-mode power converters are attractive candidates due to their high efficiency, linear regulators are also practical.

In operation, the act of closing switches labeled “1” charges the capacitors C₄, C₅, and C₆while discharging the capacitors C₁, C₂, and C₃. Similarly, the act of closing switches labeled “2” has the complementary effect. The first topological state (phase A) is shown in FIG. 18, where all switches labeled “1” are closed and all switches labeled “2” are opened. Similarly, the second topological state (phase B) is shown in FIG. 19, where all switches labeled “2” are closed and all switches labeled “1” are opened.

In this embodiment, the regulating circuit 16A limits the RMS charging and discharging current of each capacitor. For example, the capacitor C₃is discharged through the magnetic filtering element in the regulating circuit 16A during phase A, while the capacitor C₃is charged through the magnetic filtering element in the regulating circuit 16A during phase B, clearly demonstrating the adiabatic concept. Furthermore, all of the active components are implemented with switches so the converter can process power in both directions.

A few representative node voltages and currents are shown in FIG. 20. There is a slight amount of distortion on the rising and falling edges of the two illustrated currents (I_P1and I_P2), but for the most part, the currents resemble two clocks 180 degrees out of phase. In general, adiabatic charging occurs in cascade multipliers only if at least one end of a switch stack is not loaded with a large capacitance, as is the case in this embodiment, where the V_Xnode is only loaded down by the regulating circuit 16A.

In operation, different amounts of current will flow through different switches. It is therefore useful to size the switches in a manner appropriate to the currents that will be flowing through them. For example, in FIG. 17, the switches that are connected to the nodes maintained at V_P1and V_P2carry more current then the other switches. If one were to make all switches the same area, then the remaining switches would be far bigger than necessary. By making the other switches smaller than those connected to the nodes at V_P1and V_P2, one avoids having unnecessarily large switches. Since each switch consumes a portion of the circuit, one can then make the entire circuit physically smaller.

An additional advantage is that capacitive loss increases as the switch area increases. Thus, customizing the switch's area to the current that it carries during operation yields a dual benefit. It not only reduces the overall size of the circuit's footprint, it also has the effect of reducing capacitive loss.

The switches shown in FIG. 17 will transition between states at some switching frequency. To reduce loss, it is desirable that the switching network 12A constrain the RMS current through the switches at that switching frequency. One way to constrain the RMS current is to correctly choose the resistances of the switches. In particular, the resistances should be high enough so that the RC time constant of the charge transfer between the capacitors is similar to, or longer than, the switching frequency. As can be seen in FIG. 16, by controlling the width “W” of the switches and hence their resistance and their size, the switching network 12A can be forced into the fast-switching limit region.

Unfortunately, by using the resistance of the switches to constrain the RMS current, resistive power losses increase and the overall efficiency decreases. The regulating circuit 16A, however, allows us to reduce the resistance of the switches while still operating adiabatically. Therefore, the switches can be optimally sized for the highest efficiency without worrying about constraining the RMS current since it is handled by the regulating circuit 16A (or optionally a magnetic filter). The optimal size for each switch is chosen by balancing the resistive and capacitive losses in each switch at a given switching frequency and at a given current.

The modular architecture with the basic building blocks shown in FIGS. 1A-4 may be expanded to cover a wider range of applications, such as high-voltage DC, AC-DC, buck-boost, and multiple output voltages. Each of these applications includes separating the transformation, regulation, and possibly magnetic filtering functions. Extension of the architecture can also incorporate adiabatically charged switched capacitor converters.

In many switched capacitor converters, the number of capacitors and switches increases linearly with the transformation ratio. Thus, a large number of capacitors and switches are required if the transformation ratio is large. Alternatively, a large transformation ratio can be achieved by connecting numerous low gain stages in series as depicted in FIG. 21. The transformation ratio of the total switch capacitor stack (V_in/V_x) is as follows:

$\begin{matrix} \frac{V_{in}}{V_{x}} = N_{1} \times N_{2} \dots N_{n} . & (2.1) \end{matrix}$

The main disadvantage of the series stacked configuration is that the voltage stresses on the front stages are much higher than those of the rear stages. This will normally require stages with different voltage ratings and sizes. However, the transformation ratio can be easily changed by bypassing one or more stages.

Adiabatic charging of a preceding series-connected switching network only occurs if the following switching network controls the charging and discharging current of the preceding stage. Thus, it is preferable to use full-wave switched capacitor converters in the front stages or to use switched capacitor stages such as the single-phase series-parallel switched capacitor converters with magnetic filters.

FIG. 22 shows a converter with a first switching network 12A connected in series with a second switching network 12D consistent with the architecture shown in FIG. 21. Both the first and second switching networks 12A, 12D are two-phase cascade multipliers. In operation, switches labeled “1” and “2” are always in complementary states and switches labeled “7” and “8” are always in complementary states. Thus, in a first switched-state, all switches labeled “1” are open and all switches labeled “2” are closed. In a second switched-state, all switches labeled “1” are closed and all switches labeled “2” are opened. In this embodiment, closing switches 1 charges capacitors C₁, C₂, C₃, while discharging capacitors C₄, C₅, C₆and closing switches 2 has the complementary effect. Also, closing switches 7 charges capacitors C₇, C₈, C₉, while discharging capacitors C₁₀, C₁₁, C₁₂and closing switches 8 has the complementary effect.

The power converter provides a total step-down of 32:1, assuming the first regulating circuit 16A is a buck converter with a nominal step-down ratio of 2:1. Furthermore, if the input voltage is 32 V and the output voltage is 1 V, then the switches in the first switching network 12A will need to block 8 volts while the switches in the second switching network 12D will need to block 2 volts.

The modular architecture with the basic building blocks shown in FIGS. 1A-4 may be configured to handle an AC input voltage as well. One of the main attributes of switched capacitor converters is their ability to operate efficiency over a large input range by reconfiguring the switched capacitor network. If the AC wall voltage (i.e. 60 Hz & 120 V_RMS) can be thought of as a slow moving DC voltage, then a front-end switched capacitor stage 13A, also known as an AC switching network, should be able to unfold the time-varying input voltage into a relatively stable DC voltage.

A diagram of a 120 VRms AC waveform over a single 60 Hz cycle overlaid with the unfolded DC voltage is shown in FIG. 23. The AC switching network 13A has different configurations (1/3, 1/2, 1/1) at its disposal along with an inverting stage. It was also designed to keep the DC voltage under 60 V. Once the AC voltage is unfolded, it is the job of a regulating circuit 16A, shown in FIG. 24, to produce a final output voltage. It may also be necessary to place another switching network between the AC switching network 13A and the regulating circuit 16A to further condition the voltage. If this is the case, then the caveats for series-connected stages hold true since the AC switching network 13A is a special purpose switching network. Some form of magnetic or electric isolation is also common in AC-DC converters for safety reasons. Hence, in FIG. 24, voltages: V_AC, V_DC, and V_Oare purposely defined as being agnostic to a common ground.

FIG. 25 shows an AC-DC converter corresponding to the architecture shown in FIG. 24. In this embodiment, the AC switching network 13A is a synchronous AC bridge rectifier followed by a reconfigurable two-phase step-down cascade multiplier with three distinct conversion ratios (1/3, 1/2, 1/1) while the regulating circuit 16A is a synchronous buck converter. In operation, switches labeled “7” and “8” are always in complementary states. During the positive portion of the AC cycle (0 to π radians) all switches labeled “7” are closed while all switches labeled “8” are opened as shown in FIG. 26. Similarly, during the negative portion of the AC cycle (π to 2π radians) all switches labeled “8” are closed while all switches labeled “7” are opened as shown in FIG. 27.

In addition to the inverting function provided by switches 7 and 8, switches 1A-1E and switches 2A-2E may be selectively opened and closed as shown in Table 1 to provide three distinct conversion ratios of: 1/3, 1/2, and 1.

TABLE 1

V₂/V₁
1A
1B
1C
1D
1E
2A
2B
2C
2D
2E

1/3
CLK
CLK
CLK
CLK
CLK
CLKB
CLKB
CLKB
CLKB
CLKB

1/2
CLKB
CLK
CLK
CLK
CLK
CLK
CLKB
CLKB
CLKB
CLKB

1/1
ON
ON
ON
OFF
OFF
ON
ON
ON
OFF
OFF

The AC switching network 13A is provided with a digital clock signal CLK. A second signal CLKB is also generated, which may simply be the complement of CLK (i.e., is high when CLK is low and low when CLK is high), or which may be generated as a non-overlapping complement. With a switching pattern set in accordance with the first row of Table 1, the AC switching network 13A provides a step-down ratio of one-third (⅓). With a switching pattern set in accordance with the second row of Table 1, the AC switching network 13A provides a step-down ratio of one-half (½). With a switching pattern set in accordance with the first row of Table 1, the AC switching network 13A provides a step-down ratio of one.

Most power supplies attached to the wall meet some power factor specification. Power factor is a dimensionless number between 0 and 1 that defines a ratio of the real power flowing to apparent power. A common way to control the harmonic current and thus boost the power factor is by using an active power factor corrector, as shown in FIG. 28. A power-factor correction circuit 17A causes the input current to be in phase with the line voltage, thus causing reactive power consumption to be zero.

FIGS. 29-36 show specific implementations of power converters that conform to the architectural diagrams shown in FIGS. 1A-4. In each implementation, a regulating circuit or multiple regulating circuits, which may include magnetic filters, may limit both the RMS charging current and the RMS discharging current of at least one capacitor in each switching network so all of these switching networks are adiabatically charged switching networks. However, if decoupling capacitors 9A or 9B are present, then the ability of the regulating circuit to limit the RMS charging and discharging current may be diminished. Capacitors 9A and 9B are optional and to keep the output voltage fairly constant, a capacitor C_Ois used. All of the stages share a common ground. However, this need not be case. For example, if a regulating circuit 16A is implemented as a fly-back converter, then the ground can be separated easily. Even a switching network 12A can have separate grounds through capacitive isolation. Furthermore, for simplicity, the switching network in each implementation has a single conversion ratio. However, reconfigurable switching networks that provide power conversion at multiple distinct conversion ratios may be used instead.

In operation, switches labeled “1” and “2” are always in complementary states. Thus, in a first switched-state, all switches labeled “1” are open and all switches labeled “2” are closed. In a second switched-state, all switches labeled “1” are closed and all switches labeled “2” are opened. Similarly, switches labeled “3” and “4” are in complementary states, switches labeled “5” and “6” are in complementary states, and switches labeled “7” and “8” are in complementary states. Typically, the regulating circuits operate at higher switching frequencies than the switching networks. However, there is no requirement on the switching frequencies between and amongst the switching networks and regulating circuits.

FIG. 29 shows a step-up converter corresponding to the architecture shown in FIG. 1A. In this embodiment, the switching network 12A is a two-phase step-up cascade multiplier with a conversion ratio of 1:3 while the regulating circuit 16A is a two-phase boost converter. In operation, closing switches 1 and opening switches 2 charges capacitors C₃and C₄while discharging capacitors C₁and C₂. Conversely, opening switches 1 and closing switches 2 charges the capacitors C₁and C₂while discharging the capacitors C₃and C₄.

FIG. 30 shows a bidirectional step-down converter corresponding to the architecture shown in FIG. 1B. In this embodiment, the switching network 12A is a two-phase step-down cascade multiplier with a conversion ratio of 4:1 while the regulating circuit 16A is a synchronous buck converter. In operation, closing switches 1 and opening switches 2 charges capacitors C₁, C₂, and C₃while discharging capacitors C₄, C₅, and C₆. Conversely, opening switches 1 and closing switches 2 charges the capacitors C₄, C₅, and C₆while discharging the capacitors C₁, C₂, and C₃. All of the active components are implemented with switches so the converter can process power in both directions.

FIG. 31 shows a step-up converter consistent with the architecture shown in FIG. 3. In this embodiment, the regulating circuit 16A is a boost converter while the switching network 12A is a two-phase step-up series-parallel SC converter with a conversion ratio of 1:2. In operation, closing switches 1 charges a capacitor C₂while discharging a capacitor C₁. Closing switches 2 has the complementary effect.

FIG. 32 shows a bidirectional up-down converter consistent with the architecture shown in FIG. 3. In this embodiment, the regulating circuit 16A is a synchronous four switch buck-boost converter while the switching network 12A is a two-phase step-up cascade multiplier with a conversion ratio of 1:4. In operation, closing switches 1 charges capacitors C₄, C₅, and C₆while discharging capacitors C₁, C₂, and C₃. Closing switches 2 has the complementary effect. All of the active components are implemented with switches so the converter can process power in both directions.

FIG. 33 shows an inverting up-down converter consistent with the architecture shown in FIG. 2. In this embodiment, the first switching network 12A is a step-down series-parallel SC converter with a conversion ratio of 2:1; the first regulating circuit 16A is a buck/boost converter; and the second switching network 12B is a step-up series-parallel SC converter with a conversion ratio of 1:2. In operation, closing switches 1 charges a capacitor C₁while closing switches 2 discharges the capacitor C₁. Similarly, closing switches 7 discharges a capacitor C₂while closing switches 8 charges the capacitor C₂.

FIG. 34 shows a bidirectional inverting up-down converter consistent with the architecture shown in FIG. 2. In this embodiment, the first switching network 12A is a two-phase step-down series-parallel SC converter with a conversion ratio of 2:1; the first regulating circuit 16A is a synchronous buck/boost converter; and the second switching network 12B is a two-phase step-up series-parallel SC converter with a conversion ratio of 1:2. In operation, closing switches 1 charges a capacitor C₁while discharging a capacitor C₂. Closing switches 2 has the complementary effect. Similarly, closing switches 7 charges a capacitor C₄while discharging a capacitor C₃. Closing switches 8 has the complementary effect. All of the active components are implemented with switches so the converter can process power in both directions.

FIG. 35 shows an up-down converter consistent with the block diagram shown in FIG. 4. In this embodiment, the first regulating circuit 16A is a boost converter; the first switching network 12A is a two-phase step-up series-parallel SC converter with a conversion ratio of 1:2; and the second regulating circuit 16B is a boost converter. In operation, closing switches 1 charges capacitors C₁and C₂while simultaneously discharging capacitors C₃and C₄. Closing switches 2 has the complementary effect.

FIG. 36 shows a bidirectional up-down converter consistent with the block diagram shown in FIG. 4. In this embodiment, the first regulating circuit 16A is a synchronous boost converter; the first switching network 12A is a two-phase fractional step-down series-parallel SC converter with a conversion ratio of 3:2; and the second regulating circuit 16B is a synchronous buck converter. In operation, closing switches 1 charges capacitors C₃and C₄while simultaneously discharging capacitors C₁and C₂. Closing switches 2 has the complementary effect. All of the active components are implemented with switches so the converter can process power in both directions. Adjusting the duty cycle of the second regulating circuit 16B so that switch 6 remains closed for extended periods allows an inductor L₂to promote adiabatic charge transfer between capacitors in the first switching network 12A. In such an embodiment, the switches 5, 6 can be dispensed with, thus reducing the overall chip area required to implement the second regulating circuit 16B.

FIG. 37 shows a step-down converter that conforms substantially to the architecture introduced by FIG. 6B. In this embodiment, a fourth regulating circuit 16D has coupled inductors L₁, L₂. The fourth regulating circuit 16D regulates first and second switching networks 12A, 12B in parallel that operate 90° out of phase. The task of constraining charge transfer among the four capacitors C₀of the first and second switching network 12A, 12B is shared by first and second regulating circuits 16A, 16B that also share coupled inductors L₃, L₄. If the coupling factor of the coupled inductors L₃, L₄is set properly, the ripple current through these inductors can be reduced. Thus, FIG. 37 illustrates the possibility of coupled inductors L₁, L₂within one component, namely the fourth regulating circuit 16D, and the possibility, already alluded to in FIG. 6B, of coupled inductors L₃, L₄across separate components, namely the first and second regulating circuits 16A, 16B.

It should be understood that the topology of the regulating circuit can be any type of power converter with the ability to regulate the output voltage, including, but without limitation, synchronous buck, three-level synchronous buck, SEPIC, magnetic filters, and soft switched or resonant converters. Similarly, the switching networks can be realized with a variety of switched capacitor topologies, depending on desired voltage transformation and permitted switch voltage.

In some implementations, a computer accessible storage medium includes a database representative of one or more components of the converter. For example, the database may include data representative of a switching network that has been optimized to promote low-loss operation of a charge pump.

Generally speaking, a computer accessible storage medium may include any non-transitory storage media accessible by a computer during use to provide instructions and/or data to the computer. For example, a computer accessible storage medium may include storage media such as magnetic or optical disks and semiconductor memories.

Generally, a database representative of the system may be a database or other data structure that can be read by a program and used, directly or indirectly, to fabricate the hardware comprising the system. For example, the database may be a behavioral-level description or register-transfer level (RTL) description of the hardware functionality in a high level design language (HDL) such as Verilog or VHDL. The description may be read by a synthesis tool that may synthesize the description to produce a netlist comprising a list of gates from a synthesis library. The netlist comprises a set of gates that also represent the functionality of the hardware comprising the system. The netlist may then be placed and routed to produce a data set describing geometric shapes to be applied to masks. The masks may then be used in various semiconductor fabrication steps to produce a semiconductor circuit or circuits corresponding to the system. In other examples, alternatively, the database may itself be the netlist (with or without the synthesis library) or the data set.

Having described one or more preferred embodiments, it will be apparent to those of ordinary skill in the art that other embodiments incorporating these circuits, techniques and concepts may be used. Accordingly, it is submitted that the scope of the patent should not be limited to the described embodiments, but rather, should be limited only by the spirit and scope of the appended claims.

Claims

1. An apparatus comprising: a power converter comprising an input port and an output port and a controller to implement a deadtime interval;wherein, during operation of the power converter, the input port and the output port of the power converter are to be maintained at corresponding first and second voltages;wherein the power converter includes a power path to couple the input port and the output port;wherein the power path further comprises a first switching configuration disposed on the power path; the first switching configuration comprising switches, a first capacitor, and a second capacitor;wherein the power path further comprises a second switching configuration disposed on the power path; the second switching configuration comprising a first set of switches and a first inductor;wherein the first or the second switching configurations to transition between a first arrangement of switches and a second arrangement of switches;wherein the power path further comprises a third switching configuration disposed on the power path, the third switching configuration comprising a second set of switches and a second inductor;wherein, in the first arrangement of switches, during operation of the power converter, charge is to accumulate in the first capacitor at a first rate, and, in the second arrangement of switches, during operation of the power converter, charge is to deplete from the first capacitor at a second rate, the first and the second rates to be constrained by the first inductor of the second switching configuration.
2. The apparatus of claim 1, wherein the second and the third switching configurations comprise a buck converter.
3. The apparatus of claim 2, wherein the first and the second inductors are to be coupled within the buck converter.
4. The apparatus of claim 1, wherein the first and the second rates are to be constrained by the second inductor.
5. The apparatus of claim 1, wherein, in the first arrangement of switches, during operation of the power converter, charge is to accumulate in the second capacitor at a third rate, and, in the second arrangement of switches, during operation of the power converter, charge is to deplete from the second capacitor at a fourth rate, the third and fourth rates to be constrained by the first inductor or by the second inductor, or a combination thereof.
6. The apparatus of claim 5, wherein the third and the fourth rates are substantially the same.
7. The apparatus of claim 1, wherein, during operation of the power converter, the second switching configuration to effectively form a magnetic filter.
8. The apparatus of claim 1, wherein the first and the second inductors comprise a magnetic core.
9. The apparatus of claim 1, wherein the first and the second rates are substantially the same.
10. The apparatus of claim 1, wherein the power converter to include separate grounds.
11. The apparatus of claim 10, wherein at least one ground of the separate grounds is to float relative to at least one other ground of the separate grounds.
12. The apparatus of claim 1, wherein the controller is to implement at least one of the following: a variable-frequency control; or control based, at least in part, on current.
13. The apparatus of claim 12, wherein the variable-frequency control is to be implemented via a pulse-width modulator (PWM).
14. The apparatus of claim 1, wherein the power converter is to implement a particular conversion ratio.
15. The apparatus of claim 14, wherein the particular conversion ratio to be determined based, at least in part, on a number of capacitors to be included in the first switching configuration.
16. A resonant power converter comprising an input port and an output port, the resonant power converter comprising: a controller to implement a deadtime interval; anda power path to couple the input port and the output port of the resonant power converter, the input port and the output port of the resonant power converter to be maintained at corresponding first and second voltages during operation of the resonant power converter,the power path comprising a first configuration disposed on the power path, the first configuration comprising switches, a first capacitor, and a second capacitor,wherein the power path further comprising a second configuration disposed on the power path, the second configuration comprising switches, a first inductor, and a second inductor,wherein the configurations to transition between a first arrangement of switches and a second arrangement of switches,wherein, in the first arrangement of switches, during operation of the resonant power converter, charge is to accumulate in the first capacitor at a first rate, and, in the second arrangement of switches, during operation of the resonant power converter, charge is to deplete from the first capacitor at a second rate, the first and the second rates to be constrained by the inductors of the second configuration, andwherein the second configuration to comprise at least one magnetic filter having a frequency at or near a resonant frequency.
17. The resonant power converter of claim 16, wherein, in the first arrangement of switches, during operation of the power converter, charge is to accumulate in the second capacitor at a third rate, and, in the second arrangement of switches, during operation of the power converter, charge is to deplete from the second capacitor at a fourth rate, the third and fourth rates to be constrained by the inductors of the second configuration.
18. The resonant power converter of claim 17, wherein the third and fourth rates are substantially the same.
19. The resonant power converter of claim 16, wherein the first and second rates are substantially the same.
20. The resonant power converter of claim 16, wherein the first and the second inductors are to be coupled.
21. An integrated circuit (IC) for use in a resonant power converter having a path for power flow between an input port and an output port of the resonant power converter, the IC comprising: one or more drivers; anda controller to implement a deadtime interval,wherein, during operation of the resonant power converter, the controller to generate one or more signals to control a plurality of switches external to the IC substantially in accordance with a switching frequency, the switching frequency to include a frequency at or near a resonant frequency to facilitate switching of at least some of the plurality of switches,wherein the path to include a first switching configuration to be disposed on the path, the first switching configuration comprising a first group of switches of the plurality of switches, a first capacitor, and a second capacitor,wherein the path further to include a second switching configuration to be disposed on the path, the second switching configuration comprising a second group of switches of the plurality of switches and a first inductor,wherein the switching configurations to transition between a first arrangement of switches and a second arrangement of switches, andwherein, in the first arrangement of switches, during operation of the resonant power converter, charge is to accumulate in the first capacitor at a first rate, and, in the second arrangement of switches, during operation of the power converter, charge is to deplete from the first capacitor at a second rate, the first and the second rates to be constrained by the first inductor of the second switching configuration.
22. The IC of claim 21, wherein the second switching configuration further comprises a second inductor, and wherein the first and the second rates are to be constrained by the second inductor.
23. The IC of claim 22, wherein, in the first arrangement of switches, during operation of the resonant power converter, charge is to accumulate in the second capacitor at a third rate, and, in the second arrangement of switches, during operation of the resonant power converter, charge is to deplete from the second capacitor at a fourth rate, the third and fourth rates to be constrained by the first inductor or by the second inductor, or a combination thereof.
24. The IC of claim 23, wherein the third and the fourth rates are substantially the same.
25. The IC of claim 22, wherein the first and the second rates are substantially the same.
26. The IC of claim 22, wherein the first and the second inductors share an inductor core.
27. The IC of claim 26, wherein the inductor core comprises a magnetic core.
28. The IC of claim 21, wherein the resonant power converter is to implement a particular conversion ratio, and wherein the particular conversion ratio is to be determined based, at least in part, on a number of capacitors to be included in the first switching configuration.

CROSS-REFERENCE TO RELATED APPLICATIONS

The following applications are related to the present application by either 35 USC 120 or 25 USC 119. U.S. application Ser. No. 15/813,546, filed Nov. 15, 2017U.S. application Ser. No. 15/068,985, filed Mar. 14, 2016.U.S. Provisional Application No. 62/132,701, filed on Mar. 13, 2015.U.S. application Ser. No. 14/513,747, filed on Oct. 14, 2014 and which issued as U.S. Pat. No. 9,362,826 on Jun. 7, 2016.U.S. application Ser. No. 13/771,904, filed on Feb. 20, 2013, and which issued as U.S. Pat. No. 8,860,396 on Oct. 14, 2014.International Application PCT/US2012/036455, filed on May 4, 2012.U.S. Provisional Application No. 61/482,838, filed May 5, 2011.U.S. Provisional Application No. 61/548,360, filed Oct. 18, 2011.U.S. Provisional Application No. 61/577,271, filed Dec. 19, 2011. The relationships between the above applications are set forth below. The applications are identified by serial number for brevity. Full bibliographic information is contained in the above list. Where a first application that “is a continuation” of a second, the applications in question are related by 35 USC 120. Where a first application “is a non-provisional” of a second, the applications are related by 35 USC 119. This application is a continuation of Ser. No. 15/813,546.Ser. No. 15/813,546 is a continuation of Ser. No. 15/068,985.Ser. No. 15/068,985 is a non-provisional of 62/132,701.Ser. No. 15/068,985 is a continuation-in-part of Ser. No. 14/513,747.Ser. No. 14/513,747 is a continuation of Ser. No. 13/771,904.Ser. No. 13/771,904 is a continuation PCT/US2012/036455.PCT/US2012/036455 is a non-provisional of 61/482,838.PCT/US2012/036455 is a non-provisional of 61/548,360.PCT/US2012/036455 is a non-provisional of 61/577,271. The contents of the foregoing applications are incorporated herein by reference.

US Referenced Citations (331)

Number	Name	Date	Kind
3370215	Light	Feb 1968	A
3745437	Brown	Jul 1973	A
3818306	Marini	Jun 1974	A
3818360	Boutmy	Jun 1974	A
4214174	Dickson	Jul 1980	A
4812961	Essaff et al.	Mar 1989	A
4903181	Seidel	Feb 1990	A
5006782	Pelly	Apr 1991	A
5057986	Henze	Oct 1991	A
5119283	Steigerwald	Jun 1992	A
5132606	Herbert	Jul 1992	A
5159539	Koyama	Oct 1992	A
5198970	Kawabata	Mar 1993	A
5268832	Kandatsu	Dec 1993	A
5301097	McDaniel	Apr 1994	A
5331303	Shiota	Jul 1994	A
5402329	Wittenbreder, Jr.	Mar 1995	A
5548206	Soo	Aug 1996	A
5557193	Kajimoto	Sep 1996	A
5661348	Brown	Aug 1997	A
5717581	Canclini	Feb 1998	A
5737201	Meynard et al.	Apr 1998	A
5761058	Kanda et al.	Jun 1998	A
5793626	Jiang	Aug 1998	A
5801987	Dinh	Sep 1998	A
5812017	Golla	Sep 1998	A
5831846	Jiang	Nov 1998	A
5892395	Stengel	Apr 1999	A
5907484	Kowshik et al.	May 1999	A
5956243	Mao	Sep 1999	A
5959565	Taniuchi	Sep 1999	A
5959585	Miltz	Sep 1999	A
5978283	Hsu et al.	Nov 1999	A
5982645	Levran	Nov 1999	A
6107864	Fukushima et al.	Aug 2000	A
6133788	Dent	Oct 2000	A
6140807	Vannatta	Oct 2000	A
6154380	Assow	Nov 2000	A
6157253	Sigmon	Dec 2000	A
6178102	Stanley	Jan 2001	B1
6198645	Kotowski	Mar 2001	B1
6255906	Eidson	Jul 2001	B1
6275018	Telefus	Aug 2001	B1
6327462	Loke	Dec 2001	B1
6339538	Handleman	Jan 2002	B1
6377117	Oskowsky	Apr 2002	B2
6396341	Pehlke	May 2002	B1
6400579	Cuk	Jun 2002	B2
6429632	Forbes	Aug 2002	B1
6476666	Palusa et al.	Nov 2002	B1
6486728	Kleveland	Nov 2002	B2
6501325	Meng	Dec 2002	B1
6504422	Rader et al.	Jan 2003	B1
6507503	Norrga	Jan 2003	B2
6515612	Abel	Feb 2003	B1
6563235	McIntyre	May 2003	B1
6650552	Takagi et al.	Nov 2003	B2
6657876	Satoh	Dec 2003	B2
6700803	Krein	Mar 2004	B2
6738277	Odell	May 2004	B2
6738432	Pehlke	May 2004	B2
6759766	Hiratsuka et al.	Jul 2004	B2
6927441	Pappalardo et al.	Aug 2005	B2
6934167	Jang	Aug 2005	B2
6980181	Sudo	Dec 2005	B2
6995995	Zeng	Feb 2006	B2
7071660	Xu et al.	Jul 2006	B2
7072195	Xu	Jul 2006	B2
7091778	Gan	Aug 2006	B2
7103114	Lapierre	Sep 2006	B1
7135847	Taurand	Nov 2006	B2
7145382	Ker et al.	Dec 2006	B2
7157956	Wei	Jan 2007	B2
7161816	Shteynberg	Jan 2007	B2
7190210	Azrai et al.	Mar 2007	B2
7224062	Hsu	May 2007	B2
7236542	Matero	Jun 2007	B2
7239194	Azrai et al.	Jul 2007	B2
7250810	Tsen	Jul 2007	B1
7259974	Donaldson	Aug 2007	B2
7269036	Deng	Sep 2007	B2
7330070	Vaisanen	Feb 2008	B2
7362251	Jensen	Apr 2008	B2
7375992	Mok	May 2008	B2
7382113	Wai	Jun 2008	B2
7382634	Buchmann	Jun 2008	B2
7408330	Zhao	Aug 2008	B2
7443705	Ito	Oct 2008	B2
7511978	Chen et al.	Mar 2009	B2
7535133	Perreault	May 2009	B2
7589605	Perreault	Sep 2009	B2
7595682	Lin et al.	Sep 2009	B2
7616467	Mallwitz	Nov 2009	B2
7633778	Mok	Dec 2009	B2
7696735	Oraw	Apr 2010	B2
7705681	Ilkov	Apr 2010	B2
7724551	Yanagida et al.	May 2010	B2
7768800	Mazumduer	Aug 2010	B2
7777459	Williams	Aug 2010	B2
7782027	Williams	Aug 2010	B2
7786712	Williams	Aug 2010	B2
7807499	Nishizawa	Oct 2010	B2
7812579	Williams	Oct 2010	B2
7889519	Perreault	Feb 2011	B2
7907429	Ramadass	Mar 2011	B2
7907430	Kularatna et al.	Mar 2011	B2
7928705	Hooijschuur et al.	Apr 2011	B2
7940038	Da Silva	May 2011	B2
7956572	Zane	Jun 2011	B2
7977921	Bahai et al.	Jul 2011	B2
7999601	Schlueter et al.	Aug 2011	B2
8000117	Petricek	Aug 2011	B2
8018216	Kakehi	Sep 2011	B2
8026763	Dawson	Sep 2011	B2
8031003	Dishop	Oct 2011	B2
8040174	Likhterov	Oct 2011	B2
8048766	Joly et al.	Nov 2011	B2
8085524	Roozeboom	Dec 2011	B2
8089788	Rinkle	Jan 2012	B2
8106597	Mednik et al.	Jan 2012	B2
8111054	Yen et al.	Feb 2012	B2
8130518	Fishman	Mar 2012	B2
8159091	Yeates	Apr 2012	B2
8164384	Dawson	Apr 2012	B2
8169797	Coccia	May 2012	B2
8193604	Lin et al.	Jun 2012	B2
8212541	Perreault et al.	Jul 2012	B2
8276002	Dennard	Sep 2012	B2
8330436	Oraw et al.	Dec 2012	B2
8339184	Kok et al.	Dec 2012	B2
8350549	Kitabatake	Jan 2013	B2
8384467	O'Keeffe et al.	Feb 2013	B1
8395914	Klootwijk et al.	Mar 2013	B2
8423800	Huang et al.	Apr 2013	B2
8451053	Nguyen	May 2013	B2
8456874	Singer et al.	Jun 2013	B2
8503203	Szczeszynski et al.	Aug 2013	B1
8542169	Senda	Sep 2013	B2
8582333	Oraw et al.	Nov 2013	B2
8629666	Carroll	Jan 2014	B2
8643347	Perreault	Feb 2014	B2
8659353	Dawson	Feb 2014	B2
8670254	Perreault	Mar 2014	B2
8699248	Perreault	Apr 2014	B2
8718188	Balteanu	May 2014	B2
8729819	Zhao	May 2014	B2
8824978	Briffa	Sep 2014	B2
8829993	Briffa	Sep 2014	B2
8830709	Perreault	Sep 2014	B2
8830710	Perreault	Sep 2014	B2
8856562	Huang et al.	Oct 2014	B2
8860396	Giuliano	Oct 2014	B2
8957727	Dawson	Feb 2015	B2
9048727	Giuliano	Jun 2015	B2
9209758	Briffa	Dec 2015	B2
9362826	Giuliano	Jun 2016	B2
9450506	Perreault	Sep 2016	B2
9577590	Levesque	Feb 2017	B2
9634577	Perreault	Apr 2017	B2
9712051	Giuliano	Jul 2017	B2
9755672	Perreault	Sep 2017	B2
9882471	Giuliano	Jan 2018	B2
10326358	Giuliano	Jun 2019	B2
10381924	Giuliano	Aug 2019	B2
10389235	Giuliano	Aug 2019	B2
10404162	Giuliano	Sep 2019	B2
10541611	Giuliano	Jan 2020	B2
10680515	Giuliano	Jun 2020	B2
10917007	Giuliano	Feb 2021	B2
10938300	Giuliano	Mar 2021	B2
20030169096	Hsu et al.	Sep 2003	A1
20030227280	Vinciarelli	Dec 2003	A1
20040041620	D'Angelo et al.	Mar 2004	A1
20040170030	Duerbaum	Sep 2004	A1
20040222775	Muramatsu	Nov 2004	A1
20050007184	Kamijo	Jan 2005	A1
20050088865	Lopez	Apr 2005	A1
20050207133	Pavier et al.	Sep 2005	A1
20050213267	Azrai	Sep 2005	A1
20050286278	Perreault	Dec 2005	A1
20060139021	Taurand	Jun 2006	A1
20060213890	Kooken	Sep 2006	A1
20060226130	Kooken	Oct 2006	A1
20070035977	Odell	Feb 2007	A1
20070051712	Kooken	Mar 2007	A1
20070066224	D'Hont	Mar 2007	A1
20070066250	Takahashi	Mar 2007	A1
20070069818	Bhatti	Mar 2007	A1
20070091655	Oyama	Apr 2007	A1
20070123184	Nesimoglu	May 2007	A1
20070146020	Williams	Jun 2007	A1
20070146090	Carey	Jun 2007	A1
20070159257	Lee	Jul 2007	A1
20070171680	Perreault	Jul 2007	A1
20070210774	Kimura et al.	Sep 2007	A1
20070230221	Lim et al.	Oct 2007	A1
20070247222	Sorrells	Oct 2007	A1
20070247253	Carey	Oct 2007	A1
20070281635	McCallister	Dec 2007	A1
20070290747	Traylor	Dec 2007	A1
20070291718	Chan	Dec 2007	A1
20070296383	Xu et al.	Dec 2007	A1
20080001660	Rasmussen	Jan 2008	A1
20080003960	Zolfaghari	Jan 2008	A1
20080003962	Ngai	Jan 2008	A1
20080007333	Lee	Jan 2008	A1
20080012637	Aridas	Jan 2008	A1
20080013236	Weng	Jan 2008	A1
20080019459	Chen	Jan 2008	A1
20080031023	Kitagawa	Feb 2008	A1
20080055946	Lesso	Mar 2008	A1
20080062724	Feng	Mar 2008	A1
20080136500	Frulio	Jun 2008	A1
20080136991	Senda	Jun 2008	A1
20080150621	Lesso et al.	Jun 2008	A1
20080157732	Williams	Jul 2008	A1
20080157733	Williams	Jul 2008	A1
20080158915	Williams	Jul 2008	A1
20080239772	Oraw	Oct 2008	A1
20090033293	Xing	Feb 2009	A1
20090059630	Williams	Mar 2009	A1
20090072800	Ramadass	Mar 2009	A1
20090102439	Williams	Apr 2009	A1
20090147554	Adest	Jun 2009	A1
20090196082	Mazumder	Aug 2009	A1
20090257211	Kontani et al.	Oct 2009	A1
20090273955	Tseng	Nov 2009	A1
20090278520	Perreault	Nov 2009	A1
20090302686	Fishman	Dec 2009	A1
20090303753	Fu	Dec 2009	A1
20090322304	Oraw	Dec 2009	A1
20090323380	Harrison	Dec 2009	A1
20100073084	Hur	Mar 2010	A1
20100085786	Chiu	Apr 2010	A1
20100110741	Lin et al.	May 2010	A1
20100117612	Klootwijk	May 2010	A1
20100140736	Lin et al.	Jun 2010	A1
20100142239	Hopper	Jun 2010	A1
20100201441	Gustavsson	Aug 2010	A1
20100202161	Sims et al.	Aug 2010	A1
20100214746	Lotfi et al.	Aug 2010	A1
20100244189	Klootwijk	Sep 2010	A1
20100244585	Tan	Sep 2010	A1
20100291888	Hadjichristos	Nov 2010	A1
20100308751	Nerone	Dec 2010	A1
20110001542	Ranta	Jan 2011	A1
20110089483	Reynes	Apr 2011	A1
20110101884	Kim et al.	May 2011	A1
20110148518	Lejon	Jun 2011	A1
20110163414	Lin et al.	Jul 2011	A1
20110175591	Cuk	Jul 2011	A1
20110181128	Perreault	Jul 2011	A1
20120043818	Stratakos	Feb 2012	A1
20120064953	Dagher	Mar 2012	A1
20120146177	Choi et al.	Jun 2012	A1
20120153907	Carobolante	Jun 2012	A1
20120170334	Menegoli	Jul 2012	A1
20120176195	Dawson	Jul 2012	A1
20120243267	Kassayan	Sep 2012	A1
20120249096	Enenkel	Oct 2012	A1
20120252382	Bashir	Oct 2012	A1
20120313602	Perreault et al.	Dec 2012	A1
20120326684	Perreault et al.	Dec 2012	A1
20130005286	Chan	Jan 2013	A1
20130049714	Chiu	Feb 2013	A1
20130049885	Rozman	Feb 2013	A1
20130058049	Roth	Mar 2013	A1
20130058141	Oraw et al.	Mar 2013	A1
20130094157	Giuliano	Apr 2013	A1
20130106380	Marsili	May 2013	A1
20130154600	Giuliano	Jun 2013	A1
20130181521	Khlat	Jul 2013	A1
20130187612	Aiura	Jul 2013	A1
20130229841	Giuliano	Sep 2013	A1
20130241625	Perreault	Sep 2013	A1
20130343106	Perreault	Dec 2013	A1
20130343107	Perreault	Dec 2013	A1
20140015731	Khlat	Jan 2014	A1
20140118065	Briffa	May 2014	A1
20140118072	Briffa	May 2014	A1
20140120854	Briffa	May 2014	A1
20140159681	Oraw	Jun 2014	A1
20140167513	Chang	Jun 2014	A1
20140225581	Giuliano	Aug 2014	A1
20140226378	Perreault	Aug 2014	A1
20140306648	Le	Oct 2014	A1
20140306673	Le	Oct 2014	A1
20140313781	Perreault	Oct 2014	A1
20140335805	Briffa	Nov 2014	A1
20140339918	Perreault	Nov 2014	A1
20140355322	Perreault	Dec 2014	A1
20150022173	Le	Jan 2015	A1
20150023063	Perreault	Jan 2015	A1
20150084701	Perreault	Mar 2015	A1
20150097538	Le	Apr 2015	A1
20150102798	Giuliano	Apr 2015	A1
20150155895	Perreault	Jun 2015	A1
20150280553	Giuliano	Oct 2015	A1
20150295497	Perreault	Oct 2015	A1
20150357912	Perreault	Dec 2015	A1
20150364991	Chung	Dec 2015	A1
20160093948	Lehtola	Mar 2016	A1
20160094126	Liu	Mar 2016	A1
20160111356	Cho	Apr 2016	A1
20160197552	Giuliano	Jul 2016	A1
20160254754	Perreault	Sep 2016	A1
20160322894	Giuliano	Nov 2016	A1
20170237351	Giuliano	Aug 2017	A1
20170244318	Giuliano	Aug 2017	A1
20170279374	Friebe	Sep 2017	A1
20170300078	Puggelli	Oct 2017	A1
20170302093	Peterson	Oct 2017	A1
20180034363	Giuliano	Feb 2018	A1
20180145587	Giuliano	May 2018	A1
20180205315	Giuliano	Jul 2018	A1
20190027468	Giuliano	Jan 2019	A1
20190028018	Datta	Jan 2019	A1
20190115830	Giuliano	Apr 2019	A1
20190207513	Ramadass	Jul 2019	A1
20190393777	Giuliano	Dec 2019	A1
20200021187	Chang	Jan 2020	A1
20200036286	Giuliano	Jan 2020	A1
20200083805	Mauri	Mar 2020	A1
20200112247	Giuliano	Apr 2020	A1
20200127557	Giuliano	Apr 2020	A1
20200136494	Kazama	Apr 2020	A1
20200195136	Huang	Jun 2020	A1
20200204172	Geng	Jun 2020	A1
20200246626	Labbe	Aug 2020	A1
20200253520	Wang	Aug 2020	A1
20210013798	Giuliano	Jan 2021	A1

Foreign Referenced Citations (54)

Number	Date	Country
1132959	Oct 1996	CN
101563845	Oct 2009	CN
101636702	Jan 2010	CN
101647182	Feb 2010	CN
101662208	Mar 2010	CN
101976953	Feb 2011	CN
102055328	May 2011	CN
102769986	Nov 2012	CN
103650313	Mar 2014	CN
103650314	Mar 2014	CN
103975433	Aug 2014	CN
104011985	Aug 2014	CN
105229909	Jan 2016	CN
107580748	Jan 2018	CN
108964442	Dec 2018	CN
109219919	Jan 2019	CN
109478845	Mar 2019	CN
112838760	May 2021	CN
10358299	Jul 2005	DE
112016001188	Mar 2018	DE
112017002374	Jan 2019	DE
0513920	Nov 1992	EP
1750366	Feb 2007	EP
2705597	Aug 2018	EP
3425784	Jan 2019	EP
2852748	Sep 2004	FR
2505371	Feb 2014	GB
10327573	Dec 1998	JP
11235053	Aug 1999	JP
2000134095	May 2000	JP
2002062858	Feb 2002	JP
2002-233139	Aug 2002	JP
2010045943	Feb 2010	JP
2018508178	Mar 2018	JP
20110053681	May 2011	KR
20140015528	Feb 2014	KR
20150085072	Jul 2015	KR
101556838	Oct 2015	KR
20180004116	Jan 2018	KR
20180118234	Oct 2018	KR
201644164	Dec 2016	TW
2006093600	Sep 2006	WO
WO2007136919	Nov 2007	WO
2009112900	Sep 2009	WO
WO2012151466	Nov 2012	WO
2013059446	Apr 2013	WO
2013096416	Jun 2013	WO
WO2013086445	Jun 2013	WO
WO2014070998	May 2014	WO
2014154390	Oct 2014	WO
2014169186	Oct 2014	WO
WO2014168911	Oct 2014	WO
WO2016149105	Sep 2016	WO
WO2017196826	Nov 2017	WO

Non-Patent Literature Citations (355)

Entry
O. Abutbul et al. “Step-Up Switching-Mode Converter With High Voltage Gain Using a Switched-Capacitor Circuit” IEEE Transactions on Circuits and Systems I., vol. 50, pp. 1098-1102, Aug. 2003.
Umeno et al. “A New Approach to Low Ripple-Noise Switching Converters on the Basis of Switched-Capacitor Converters” IEEE International Symposium on Circuits and Systems, vol. 2, pp. 1077-1080, Jun. 1991.
Axelrod et al. “Single-switch single-stage switched-capacitor buck converter”, Proc. of NORPIE 2004, 4th Nordic Workshop on Power and Industrial Electronics, Jun. 2004.
Sun et al. “High Power Density, High Efficiency System Two-Stage Power Architecture for Laptop Computers”, Power Electronics Specialists Conference, pp. 1-7, Jun. 2006.
R. D. Middlebrook, “Transformerless DC-to-DC Converters with Large Conversion Ratios” IEEE Transactions on Power Electronics, vol. 3, No. 4, pp. 484-488, Oct. 1988.
Wood et al., “Design, Fabrication and Initial Results of a 2g Autonomous Glider” IEEE Industrial Electronics Society, pp. 1870-1877, Nov. 2005.
T. A. Meynard, H. Foch, “Multi-Level Conversion: High Voltage Choppers and Voltage-Source Inverters,” IEEE Power Electronics Specialists Conference, pp. 397-403, 1992.
Pilawa-Podgurski et al. “Merged Two-Stage Power Converter Architecture with Soft Charging Switched-Capacitor Energy Transfer” 39th IEEE Power Electronics Specialists Conference, 2008.
Han et al. “A New Approach to Reducing Output Ripple in Switched-Capacitor-Based Step-Down DC-DC Converters” IEEE Transactions on Power Electronics, vol. 21, No. 6, pp. 1548-1555 Nov. 2006.
Lei et al. “Analysis of Switched-capacitor DC-DC Converters in Soft-charging Operation” 14th IEEE Workshop on Control and Modeling for Power Electronics, pp. 1-7, Jun. 23, 2013.
Ng et al. “Switched Capacitor DC-DC Converter: Superior where the Buck Converter has Dominated” PhD Thesis, UC Berkeley, Aug. 17, 2011.
R. Pilawa-Podgurski and D. Perreault, “Merged Two-Stage Power Converter with Soft Charging Switched-Capacitor Stage in 180 nm CMOS,” IEEE Journal Of Solid-State Circuits, vol. 47, No. 7, pp. 1557-1567, Jul. 2012.
Ottman et al., “Optimized Piezoelectric Energy Harvesting Circuit using Step-Down Converter in Discontinuous Conduction Mode”, IEEE Power Electronics Specialists Conference, pp. 1988-1994, 2002.
Ma et al., “Design and Optimization of Dynamic Power System for Self-Powered Integrated Wireless Sensing Nodes” ACM ISLPED '05 conference (published at pp. 303-306 of the proceedings).
Xu et al., “Voltage Divider and its Application in Two-stage Power Architecture,” IEEE Twenty-First Annual IEEE Applied Power Electronics Conference and Exposition, pp. 499-504, Mar. 2006.
Markowski, “Performance Limits of Switched-Capacitor DC-DC Converters”, IEEE PESC'95 Conference, 1995.
Texas Instruments data sheet for part TPS54310, “3-V to 6-V input, 3-A output synchronous-buck PWM switcher with integrated FETs”, dated 2002-2005.
Linear Technology data sheet for part LTC3402, “2A, 3MHz Micropower Synchronous Boost Converter”, 2000.
Starzyk et al., “A DC-DC Charge Pump Design Based on Voltage Doublers,” IEEE Transactions on Circuits and Systems—I: Fundamental Theory and Applications, vol. 48, No. 3, Mar. 2001, pp. 350-359.
U.S. Appl. No. 16/456,060: Request for Continued Examination and Information Disclosure Statement filed Apr. 5, 2021, 96 pages Doc 8046.
U.S. Appl. No. 16/456,060: Response to Notice to File Corrected Application Papers filed Apr. 12, 2021, 22 pages Doc 8043.
U.S. Appl. No. 16/456,060: Notice of Allowance/Allowability dated Apr. 28, 2021, 39 pages Doc 8045.
CN 201780030693: Second Office Action dated Mar. 15, 2021, 19 pages Doc 8039.
CN201780042383: Patent Certificate dated Mar. 23, 2021, 4 pages Doc 8040
202110224392.X: Request for Examination filed Apr. 30, 2021, 2 pages, Doc 8041.
U.S. Appl. No. 17/187,664: Preliminary Amendment and Response to Notice to File Missing Parts filed Jul. 12, 2021, 17 pages, Doc 8098.
CN201810954743: Decision on Rejection dated May 27, 2021, 7 pages, Doc 8099.
CN201680027105.3: Response to Third Office Action filed Jun. 17, 2021, 14 pages, Doc 8100.
U.S. Appl. No. 16/456,060: Issue Fee Payment and Comments filed Jul. 28, 2021, 8 pages Doc 8103.
202110224392.X: Notice of Entry into Substantive Examination dated May 31, 2021, 3 pages, Doc 8102
Giuliano—“Architectures and Topologies for Power Delivery”, Biannual Review of MIT Center for Integrated Circuits; Power Point Presentation, May 9, 2007, 17 slides, Doc 7426.
Giuliano—“Architectures and Topologies for Power Delivery”, Biannual Review of MIT Center for Integrated Circuits; Power Point Presentation, May 9, 2007, 17 slides.
U.S. Appl. No. 16/931,768: Issue Notification dated Feb. 10, 2021, 13 pages, Doc 7414.
U.S. Appl. No. 17/187,664: U.S. Appl. No. 17/187,664, filed Feb. 26, 2021, 56 pages, Doc 7415.
U.S. Appl. No. 17/187,664: Filing Receipt and Notice to File Missing Parts dated Mar. 10, 2021, 7 pages, Doc 7416.
U.S. Appl. No. 16/534,196: Office Action dated Jan. 29, 2021, 10 pages Doc 7419.
U.S. Appl. No. 16/862,351: Notice of Publication dated Jan. 14, 2021, 1 page Doc 7423.
CN201810954743: Response to Second Office Action filed Feb. 7, 2021, 41 pages, Doc 7417.
EP18188795: Article 94(3) Communication dated Jan. 12, 2021, 5 pages Doc 7418.
CN201680027105.3: Third Office Action dated Feb. 3, 2021, 26 pages, Doc 7420.
JP2017567041: Final Office Action dated Mar. 29, 2021, 8 pages, Doc 7421.
KR20177029575: Voluntary Amendment and Request for Examination filed Mar. 9, 2021, 38 pages Doc 7422.
CN201780042383: Decision to Grant dated Dec. 14, 2020, 4 pages Doc 7424.
202110224392.X: Patent Application No. 202110224392.X filed Mar. 1, 2021, 128 pages, Doc 7425.
Andreassen—“Digital Variable Frequency Control for Zero Voltage Switching and Interleaving of Synchronous Buck Converters” 12th Intl. Power Electronics and Motion Control Conference, IEEE Aug. 2006, pp. 184-188, 5 pages, Doc 7043.
Cao—“Multiphase Multilevel Modular DC-DC Converter for High-Current High-Gain TEG Application” IEEE Transactions on Industry Applications, vol. 47, No. 3, May/Jun. 1991, pp. 1400-1408, 9 pages, 7042.
Cheng—“New Generation of Switched Capacitor Converters” PESC 98 Record, 29th Annual IEEE Power Electronics and Motion Control Conference, Wuhan, China, May 17-20, 2009, pp. 1529-1535, 7 pages, Doc 7049.
Luo—“Investigation of Switched-Capacitorized DC/DC Converters” 2009 IEEE 6th Intl. Power Electronics and Motion Control Conference, Wuhan, China, May 17-20, 2009, pp. 1270-1276, 7 pages, Doc 7050.
U.S. Appl. No. 13/771,904: US Patent Application filed Feb. 20, 2013, 62 pages, Doc 7111.
U.S. Appl. No. 13/771,904: Filing Receipt and Notice to File Corrected Application Papers dated Mar. 20, 2013, 6 pages, Doc 7112.
U.S. Appl. No. 13/771,904: Response to Notice to File Corrected Application Papers filed May 20, 2013, 30 pages, Doc 7113.
U.S. Appl. No. 13/771,904: Updated Filing Receipt and Informational Notice dated May 28, 2013, 4 pages, Doc 7114.
U.S. Appl. No. 13/771,904: Notice of Publication dated Sep. 5, 2013, 1 page, Doc 7115.
U.S. Appl. No. 13/771,904: Nonfinal Office Action dated Sep. 13, 2013, 12 pages, Doc 7116.
U.S. Appl. No. 13/771,904: Amendment filed Mar. 13, 2014, 11 pages, Doc 7117.
U.S. Appl. No. 13/771,904: Final Office Action dated Apr. 8, 2014, 16 pages, Doc 7118.
U.S. Appl. No. 13/771,904: Amendment filed May 23, 2014, 11 pages, Doc 7119.
U.S. Appl. No. 13/771,904: Notice of Allowance dated Jun. 9, 2014, 12 pages, Doc 7120.
U.S. Appl. No. 13/771,904: Issue Fee Payment and 312 Amendment filed Aug. 29, 2014, 14 pages, Doc 7121.
U.S. Appl. No. 13/771,904: Examiner Response to 312 Amendment dated Sep. 11, 2014, 3 pages, Doc 7122.
U.S. Appl. No. 13/771,904: Issue Notification dated Sep. 24, 2014, 1 page, Doc 7123.
U.S. Appl. No. 14/513,747: US Patent Application filed Oct. 14, 2014, 76 pages Doc 7124.
U.S. Appl. No. 14/513,747: Filing Receipt and Notice to File Corrected Application Papers dated Oct. 22, 2014, 5 pages Doc 7125.
U.S. Appl. No. 14/513,747: Response to Notice to File Corrected Application Papers with Amendment dated Dec. 22, 2014, 47 pages Doc 7126.
U.S. Appl. No. 14/513,747: Updated Filing Receipt dated Jan. 5, 2015, 3 pages Doc 7127.
U.S. Appl. No. 14/513,747: Notice of Publication dated Apr. 16, 2015, 1 page Doc 7128.
U.S. Appl. No. 14/513,747: Petition to Make Special Under Patent Prosecution Highway dated Apr. 22, 2015, 4 pages Doc 7129.
U.S. Appl. No. 14/513,747: Decision Granting Petition to Make Special Under Patent Prosecution Highway dated Apr. 22, 2015, 5 pages Doc 7130.
U.S. Appl. No. 14/513,747: Non-final Office Action dated Jun. 17, 2015, 19 pages Doc 7131.
U.S. Appl. No. 14/513,747: Amendment filed Sep. 17, 2015, 13 pages Doc 7132.
U.S. Appl. No. 14/513,747: Final Office Action dated Oct. 14, 2015, 17 pages Doc 7133.
U.S. Appl. No. 14/513,747: Amendment filed Jan. 14, 2016, 12 pages Doc 7134.
U.S. Appl. No. 14/513,747: Notice of Allowance dated Jan. 26, 2016, 12 pages Doc 7135.
U.S. Appl. No. 14/513,747: Issue Fee Payment filed Apr. 26, 2016, 1 page Doc 7136.
U.S. Appl. No. 14/513,747: Issue Notification dated May 10, 2016, 1 page Doc 7137.
U.S. Appl. No. 15/138,692: US Patent Application filed Apr. 26, 2016, 60 pages Doc 7138.
U.S. Appl. No. 15/138,692: Filing Receipt and Notice to File Missing Parts dated May 13, 2016, 6 pages Doc 7139.
U.S. Appl. No. 15/138,692: Response to Notice to File Missing Parts and Amendment dated Jul. 13, 2016, 14 pages Doc 7140.
U.S. Appl. No. 15/138,692: Updated Filing Receipt dated Jul. 13, 2016, 4 pages Doc 7141.
U.S. Appl. No. 15/138,692: Notice of Publication dated Nov. 3, 2016, 1 page Doc 7142.
U.S. Appl. No. 15/138,692: Notice of Allowance and Allowability dated Mar. 10, 2017, 24 pages Doc 7143.
U.S. Appl. No. 15/138,692: Supplemental Notice of Allowability dated Apr. 11, 2017, 5 pages Doc 7144.
U.S. Appl. No. 15/138,692: Issue Fee Payment and 312 Amendment filed Jun. 9, 2017, 10 pages Doc 7145.
U.S. Appl. No. 15/138,692: Examiner Response to 312 Amendment and Corrected Filing Receipt dated Jun. 21, 2017, 6 pages Doc 7146
U.S. Appl. No. 15/138,692: Issue Notification dated Jun. 28, 2017, 1 page Doc 7147.
U.S. Appl. No. 15/618,481: US Patent Application filed Jun. 9, 2017, 63 pages Doc 7148.
U.S. Appl. No. 15/618,481: Filing Receipt and Notice to File Missing Parts dated Jun. 20, 2017, 6 pages Doc 7149.
U.S. Appl. No. 15/618,481: Response to Notice to File Missing Parts and Preliminary Amendment filed Oct. 20, 2017, 21 pages Doc 7150.
U.S. Appl. No. 15/618,481: Request to Update Name of Applicant filed Oct. 24, 2017, 11 pages Doc 7151.
U.S. Appl. No. 15/618,481: Updated Filing Receipt dated Oct. 24, 2017, 5 pages Doc 7152.
U.S. Appl. No. 15/618,481: Corrected Filing Receipt and Acceptance of Power of Attorney dated Oct. 26, 2017, 5 pages Doc 7153.
U.S. Appl. No. 15/618,481: Notice of Publication dated Feb. 1, 2018, 1 page Doc 7154.
U.S. Appl. No. 15/618,481: Request to Update Name of Applicant filed Feb. 23, 2018, 12 pages Doc 7155.
U.S. Appl. No. 15/618,481: Corrected Filing Receipt dated May 14, 2018, 4 pages Doc 7156.
U.S. Appl. No. 15/618,481: Notice of Allowance and Allowability dated Feb. 6, 2019, 27 pages Doc 7157.
U.S. Appl. No. 15/618,481: Issue Fee Payment dated May 3, 2019, 6 pages Doc 7158.
U.S. Appl. No. 15/618,481: Issue Notification dated May 29, 2019, 1 page Doc 7159.
U.S. Appl. No. 16/444,428: US Patent Application filed Jun. 18, 2019, 59 pages Doc 7160.
U.S. Appl. No. 16/444,428: Filing Receipt and Notice to File Missing Parts dated Jun. 26, 2019, 7 pages Doc 7161.
U.S. Appl. No. 16/444,428: Response to Notice to File Missing Parts dated Dec. 26, 2019, 15 pages Doc 7162.
U.S. Appl. No. 16/444,428: Updated Filing dated Dec. 30, 2019, 6 pages Doc 7163.
U.S. Appl. No. 16/444,428: Notice of Publication dated Apr. 9, 2020, 1 page Doc 7164.
U.S. Appl. No. 16/444,428: Preliminary Amendment dated May 8, 2020, 13 pages Doc 7165.
U.S. Appl. No. 16/444,428: Supplemental Amendment dated Jul. 29, 2020, 13 pages Doc 7166.
U.S. Appl. No. 16/444,428: Notice of Allowance and Allowability dated Aug. 24, 2020, 33 pages Doc 7167.
U.S. Appl. No. 16/444,428: Request for Continued Examination filed Sep. 8, 2020, 14 pages Doc 7168.
U.S. Appl. No. 16/444,428: Notice of Allowance and Allowability dated Sep. 16, 2020, 33 pages Doc 7169.
U.S. Appl. No. 16/444,428: Notice of Allowance and Allowability dated Oct. 30, 2020, 36 pages Doc 7375.
U.S. Appl. No. 16/919,033: US Patent Application filed Jul. 1, 2020, 73 pages, Doc 7170.
U.S. Appl. No. 16/919,033: Amended Application Data Sheet filed Jul. 2, 2020, 7 pages, Doc 7171.
U.S. Appl. No. 16/919,033: Filing Receipt and Notice of Missing Parts dated Jul. 15, 2020, 12 pages, Doc 7172.
U.S. Appl. No. 16/919,033: Petition for Express Abandonment filed Sep. 8, 2020, 4 pages, Doc 7390.
U.S. Appl. No. 16/919,033: Decision Granting Petition for Express Abandonment dated Oct. 16, 2020, 2 pages, Doc 7391.
U.S. Appl. No. 16/931,768: US Patent Application filed Jul. 17, 2020, 73 pages, Doc 7376.
U.S. Appl. No. 16/931,768: Filing Receipt dated Jul. 29, 2020, 6 pages, Doc 7377.
U.S. Appl. No. 16/931,768: Acceptance of Track One dated Jul. 30, 2020, 2 pages, Doc 7378.
U.S. Appl. No. 16/931,768: Notice of Allowance and Allowability dated Aug. 25, 2020, 26 pages, Doc 7379.
U.S. Appl. No. 16/931,768: Corrected Notice of Allowability dated Sep. 14, 2020, 7 pages, Doc 7380.
U.S. Appl. No. 16/931,768: Corrected Notice of Allowability dated Oct. 15, 2020, 11 pages, Doc 7381.
U.S. Appl. No. 16/931,768: Notice of Publication dated Nov. 5, 2020, 1 page, Doc 7382.
U.S. Appl. No. 16/931,768: Request for Continued Examination filed Nov. 5, 2020, 14 pages, Doc 7383.
U.S. Appl. No. 16/931,768: Notice of Allowance and Notice of Allowability dated Dec. 3, 2020, 26 pages, Doc 7392.
U.S. Appl. No. 16/931,768: Issue Fee Payment and 312 Response filed Dec. 30, 2020 , 13 pages, Doc 7393.
U.S. Appl. No. 15/068,985: Patent Application filed Mar. 14, 2016, 90 pages Doc 7197.
U.S. Appl. No. 15/068,985: Filing Receipt and Informational Notice dated Mar. 29, 2016, 5 pages Doc 7198.
U.S. Appl. No. 15/068,985: Request for Corrected filed Apr. 29, 2016, 8 pages Doc 7199.
U.S. Appl. No. 15/068,985: Preliminary Amendment filed Apr. 29, 2016, 3 pages Doc 7200.
U.S. Appl. No. 15/068,985: Corrected Filing Receipt dated May 9, 2016, 3 pages Doc 7201.
U.S. Appl. No. 15/068,985: Request for Corrected Filing Receipt dated May 31, 2016, 1 page Doc 7202.
U.S. Appl. No. 15/068,985: Corrected Filing Receipt dated Jun. 8, 2016, 4 pages Doc 7203
U.S. Appl. No. 15/068,985: Notice of Publication dated Jul. 7, 2016, 1 page Doc 7204.
U.S. Appl. No. 15/068,985: Non-final Office Action dated Mar. 7, 2017, 20 pages Doc 7205.
U.S. Appl. No. 15/068,985: Response to Non-final Office Action filed Jul. 7, 2017, 20 pages Doc 7206 .
U.S. Appl. No. 15/068,985: Notice of Allowance dated Aug. 11, 2017, 17 pages Doc 7207.
U.S. Appl. No. 15/068,985: Issue Fee Payment and 312 Amendment filed Nov. 9, 2017, 16 pages Doc 7208.
U.S. Appl. No. 15/068,985: Request to Expedite Petition to Correct Priority filed Nov. 14, 2017, 5 pages Doc 7209.
U.S. Appl. No. 15/068,985: Order Granting Petition to Correct Priority and Corrected Filing Receipt dated Nov. 28, 2017, 6 pages Doc 7210.
U.S. Appl. No. 15/068,985: Issue Notification dated Jan. 10, 2018, 1 page Doc 7211.
U.S. Appl. No. 15/813,546: Application as filed Nov. 15, 2017, 77 pages, Doc 7212.
U.S. Appl. No. 15/813,546: Filing Receipt and Notice to File Missing Parts dated Dec. 13, 2017, 7 pages, Doc 7213.
U.S. Appl. No. 15/813,546: Response to Notice to File Missing Parts and Preliminary Amendment filed Feb. 12, 2018, 12 pages, Doc 7214.
U.S. Appl. No. 15/813,546: Updated Filing Receipt dated Feb. 15, 2018, 5 pages, Doc 7215.
U.S. Appl. No. 15/813,546: Amended Application Data Sheet filed Feb. 28, 2018, 12 pages, Doc 7216.
U.S. Appl. No. 15/813,546: Notice of Publication dated May 24, 2018, 1 page, Doc 7217.
U.S. Appl. No. 15/813,546: Non-final Office Action dated Jun. 1, 2018, 17 pages, Doc 7218.
U.S. Appl. No. 15/813,546: Amendment and terminal Disclaimer filed Aug. 30, 2018, 15 pages, Doc 7219.
U.S. Appl. No. 15/813,546: Request to Change Applicant Name filed Sep. 5, 2018, 13 pages, Doc 7220.
U.S. Appl. No. 15/813,546: Updated Filing Receipt dated Jan. 9, 2019, 4 pages, Doc 7221.
U.S. Appl. No. 15/813,546: Final Rejection dated Mar. 11, 2019, 10 pages, Doc 7222.
U.S. Appl. No. 15/813,546: Response to Final Rejection and Terminal Disclaimer dated Mar. 20, 2019, 10 pages, Doc 7223.
U.S. Appl. No. 15/813,546: Approval Terminal Disclaimer dated Mar. 22, 2019, 1 page, Doc 7224.
U.S. Appl. No. 15/813,546: Notice of Allowance and Allowability dated Apr. 3, 2019, 16 pages, Doc 7225.
U.S. Appl. No. 15/813,546: Supplemental Notice of Allowability dated Jun. 25, 2019, 3 pages, Doc 7226
U.S. Appl. No. 15/813,546: Issue Fee Payment and 312 Amendment dated Jul. 3, 2019, 15 pages, Doc 7227.
U.S. Appl. No. 15/813,546: Response to 312 Amendment dated Aug. 6, 2019, 3 pages, Doc 7228.
U.S. Appl. No. 15/813,546: Issue Notification dated Aug. 14, 2019, 1 page, Doc 7229.
PCT/US2017/023191: PCT Application filed Mar. 20, 2017, 94 pages Doc 7345.
PCT/US2017/023191: Intl Search Report and Written Opinion dated Jun. 30, 2017, 9 pages Doc 7356 .
U.S. Appl. No. 16/085,680: Patent Application filed Sep. 17, 2018, 391 pages Doc 7243.
U.S. Appl. No. 16/085,680: Filing Receipt dated Jan. 9, 2019, 7 pages Doc 7244.
U.S. Appl. No. 16/085,680: Notice of Allowance and Allowability dated Mar. 8, 2019, 17 pages Doc 7245.
U.S. Appl. No. 16/085,680: Notice of Publication dated Apr. 18, 2019, 1 page Doc 7246.
U.S. Appl. No. 16/085,680: Replacement Figures filed Apr. 23, 2019, 8 pages Doc 7247.
U.S. Appl. No. 16/085,680: Examiner Interview Summary dated May 14, 2019, 5 pages Doc 7248.
U.S. Appl. No. 16/085,680: Examiner Interview Summary dated May 16, 2019, 5 pages Doc 7249.
U.S. Appl. No. 16/085,680: Supplemental Notice of Allowability dated May 24, 2019, 20 pages Doc 7250.
U.S. Appl. No. 16/085,680: Issue Fee Payment filed Jun. 10, 2019, 7 pages Doc 7251.
U.S. Appl. No. 16/085,680: Issue Notification dated Jul. 24, 2019, 1 page Doc 7252.
U.S. Appl. No. 16/538,068: Patent Application filed Aug. 12, 2019, 105 pages Doc 7253.
U.S. Appl. No. 16/538,068: Filing Receipt and Notice to File Missing Parts dated Aug. 23, 2019, 7 pages Doc 7254.
U.S. Appl. No. 16/538,068: Response to Notice to File Missing Parts dated Oct. 23, 2019, 6 pages Doc 7255.
U.S. Appl. No. 16/538,068: Updated Filing Receipt dated Oct. 25, 2019, 5 pages Doc 7256.
U.S. Appl. No. 16/538,068: Notice of Allowance and Allowability dated Jan. 29, 2020, 33 pages Doc 7257.
U.S. Appl. No. 16/538,068: Notice of Publication dated Jan. 30, 2020, 1 page Doc 7258.
U.S. Appl. No. 16/538,068: Issue Fee Payment filed Apr. 29, 2020, 8 pages Doc 7259.
U.S. Appl. No. 16/538,068: Issue Notification dated May 20, 2020, 1 page Doc 7260
U.S. Appl. No. 16/862,351: Patent Application filed Apr. 29, 2020, 98 pages Doc 7261.
U.S. Appl. No. 16/862,351: Filing Receipt and Notice to File Missing Parts dated May 6, 2020, 9 pages Doc 7262.
U.S. Appl. No. 16/862,351: Response to Missing Parts and Preliminary Amendment filed Oct. 6, 2020, 18 pages Doc 7386.
PCT/US2017/031726: PCT Application filed May 9, 2017, 67 pages Doc 7346.
PCT/US2017/031726: Intl Search Report and Written Opinion dated Aug. 8, 2017, 67 pages Doc 7361 .
PCT/US2017/031726: Intl Preliminary Report on Patentability dated Nov. 22, 2018, 67 pages Doc 7363.
DE112017002374: DE Patent Application filed Nov. 8, 2018, 167 pages Doc 7285.
U.S. Appl. No. 15/590,562: Patent Application filed May 9, 2017, 130 pages Doc 7263.
U.S. Appl. No. 15/590,562: Filing Receipt and Informational Notice dated May 9, 2017, 7 pages Doc 7264.
U.S. Appl. No. 15/590,562: Notice of Publication dated Aug. 24, 2017, 1 page Doc 7265.
U.S. Appl. No. 15/590,562: Restriction Requirement dated Aug. 24, 2017, 7 pages Doc 7266.
U.S. Appl. No. 15/590,562: Response to Restriction Requirement and Preliminary Amendment filed Mar. 12, 2018, 15 pages Doc 7267.
U.S. Appl. No. 15/590,562: Non-final Office Action dated Sep. 20, 2018, 1 page Doc 7268.
U.S. Appl. No. 15/590,562: Amendment filed Dec. 18, 2018, 26 pages Doc 7269.
U.S. Appl. No. 15/590,562: Applicant Summary of Interview with Examiner dated Mar. 22, 2019, 8 pages Doc 7270.
U.S. Appl. No. 15/590,562: Notice of Allowance and Allowability dated Apr. 5, 2019, 19 pages Doc 7271.
U.S. Appl. No. 15/590,562: Request to Change Applicant Name filed May 24, 2019, 13 pages Doc 7272.
U.S. Appl. No. 15/590,562: Updated Filing Receipt dated Jun. 3, 2019, 9 pages Doc 7273.
U.S. Appl. No. 15/590,562: Issue Fee Payment filed Jul. 3, 2019, 6 pages Doc 7274.
U.S. Appl. No. 15/590,562: Issue Notification dated Jul. 31, 2019, 1 page Doc 7275.
U.S. Appl. No. 16/456,060: Patent Application filed Jun. 28, 2019, 141 pages Doc 7276.
U.S. Appl. No. 16/456,060: Filing Receipt and Notice to File Missing Parts dated Jul. 12, 2019, 8 pages Doc 7277.
U.S. Appl. No. 16/456,060: Response to Notice to File Missing Parts and Preliminary Amendment filed Sep. 12, 2019, 32 pages Doc 7278
U.S. Appl. No. 16/456,060: Updated Filing Receipt dated Sep. 17, 2019, 6 pages Doc 7279.
U.S. Appl. No. 16/456,060: Notice of Publication dated Dec. 26, 2019, 1 page Doc 7280.
U.S. Appl. No. 16/456,060: Non-final Office Action dated Jul. 20, 2020, 35 pages Doc 7281.
U.S. Appl. No. 16/456,060: Response to Non-final Office Action and Terminal Disclaimer dated Nov. 19, 2020, 14 pages Doc 7396.
U.S. Appl. No. 16/456,060: Notice of Allowance and Allowability dated Jan. 4, 2021, 9 pages Doc 7395.
U.S. Appl. No. 12/437,599 / MIT1: Patent Application filed May 8, 2009, 61 pages (MIT1) Doc 7287.
U.S. Appl. No. 12/437,599 / MIT1: Filing Receipt dated May 8, 2009, 3 pages (MIT1) Doc 7288.
U.S. Appl. No. 12/437,599 / MIT1: Notice of Publication dated Nov. 12, 2009, 1 page (MIT1) Doc 7289.
U.S. Appl. No. 12/437,599 / MIT1: Non-final Office Action dated Oct. 19, 2011, 35 pages (MIT1) Doc 7290.
U.S. Appl. No. 12/437,599 / MIT1: Amendment filed Apr. 13, 2012, 21 pages (MIT1) Doc 7291.
U.S. Appl. No. 12/437,599 / MIT1: Notice of Allowance and Allowability dated May 22, 2012, 16 pages (MIT1) Doc 7292.
U.S. Appl. No. 12/437,599 / MIT1: Examiner Initialed Interview Summary dated May 22, 2012, 1 page (MIT1) Doc 7293.
U.S. Appl. No. 12/437,599 / MIT1: Issue Fee Payment filed May 25, 2012, 5 pages (MIT1) Doc 7294.
U.S. Appl. No. 12/437,599 / MIT1: Issue Notification dated Jun. 13, 2012, 1 page (MIT1) Doc 7295.
U.S. Appl. No. 13/487,781 / MIT2: Patent Application filed Jun. 4, 2012, 51 pages (MIT2) Doc 7296.
U.S. Appl. No. 13/487,781 / MIT2: Filing Receipt and Notice to File Missing Parts dated Jun. 18, 2012, 5 pages (MIT2) Doc 7297.
U.S. Appl. No. 13/487,781 / MIT2: Response to Notice to File Missing Parts dated Aug. 20, 2012, 5 pages (MIT2) Doc 7298.
U.S. Appl. No. 13/487,781 / MIT2: Updated Filing Receipt dated Aug. 29, 2012, 5 pages (MIT2) Doc 7299.
U.S. Appl. No. 13/487,781 / MIT2: Preliminary Amendment filed Aug. 30, 2012, 14 pages (MIT2) Doc 7300.
U.S. Appl. No. 13/487,781 / MIT2: Updated Filing Receipt dated Sep. 6, 2012, 3 pages (MIT2) Doc 7300.
U.S. Appl. No. 13/487,781 / MIT2: Preliminary Amendment filed Sep. 21, 2012, 6 pages (MIT2) Doc 7302.
U.S. Appl. No. 13/487,781 / MIT2: Notice of Publication dated Dec. 13, 2012, 1 page (MIT2) Doc 7304.
U.S. Appl. No. 13/487,781 / MIT2: Notice of Allowance and Allowability dated Sep. 4, 2013, 22 pages (MIT2) Doc 7305.
U.S. Appl. No. 13/487,781 / MIT2: Issue Fee Payment and 312 Amendment filed Dec. 4, 2013, 23 pages (MIT2) Doc 7306.
U.S. Appl. No. 13/487,781 / MIT2: Response to 312 Amendment dated Dec. 27, 2013, 6 pages (MIT2) Doc 7307.
U.S. Appl. No. 13/487,781 / MIT2: Issue Notification dated Jan. 15, 2014, 1 page (MIT2) Doc 7308.
U.S. Appl. No. 13/599,037 / MIT3: Patent Application filed Aug. 30, 2012, 59 pages (MIT3) Doc 7309.
U.S. Appl. No. 13/599,037 / MIT3: Filing Receipt dated Sep. 17, 2012, 4 pages (MIT3) Doc 7310.
U.S. Appl. No. 13/599,037 / MIT3: Preliminary Amendment dated Sep. 21, 2012, 5 pages (MIT3) Doc 7311.
U.S. Appl. No. 13/599,037 / MIT3: Notice of Publication dated Dec. 27, 2012, 1 page (MIT3) Doc 7312.
U.S. Appl. No. 13/599,037 / MIT3: e-Terminal Disclaimer filed and accepted Dec. 5, 2013, 7 pages (MIT3) Doc 7313.
U.S. Appl. No. 13/599,037 / MIT3: Notice of Allowance and Allowability dated Jan. 2, 2014, 26 pages (MIT3) Doc 7314.
U.S. Appl. No. 13/599,037 / MIT3: Issue Fee Payment dated Feb. 28, 2014, 8 pages (MIT3) Doc 7315.
U.S. Appl. No. 13/599,037 / MIT3: Issue Notification dated Mar. 26, 2014, 1 page (MIT3) Doc 7316.
U.S. Appl. No. 14/251,917 / MIT4: Patent Application filed Apr. 14, 2014, 63 pages (MIT4) Doc 7317.
U.S. Appl. No. 14/251,917 / MIT4: Filing Receipt dated May 5, 2014, 3 pages (MIT4) Doc 7318.
U.S. Appl. No. 14/251,917 / MIT4: Notice of Publication dated Aug. 14, 2014, 1 page (MIT4) Doc 7319.
U.S. Appl. No. 14/251,917 / MIT4: Notice of Allowance and Allowability dated Mar. 2, 2015, 23 pages (MIT4) Doc 7320.
U.S. Appl. No. 14/251,917 / MIT4: 312 Amendment filed Apr. 22, 2015, 13 pages (MIT4) Doc 7321.
U.S. Appl. No. 14/251,917 / MIT4: Response to 312 Amendment filed Apr. 30, 2015, 3 pages (MIT4) Doc 7322.
U.S. Appl. No. 14/251,917 / MIT4: Issue Fee Payment filed May 1, 2015, 8 pages (MIT4) Doc 7323.
U.S. Appl. No. 14/251,917 / MIT4: Issue Notification dated May 1, 2015, 8 pages (MIT4) Doc 7324.
U.S. Appl. No. 14/708,903 / MIT5: Patent Application filed May 11, 2015, 57 pages (MIT5) Doc 7325.
U.S. Appl. No. 14/708,903 / MIT5: Filing Receipt and Notice of Missing Parts filed May 19, 2015, 5 pages (MIT5) Doc 7326.
U.S. Appl. No. 14/708,903 / MIT5: Response to Notice of Missing Parts filed May 19, 2015, 3 pages (MIT5) Doc 7327.
U.S. Appl. No. 14/708,903 / MIT5: Notice of Publication dated Oct. 1, 2015, 1 page (MIT5) Doc 7328.
U.S. Appl. No. 14/708,903 / MIT5: Non-final Office Action filed Oct. 1, 2015, 36 pages (MIT5) Doc 7329.
U.S. Appl. No. 14/708,903 / MIT5: Amendment and e-Terminal Disclaimer filed Jan. 3, 2017, 23 pages (MIT5) Doc 7330.
U.S. Appl. No. 14/708,903 / MIT5: Notice of Allowance and Allowability dated Feb. 23, 2017, 31 pages (MIT5) Doc 7331.
U.S. Appl. No. 14/708,903 / MIT5: Issue Fee Payment filed Apr. 24, 2017, 7 pages (MIT5) Doc 7332
U.S. Appl. No. 14/708,903 / MIT5: Issue Notification dated May 10, 2017, 1 page (MIT5) Doc 7333.
U.S. Appl. No. 14/708,903 / MIT5: Request for Certificate of Correction filed Apr. 14, 2018, 6 pages (MIT5) Doc 7334.
U.S. Appl. No. 14/708,903 / MIT5: Request for Certificate of Correction filed Apr. 14, 2018, 1 page (MIT5) Doc 7335.
U.S. Appl. No. 15/585,676 / MIT6: Patent Application filed May 3, 2017, 63 pages (MIT6) Doc 7336.
U.S. Appl. No. 15/585,676 / MIT6: Filing Receipt dated May 12, 2017, 4 pages (MIT6) Doc 7337.
U.S. Appl. No. 15/585,676 / MIT6: Notice of Publication dated Aug. 17, 2017, 1 page (MIT6) Doc 7338.
U.S. Appl. No. 15/585,676 / MIT6: Non-final Office Action dated Oct. 6, 2017, 34 pages (MIT6) Doc 7339.
U.S. Appl. No. 15/585,676 / MIT6: Amendment filed Apr. 5, 2018, 13 pages (MIT6) Doc 7340.
U.S. Appl. No. 15/585,676 / MIT6: Supplemental Amendment filed Apr. 5, 2018, 9 pages (MIT6) Doc 7341.
U.S. Appl. No. 15/585,676 / MIT6: Final Rejection dated Jul. 2, 2018, 9 pages (MIT6) Doc 7342.
U.S. Appl. No. 15/585,676 / MIT6: Notice of Abandonment dated Jan. 25, 2019, 2 pages (MIT6) Doc 7343.
PCT/US12/36455: PCT Application filed May 4, 2012, 59 pages Doc 7178.
PCT/US12/36455: International Search Report and Written Opinion dated Nov. 28, 2012, 7 pages Doc 7179.
PCT/US12/36455: International Preliminary Report an Patentability dated Nov. 5, 2013, 5 pages Doc 7180.
CN201280033387: First Search Report dated Jun. 24, 2015, 2 pages Doc 7052.
CN201280033387: First Office Action dated Jul. 2, 2015, 18 pages Doc 7053.
CN201280033387: Response to First Office Action dated Jan. 18, 2016, 11 pages Doc 7054.
CN201280033387.X: Supplementary Search Report dated Mar. 29, 2016, 1 page Doc 7055.
CN201280033387: Second Office Action dated Apr. 7, 2016, 13 pages Doc 7056.
CN201280033387: Response to Second Office Action filed Aug. 18, 2016, 25 pages Doc 7057.
CN201280033387: Supplementary Search Report dated Jan. 16, 2017, 1 page Doc 7058.
CN201280033387: Third Office Action dated Apr. 7, 2016, 22 pages Doc 7059.
CN201280033387: Response to Third Office Action filed Jun. 1, 2017, 22 pages Doc 7060.
CN201280033387: Fourth Office Action dated Sep. 8, 2017, 24 pages Doc 7061.
CN201280033387: Response to Fourth Office Action filed Jan. 5, 2018, 11 pages Doc 7062.
CN201280033387: Decision to Grant CN Patent dated Jun. 6, 2018, 11 pages Doc 7063.
CN201280033387: Rectified Decision to Grant CN Patent dated Jun. 27, 2018, 4 pages Doc 7064.
CN201280033387: Certificate of Patent dated Sep. 21, 2018, 2 pages Doc 7065.
CN201810954743: CN Patent Application as filed Aug. 21, 2018, 59 pages, Doc 7066.
CN201810954743: Filing Receipt dated Aug. 21, 2018, 1 page, Doc 7067.
CN201810954743: Notice of Publication dated Dec. 7, 2018, 33 pages, Doc 7071.
CN201810954743: Search Report dated Dec. 19, 2019, 2 pages, Doc 7068.
CN201810954743: First Office Action dated Dec. 30, 2019, 23 pages, Doc 7069.
CN201810954743: Office Action dated Dec. 30, 2019, 24 pages, Doc 7072.
CN201810954743: Response to First Office Action dated Jul. 14, 2020, 34 pages, Doc 7070.
CN201810954743: Second Office Action dated Sep. 21, 2020, 21 pages, Doc 7353.
EP12780024: EP Application as filed Dec. 3, 2013, 19 pages, Doc 7073.
EP12780024: Notice of Publication dated Feb. 12, 2014, 1 page, Doc 7074.
EP12780024: Search Report and Opinion dated Feb. 18, 2015, 7 pages, Doc 7075.
EP12780024: Rule 70 Communication dated Mar. 6, 2015, 1 page, Doc 7076.
EP12780024: Amendment filed Dec. 16, 2015, 13 pages, Doc 7077.
EP12780024: Article 94 Communication dated Feb. 23, 2016, 7 pages, Doc 7078.
EP12780024: Amendment in Response to Article 94 Communication filed Aug. 10, 2016, 23 pages, Doc 7079.
EP12780024: Article 94 Communication dated Jan. 3, 2017, 5 pages, Doc 7080.
EP12780024: Amendment in Response to Article 94 Communication filed Jun. 8, 2017, 5 pages, Doc 7081.
EP12780024: Intention to Grant dated Feb. 7, 2018, 103 pages, Doc 7082.
EP12780024: Request for Correction/Amendment of Granted Claims filed Mar. 13, 2018, 103 pages, Doc 7083.
EP12780024: Request for Correction/Amendment of Granted Claims filed Mar. 13, 2018, 103 pages, Doc 7084
EP12780024: Approval/Grant of Request for Correction/Amendment of Granted Claims dated Mar. 13, 2018, 3 pages, Doc 7085.
EP12780024: Revised Intention to Grant dated Jul. 4, 2018, 99 pages, Doc 7086.
EP12780024: Decision to Grant dated Jul. 19, 2018, 2 pages, Doc 7087.
EP12780024: Patent Certificate dated Aug. 15, 2018, 2 page, Doc 7088.
EP18188795: EP Patent Application as filed Aug. 13, 2018, 62 pages Doc 7046.
EP18188795: European Search Report dated Sep. 26, 2018, 3 pages Doc 7044.
EP18188795: Extended European Search Report and Opinion dated Oct. 9, 2018, 8 pages Doc 7045.
EP18188795: Notice of Publication dated Dec. 12, 2018, 2 pages Doc 7089.
EP18188795: Amendment and Request for Examination filed Jun. 17, 2019, 28 pages Doc 7047.
EP18188795: Article 94(3) Communication dated Nov. 11, 2019, 7 pages Doc 7041.
EP18188795: Amendment / Response to 94(3) Objection filed Aug. 21, 2020, 7 pages Doc 7048.
EP18188795: Decision on the Request for Further Processing under 135(3) EPC Sep. 1, 2020, 1 page Doc 7394.
KR20137032399: KR Patent Application filed May 12, 2013, 136 pages Doc 7090.
KR20137032399: Request for Amendment of Inventor Information filed Dec. 13, 2013, 2 pages Doc 7091.
KR20137032399: Amendment of Biographic Data entered Dec. 23, 2013, 4 pages Doc 7092.
KR20137032399: Office Action dated Nov. 18, 2014, 8 pages Doc 7093.
KR20137032399: Amendment to Claims filed Jan. 15, 2015, 21 pages Doc 7094.
KR20137032399: Response to Office Action dated Jan. 15, 2015, 15 pages Doc 7095.
KR20137032399: Final Office Action dated May 22, 2015, 5 pages Doc 7096.
KR20137032399: Amendment filed Jun. 17, 2015, 6 pages Doc 7098.
KR20137032399: Response to Final Office Action filed Jun. 17, 2015, 5 pages Doc 7099.
KR20137032399: Grant of Patent dated Jun. 24, 2015, 2 pages Doc 7100.
KR20137032399: Patent Certificate dated Sep. 23, 2015, 2 pages Doc 7101
KR20157016195: KR Divisional Application filed Jun. 17, 2015, 126 pages Doc 7097.
KR20157016195: Request for Amendment of Inventor Information filed Jul. 2, 2015, 2 pages Doc 7104.
KR20157016195: Amendment of Bibliographic Data dated Jul. 3, 2015, 4 pages Doc 7105.
KR20157016195: Amendment filed Feb. 29, 2015, 13 pages Doc 7106.
KR20157016195: Amendment filed Apr. 13, 2017, 15 pages Doc 7107.
KR20157016195: Request for Examination filed Apr. 20, 2017, 2 pages Doc 7108.
KR20157016195: Office Action dated Jul. 5, 2017, 9 pages Doc 7109.
KR20157016195: Final Office Action dated Dec. 20, 2017, 9 pages Doc 7110.
PCT/US16/22040: PCT Application filed Mar. 11, 2016, 71 pages, Doc 7173.
PCT/US16/22040: International Search Report and Written Opinion dated Jun. 20, 2016, 10 pages, Doc 7175.
PCT/US16/22040: Article 19 Amendment filed Sep. 22, 2016, 10 pages, Doc 7174.
PCT/US16/22040: International Preliminary Report on Patentability dated Sep. 19, 2017, 7 pages, Doc 7177.
CN201680027105.3: CN Application as filed Nov. 9, 2017, 167 pages, Doc 7181.
CN201680027105.3: First Office Action dated May 7, 2019, 22 pages, Doc 7182.
CN201680027105.3: Response to First Office Action filed Nov. 22, 2019, 25 pages, Doc 7184.
CN201680027105.3: Second Office Action dated Mar. 18, 2020, 12 pages, Doc 7183.
CN201680027105.3: Response to Second Office Action filed Aug. 3, 2020, 31 pages, Doc 7185.
DE112016001188: DE Application filed Sep. 13, 2017, 172 pages Doc 7186.
JP2017567041: JP Application filed Sep. 12, 2017, 68 pages, Doc 7189.
JP2017567041: Office Action dated May 25, 2020, 30 pages, Doc 7190.
JP2017567041: Response to Office Action filed Oct. 26, 2020, 87 pages, Doc 7384.
KR20177029575: KR Application filed Oct. 13, 2017, 169 pages Doc 7191.
KR20177029575: Request for Amendment to Signatory filed Oct. 23, 2017, 2 pages Doc 7193
KR20177029575: Allowed Amendment to Signatory dated Dec. 11, 2017, 4 pages Doc 7194.
TW105107546: TW Application filed Mar. 11, 2016, 65 pages, Doc 7195.
CN 201780030693: CN Patent Application filed Nov. 16, 2018, 129 pages Doc 7238.
CN 201780030693: Office Action dated Apr. 28, 2020, 15 pages Doc 7240.
CN 201780030693: Response to Office Action filed Nov. 12, 2020, 63 pages Doc 7385.
KR 10-2018-7030031: KR Patent Application filed Oct. 17, 2018, 169 pages Doc 7242.
CN201780042383: CN Patent Application filed Jan. 7, 2019, 275 pages Doc 7282.
CN201780042383: Office Action dated Apr. 28, 2020, 16 pages Doc 7284.
CN201780042383: Response to Office Action filed Nov. 13, 2020, 19 pages Doc 7387.
U.S. Appl. No. 15/138,692: List of References Cited by Examiner in U.S. Appl. No. 15/138,692 dated Mar. 10, 2017, 1 page.
U.S. Appl. No. 15/138,692: Examiner initialed SB08/1449 document listing from U.S. Appl. No. 15/138,692 considered Mar. 3, 2017, 6 pages.
U.S. Appl. No. 15/138,692: Examiner initialed SB08/1449 document listing from U.S. Appl. No. 15/138,692 considered Mar. 3, 2017, 1 page.

Related Publications (1)

	Number	Date	Country
	20200127557 A1	Apr 2020	US

Provisional Applications (4)

Number	Date	Country
62132701	Mar 2015	US
61482838	May 2011	US
61548360	Oct 2011	US
61577271	Dec 2011	US

Continuations (4)

	Number	Date	Country
Parent	15813546	Nov 2017	US
Child	16534196		US
Parent	15068985	Mar 2016	US
Child	15813546		US
Parent	13771904	Feb 2013	US
Child	14513747		US
Parent	PCT/US2012/036455	May 2012	US
Child	13771904		US

Continuation in Parts (1)

	Number	Date	Country
Parent	14513747	Oct 2014	US
Child	15068985		US

DC-DC converter with modular stages

Information

Patent Number

Date Filed

Date Issued

Inventors

Original Assignees

Examiners

Agents

CPC

Field of Search

CPC

International Classifications

Abstract