Patent Application
20160226385
The present disclosure relates to dc-dc power converters for use in data communications systems. More specifically, the present disclosure relates to power converters that provide a fixed gain with high efficiency step-down conversion for line cards and other applications.
This section provides background information related to the present disclosure which is not necessarily prior art.
Large telecommunication (telecom) installations traditionally use a negative or −48 volt (V) battery backup system. A negative voltage system and specifically a −48V system developed for a variety of reasons. One reason for a negative voltage system is that there is less corrosion of copper cables compared to a positive voltage system. Grounding the positive battery terminal provides cathodic protection. The output voltage level, historically, was the result of connecting four 12V batteries in series. Thus, a standard −48V telecom power distribution architecture developed. In some places −60V systems developed, i.e. from connecting five batteries together.
As data communications (datacom) developed the industry adopted the −48V legacy architecture. This is despite datacom systems generally not using battery backup and the reasons for using negative voltage are not a concern in datacom. The reasons for leveraging the −48V architecture include the wide availability and therefore relatively low cost of rectifiers and power converters designed for −48V applications. In addition, typical datacom and modern telecom networking applications have a regulated −48V bus eliminating large voltage variations of historical battery operated systems.
Datacom and modern telecom systems use fast switching digital processor operating at a variety of low voltage supply levels, e.g. from about 1V to 5V. In addition, the variety of processors and digital equipment led to complex power-up and power-down sequencing requirements. This led to a distributed architecture where a regulated −48V dc (direct current) supply was stepped down to a lower voltage, e.g. +12V. Point-of-load (POL) circuits then further stepped the +12V to the required voltage supply level. The POL circuits may include dc-dc step-down regulators, e.g. voltage regulator modules (VRM) to accommodate every increasing current slew rate requirements for the digital processors. Non-isolated POL circuit regulators are typically used because they easily and economically meet the architecture requirements, including the sequencing requirements. As system power demands increased, a distributed system 100 of providing a relatively low current −48V from ac-dc front end power supply 102 to multiple line cards 104, 106, 108 evolved, as shown in
A typical prior art unregulated converter 110 is an unregulated Intermediate Bus Converter (IBC) shown in
As recognized by the inventor, various parasitic inductances that are created during operation of converter 110, e.g. transformer leakage inductance, layout and component lead inductance, etc. slows rising output currents. In addition, the dead transition time between the switching transitions of Q1, Q2 causes significant ripple current stress on output capacitor C2 of about 40% of the load current. For example a 50 amp (A) rated design produces about 20 A rms (root mean square) on C2, with similar stress on C1. Accordingly, the inventor has recognized a need for an efficient dc-dc power converter with fast transient response with appropriate circulating chassis current control with or without isolation (aka galvanic isolation).
This section provides a general summary of the disclosure, and is not a comprehensive disclosure of its full scope or all of its features.
A dc-dc power converter example is disclosed for use in data communications and telecommunications networks. The power converter is for connection between a front end ac-dc power supply and a point-of-load circuit. The dc-dc power converter may include one of an unregulated flyback converter and an unregulated buck converter. Each of the flyback and the buck converters has an input for connection to an output of the front end ac-dc power supply and an output for connection to an input of the point-of-load circuit. A switch controller has an input connected to either the flyback converter input or the buck converter input. The switch controller has an output connected to one of a switch of the flyback converter and a switch of the buck converter.
Further aspects and areas of applicability will become apparent from the description provided herein. It should be understood that various aspects of this disclosure may be implemented individually or in combination with one or more other aspects. It should also be understood that the description and specific examples herein are intended for purposes of illustration only and are not intended to limit the scope of the present disclosure.
The drawings described herein are for illustrative purposes only of selected embodiments and not all possible implementations, and are not intended to limit the scope of the present disclosure.
Corresponding reference numerals indicate corresponding parts throughout the several views of the drawings.
Example embodiments will now be described more fully with reference to the accompanying drawings.
A dc-dc power converter 300 for use in data communications and telecom networks is described. The power converter 300 is for connection between a front end ac-dc power supply 102 and a point-of-load circuit (POL) 112, as shown in
The dc-dc power converter 300 may include one of an unregulated flyback converter 400 (shown in
If a polarity inversion is required due to a negative power supply from front end power supply 102′ and a non-isolated converter is permitted, an example flyback converter 400 may include input 302 for connection to output 304 of the front end ac-dc power supply 102′ and output 306 for connection to an input 308 of the POL 112.
As shown in
By appropriately driving switch Q4 with switch controller 414, a desired +12V output at 306 may be achieved from a −48V input at 302. The inductor L4 stores energy when switch Q4 is on and discharges in to the load, at 306. When Q4 is off energy is stored in output capacitor C4. Using the well-known inductor voltage balance principal where the ratio of output voltage to input voltage is equal to the ratio of the Q4 on-time to Q4 off-time per cycle, the duty cycle of the switch Q4 will be 20%, with an L4 discharge duty cycle of 80%. The flyback converter 400 should work well at lower powers such as 80-120 Watts (W) and provide excellent power conversion efficiency, e.g. up to about 98%.
If a positive front end power supply 102′ is permitted, an example buck converter 500 may include input 303 for connection to output 304 of the front end ac-dc power supply 102′ and output 307 for connection to input 308 of the POL 112.
As shown in
By appropriately driving switch Q5 with switch controller 514, a desired +12V output at 307 may be achieved from a +48V input at 303. The buck converter 500 provides the necessary step down function. Since regulation is not needed, the duty cycle of the signal driving Q5 may be fixed to achieve desired step down ratio. A duty cycle of 25% will result in the 12V output, where the duty cycle is equal to the ratio of output voltage to input voltage (12V:48V). However, the large off-time of 75% may require a large inductor L5 and output capacitor C5, negatively impacting cost and a power density of the converter 500.
Each of the flyback converter 400 switch Q4 and the buck converter 500 switch Q5 may be a MOSFET (metal-oxide semiconductor field-effect transistor).
Each of the flyback converter 400 and the buck converter 500 may be non-isolated converters, if galvanic isolation is not required.
If galvanic isolation is required a flyback converter 600 may be used, as shown in
If higher output power levels are required, e.g. above 150 W, ripple current stresses on the output capacitor C4 or C5 will significantly increase because of the increasing charge and discharge levels during every switching cycle. Therefore, as the output power levels increase the size of the output capacitor C4 or C5 increases, negatively affecting cost and the power density.
As output power level requirements rise, the ripple stresses on the output capacitors C4, C5 also significantly rise, hindering efficiency and power density. To increase efficiency and the achievable power density for high output power levels, e.g. up to 3-4 times compared to a single phase approach, a flyback converter 700 or a buck converter 800 may include one of multiple interleaved flyback power rails and multiple interleaved buck power rails, respectively, as shown in
If the front end ac-dc power supply 102′ outputs a negative voltage, the dc-dc power converter 300 may include the flyback converter 700 for providing an inverted, positive voltage at the flyback converter output 306.
If the front end ac-dc power supply 102′ is permitted to output a positive voltage, the dc-dc power converter 300 may include the buck converter 800.
In the example of
In the examples of
The efficiency of the
The buck converter example of
The same factors for the
An example operation of
Because of the excellent ripple cancellation achieved through interleaving, the output capacitor C4 may be small. However, the energy source in this example converter is inductive; possibly unacceptably limiting a response time to fast transient load changes. To achieve a faster response time a larger capacitor may be required.
In addition, some 48V datacom applications require that the dc-dc converter to handle an input voltage change of ±10% or a range 43V to 53V. Therefore, design specifications may require use of 75V or 80V MOSFETS for the control switches and synchronous rectifier devices. Telecom applications input voltage variability may be even wider, e.g. up to 72V, requiring use of 100V control switches and synchronous rectifier devices. These higher voltage MOSFET devices have relatively slow body diodes causing unacceptable reverse recovery losses at each control switch turn-on and this conduction of the body diode of the synchronous rectifier MOSFET cannot be avoided. These losses may unacceptably deteriorate efficiency at higher switching frequencies, e.g. above 100 kHz.
It is known that the above issues may be significantly mitigated via soft switching or discontinuous current mode (DCM) operation. However, soft switching circuits add to the complexity and cost and DCM operation may produce unacceptably high peak currents. Boundary mode conduction (BCM) also addresses this issue but also adds complexity, cost, and may result in unacceptably large operating frequency variation. In addition, implementing multi-phase operation in BCM is complicated. However, these loss issues may be addressed by the
In switching applications, a net average voltage across the inductors is zero over a full cycle, i.e. the volt·second product across each inductor is balanced. The concept is explained in detail below using an example of a single phase of
In
In the next cycle, because of the higher output voltage, L4 discharges earlier to maintain the volt·second balance. If Q46 is closed during the entire Q4 off-time, the L4 current reverses and L4 charges in a reverse direction by drawing energy from C4. Thus, when L4 discharges during Q4 off-time, the current flows from Q46's source to drain in Q2, as in a rectifier diode. Once L4 completely discharges, the L4 current again reverses and now flows from drain to source in Q4. When current flows from Q46's drain to source, Q46 operates as a switch, rather than a rectifier. When Q46 turns off and just before a next activation of Q4, L4's stored energy is returned to the energy input source at 302, because of the current reversal. The coordination of the controls driving Q4 and Q46 are timed so that the body diode of Q4 conducts. When Q4 is turned on, Q4 initially operates as synchronous rectifier as current flows from Q4's source to drain until all of L4's stored energy is transferred to the input source at 302. After L4 has discharged, L4's current again reverses and L4 starts to charge and store energy from the input source at 302 through switch Q4.
During CCM operation, the following energy balance equation is well known:
V
in
*T
Q4on
=V
out
*T
Q46on (1)
Where Vin is the input voltage at 302, TQ4on is the Q4 on-time, Vout is the output voltage at 306, and TQ46on is the Q46 on-time.
If TQ4on=0.20 s, TQ46on=0.8 s, and Vin=48, then Vout=12V. Thus, the example operation ensures an output voltage of 12V regardless of load, because L4 is forced to operate in CCM. Designing the L4 value and switching operating frequency such that L4's peak current is slightly more than twice the required load current, e.g. around 10% more ensures there is excess energy in L4 and that above described operation occurs over the entire load range; if Q4 is operated at duty cycle D then Q46 is operated in a complementary manner, at duty cycle of (1-D), i.e. out of phase with respect to Q46. To prevent unacceptable current spikes, it is known that a short transition delay (dead time) between the transition of Q4 and the transition of Q46 is desired.
If the load current from a 12V output is 10 A, then for boundary mode operation, the peak (also referred to as peak-to-peak) inductor current will be 10 A÷0.5÷0.8=25 A, as is well-known based on triangular waveforms. L4 is exactly discharged and no reverse current will follow through L4, during Q4 off-time. However, if the operating frequency and L4's inductor value are chosen such that the peak current is 27 A, then a −2 A reverse current will build in L4 and Q46. When Q46 turns off, Q46's drain voltage rises as the L4's reverse stored energy transfers to the input source at 302. In addition, during Q46's off-time, the body diode of Q46 recovers in lossless manner. Of course, during transition, the body diode of Q4 conducts because of the reverse current direction; but Q4 also recovers in a lossless manner when Q4 turns off, because of the resonant action of L4. It is well known to keep a transition time between switching of Q4 and Q46 small, to minimize body diode conduction losses and such should be applied to this example.
From the above explanation, a dc-dc converter using synchronous rectifiers, whether single or multiple phase, may benefit from a design where a peak current of the inductor is slightly more than twice a load current for allowing a reverse current flow in the inductor. Such a design has higher power conversion efficiency at higher switching operating frequencies compared to other designs. Depending on the application and devices chosen, a peak current that is “slightly more”, may be a peak current twice the load current plus about ten percent of twice the load current. Of course, other values may also be considered “slightly more”, depending on the specifications and performance demands expected for an intended application.
Regarding the buck converter examples of
The example of
One potential drawback of the examples disclosed with respect to
If efficiency at lighter loads cannot be compromised, then the examples shown in
In the examples of
The load currents may be sensed using a sense resistance or any other type of current sensor. For example, the load current may be sensed by placing a current sense resistor, R1, in series with output 306 or 307 and determining the load current using sensors 1100 or 1200. When the load is below 50%, the frequency is doubled at the beginning of a new cycle. If the duty cycle is 20% and the operating frequency is 100 kHz at full load, doubling the operating frequency, to 200 kHz, at the same duty cycle reduces the on-time of switch Q4 or Q5 by half. The result is that only half the peak inductor current is generated compared to full load conditions while still ensuring the peak current is higher than needed to support the load and create reverse current flows through the synchronous rectifiers Q46 or Q55. The rest of the operation is the same as described above but with improved efficiency at conditions below half-load.
It is also possible to create several operating frequency change steps. For example, the switch controller may operate at 20% duty cycle at 100 kHz above 50% load, 20% duty cycle at 200 kHz between 50% and 25% load, and 20% duty cycle at 400 kHz below 25% load. Additional operating frequency steps may further improve the converters' efficiencies as the load drops. These frequency step changes are easily implemented with digital control and avoid complex control loops and stability issues. After detecting a change in a current threshold, the frequency changes should be applied at a start of a new cycle. The disclosed frequency doubling method ensures very fast transient response to load changes and reduces losses at lighter loads. When this concept is applied to multi-phase interleaved designs, a new cycle begins when the power rail operating at zero phase begins operation.
There are several ways to detect load changes and sensing the output current using current sensor is only one example. The load current may be indirectly sensed or estimated by sensing input current. Load current may also be detected by sensing a lack of body diode conduction of each control switch at the instance of turn on. As explained above, the example design ensures reverse current in the inductor to force conduction of the switch body diode. When load current increases, the inductor may enter CCM and the inductor current may not reverse. Detecting this lack of current reversal may also be used to indicate an increase in load current.
The example disclosure relative to
It is also possible to drop some of the phases, of a converter having multiple interleaved power rails, at light loads, to improve efficiency and dynamic response. For example, in a converter having an N number of phases (or interleaved power rails), at light loads, the switch controller of the converter could force the converter to operate with only N-M phases, where M is smaller than N. For example, if a converter has four phases with each power rail operating at a 90° phase shift, N=4. At light loads, e.g. below 25%, two of the phases may be turned off and thus M=2 with a resultant phase shift adjustment from 90° to 180°. When the load increases above 25% of full load, all four phases may be enabled again, with a phase shift change back to 90°. This example increases the converters' dynamic frequency response without changing the operating frequency. Another way of stating this is that the converter has an N number of interleaved power rails and the switch controller, at least at one predetermined load level less than a full load, causes the converter to operate an N-M number of interleaved power rails, where M is smaller than N.
The foregoing description of the embodiments has been provided for purposes of illustration and description. It is not intended to be exhaustive or to limit the disclosure. Individual elements or features of a particular embodiment are generally not limited to that particular embodiment, but, where applicable, are interchangeable and can be used in a selected embodiment, even if not specifically shown or described. The same may also be varied in many ways. Such variations are not to be regarded as a departure from the disclosure, and all such modifications are intended to be included within the scope of the disclosure.
Example embodiments are provided so that this disclosure will be thorough, and will fully convey the scope to those who are skilled in the art. Numerous specific details are set forth such as examples of specific components, devices, and methods, to provide a thorough understanding of embodiments of the present disclosure. It will be apparent to those skilled in the art that specific details need not be employed, that example embodiments may be embodied in many different forms and that neither should be construed to limit the scope of the disclosure. In some example embodiments, well-known processes, well-known device structures, and well-known technologies are not described in detail.
The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting. As used herein, the singular forms “a,” “an,” and “the” may be intended to include the plural forms as well, unless the context clearly indicates otherwise. The terms “comprises,” “comprising,” “including,” and “having,” are inclusive and therefore specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. The method steps, processes, and operations described herein are not to be construed as necessarily requiring their performance in the particular order discussed or illustrated, unless specifically identified as an order of performance. It is also to be understood that additional or alternative steps may be employed.
Although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms may be only used to distinguish one element, component, region, layer or section from another region, layer or section. Terms such as “first,” “second,” and other numerical terms when used herein do not imply a sequence or order unless clearly indicated by the context. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the example embodiments.
This application claims the benefit of U.S. Provisional Application No. 62/111,430 filed Feb. 3, 2015. The entire disclosure of the above application is incorporated herein by reference.
| Number | Date | Country | |
|---|---|---|---|
| 62111430 | Feb 2015 | US |
