TREA

DC free code design with state dependent mapping

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Information

  • Patent Application
  • 20040066318
  • Publication Number
    20040066318
  • Date Filed
    March 24, 2003
    21 years ago
  • Date Published
    April 08, 2004
    20 years ago
Information
Abstract
A method of encoding digital information in a system is provided. The method includes receiving a sequence of user-bits and calculating a running digital sum (RDS) of the system. Also, a code word is generated based on the sequence of user bits and the RDS of the system to maintain the RDS of the system calculated with the code word to within a selected range. In one embodiment, the sequence of user bits is 19 bits and the code word is 20 bits.
Description


FIELD OF THE INVENTION

[0002] The present invention relates to communicating digital data through a communication channel. In particular, the present invention relates to encoding and decoding techniques for DC free codes.


BACKGROUND OF THE INVENTION

[0003] In the field of digital communications, digital information is typically prepared for transmission through a channel by encoding it. The encoded data is then used to modulate a transmission to the channel. A transmission received from the channel is then typically demodulated and decoded to recover the original information.

[0004] The encoding of the digital data serves to improve communication performance so that the transmitted signals are less corrupted by noise, fading, or other interference associated with the channel. The term “channel” can include media such as transmission lines, wireless communication and information storage devices such as magnetic disc drives. In the case of information storage devices, the signal is stored in the channel for a period of time before it is accessed or received. Encoding can reduce the probability of noise being introduced into a recovered digital signal when the encoding is adapted to the known characteristics of the data and its interaction with known noise characteristics of a communication channel.

[0005] In typical encoding arrangements, data words of m data bits are encoded into larger code words of n code bits, and the ratio m/n is known as the code rate of the encoding arrangement. Decreasing the code rate reduces the complexity of the encoder/decoder and can also improve error correction capability, however, a decreased code rate also increases energy consumption and slows communication.

[0006] Further, it is often desirable for encoded channel sequences to have a spectral null at zero frequency. Such sequences are said to be DC free and particularly found to enhance the performance in perpendicular magnetic recording. Given a sequence of binary digits, wherein a binary digit “1” is plus one (+1) and a binary “0” is minus one (−1), the sequence will be DC free if a running digital sum of the bipolar sequence is bounded. The running digital sum is the sum of all values in a bipolar sequence. When the variation of the running digital sum is kept to a small value, it is known to have a tight or small bound. A tighter bound improves the performance of the channel.

[0007] There is a need to provide improved DC free coding techniques that reduce the probability of noise being introduced to the system and have optimal code rates. Various embodiments of the present invention address these problems, and offer other advantages over the prior art.


SUMMARY OF THE INVENTION

[0008] A method of encoding digital information in a system is provided. The method includes receiving a sequence of user bits and calculating a running digital sum (RDS) of the system. In addition, a code word is generated based on the sequence of user bits and the RDS of the system to maintain the RDS of the system calculated with the code word to within a selected range.

[0009] Another embodiment of the present invention relates to a system for generating a code word from a sequence of user bits. The system has an input circuit adapted to receive the sequence of user bits and a calculation circuit adapted to calculate the running digital sum (RDS) of the system. An encoder is also provide that is adapted to generate a code word based on the sequence of user bits and the RDS of the system to maintain the RDS of the system calculated with the code word to within a selected range.

[0010] Another aspect of the present invention is a method of decoding a code word. The method includes receiving a code word, identifying a state value associated with the code word, and generating a sequence of user bits based on the code word and the state value.

[0011] Yet another aspect of the present invention is a digital communication system. The system includes a communication channel, an encoder system and a decoder system. The encoder system includes an input circuit adapted to receive the sequence of user bits, a calculation circuit adapted to calculate the running digital sum (RDS) of the system, an encoder adapted to generate a code word based on the sequence of user bits and the RDS of the system to maintain the RDS of the system calculated with the code word to within a selected range and an output circuit adapted to transmit the code word to the communication channel. The decoder system includes an input circuit adapted to receive a code word from the communication channel, a state evaluator adapted to identify a state value associated with the code word, and a decoder adapted to generate a sequence of user bits based on the code word and the state value.






[0012] Other features and benefits that characterize embodiments of the present invention will be apparent upon reading the following detailed description and review of the associated drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0013]
FIG. 1 is an isometric view of a disc drive.

[0014]
FIG. 2 is a flow diagram of a method of encoding information according to the present invention.

[0015]
FIG. 3 is a block diagram of an encoder.

[0016]
FIG. 4 is a block diagram of an encoder input circuit.

[0017]
FIG. 5 is a block diagram of a first encoder circuit.

[0018]
FIG. 6 is a block diagram of a second encoder circuit.

[0019]
FIG. 7 is a block diagram of a third encoder circuit.

[0020]
FIG. 8 is a block diagram of an encoder for generating a first segment of a code word.

[0021]
FIG. 9 is a block diagram of an encoder for generating a second segment of a code word.

[0022]
FIG. 10 is a block diagram of an encoder output circuit.

[0023]
FIG. 11 is a flow diagram of a method of decoding digital information.

[0024]
FIG. 12 is a block diagram of a decoder.

[0025]
FIG. 13 is a block diagram of a decoder input circuit.

[0026]
FIG. 14 is a block diagram of a decoder for decoding a first segment of a code word.

[0027]
FIG. 15 is a block diagram of a decoder for decoding a second segment of a code word.

[0028]
FIG. 16 is a block diagram of a decoder output circuit.






DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

[0029]
FIG. 1 is a perspective view of a magnetic disc drive 100 in which the present invention is useful. Disc drive 100 communicates with a host system 101 and includes a housing with a base 102 and a top cover (not shown). Disc drive 100 further includes a disc pack 106, which is mounted on a spindle motor (not shown), by a disc clamp 108. Disc pack 106 includes a plurality of individual discs, which are mounted for co-rotation about central axis 109. Each disc surface has an associated head, which is mounted to disc drive 100 for communication with the disc surface. In the example shown in FIG. 1, heads 110 are supported by suspensions 112 which are in turn attached to track accessing arms 114 of an actuator 116. The actuator shown in FIG. 1 is of the type known as a rotary moving coil actuator and includes a voice coil motor (VCM), shown generally at 118. Voice coil motor 118 rotates actuator 116 with its attached heads 110 about a pivot shaft 120 to position heads 110 over a desired data track along an arcuate patch 122 between a disc inner diameter 124 and a disc outer diameter 126. Voice coil motor 118 operates under control of internal circuitry 128.

[0030] The heads 110 and rotating disc pack 106 form a communication channel that can receive digital data and reproduce the digital data at a later time. Write circuitry within internal circuitry 128 receives data, typically from a digital computer, and then encodes data in code words adapted to the communication channel. The encoded data is then used to modulate a write current provided to a write transducer in the head 110. The write transducer and the head 110 causes successive code words to be encoded on a magnetic layer on disc pack 106. At a later time, a read transducer in the head recovers the successive code words from the magnetic layer as a serial modulated read signal. Read circuitry within internal circuitry 128 demodulates the read signal into successive parallel code words. The demodulated code words are then decoded by decoder circuitry within circuitry 128, which recovers the digital data for use, by host system 101, at a later time.

[0031] In order to encode data that is written onto a magnetic layer on disc pack 106, a method according to the present invention is used. According to one embodiment of the present invention, a 19-bit word of user data is encoded into a 20-bit code word. In order to generate the 20-bit code word, the 19-bit data word is broken down into smaller fragments. The fragments are rearranged and mapped into two 10-bit segments according to a lookup table and a mapping table. In one embodiment, a goal of the method is to maintain the running digital sum of the system within a selected range of +/31 4, calculated after each 20-bit code word. The selected range represents a bound on the running digital sum of the system. Maintaining the running digital sum within the selected range improves the performance of disc drive 100. Upon decoding of the code word, the code word is evaluated in order to determine a state value. Using the state value, the code word can be decoded using the state value to render the sequence of user bits.

[0032]
FIG. 2 illustrates a flow diagram of a method 200 of encoding information according to the present invention. According to method 200, a 19-bit data word is received at step 202. At step 204, the method 200 accesses a current state value that has been calculated after each code word that is generated. The current state is the running digital sum of the system. The initial state is calculated as zero. Depending on the current state, the 19-bit data word is broken up into three fragments according to a lookup table at step 206. The assembly and format of the lookup table is discussed below. Next, at step 208, a ‘g’ group and an ‘h’ group is selected based on the first fragment as determined in step 206. These groups are chosen in order to maintain the running digital sum within a range of +/−4. Once the respective groups are obtained, the second fragment is mapped into a group 10-bit segment at step 210. The mapping is performed according to a mapping table as discussed below. In step 212, the third fragment is mapped into an ‘h’ group 10-bit segment according to a mapping table. The ‘g’ group and ‘h’ group segments are then combined, at step 214, to form a 20-bit code word that maintains the running digital sum of the system within +/−4. The code word is output, for example to a disc, at step 216.

[0033] In order to generate the lookup table, it is important to investigate the running digital sums for 20-bit code words. By separating 20-bit code words into 10-bit segments, the design of a rate 19/20 DC free code is simplified. For a given a 10 bit pattern, the pattern may have a running digital sum of −10, −8, −6, −4, −2, 31 0, 2, 4, 6, 8 or 10. Table 1 shows 10 bit patterns grouped according to their respective digital sums. The groups having running digital sums of 0, 2, 4, 6 and 8 are shown. Since the running digital sums of −2, −4, −6 and −8 are merely the inverse of the corresponding patterns with the positive running digital sum, only the groups with a positive running digital sum are shown. The patterns having running digital sums of 10 and −10 are not used. The table shows the 10-bit patterns in hexadecimal.
1TABLE 1A Grouping Table that groups 10-bit segments according to theirrespective running digital sums.Group gb:There are 252 10-bit patterns with RDS = 001F02F03703B03D03E04F05705B05D05E06706B06D06E07307507607907A07C08F09709B09D09E0A70AB0AD0AE0B30B50B60B90BA0BC0C70CB0CD0CE0D30D50D60D90DA0DC0E30E50E60E90EA0EC0F10F20F40F810F11711B11D11E12712B12D12E13313513613913A13C14714B14D14E15315515615915A15C16316516616916A16C17117217417818718B18D18E19319519619919A19C1A31A51A61A91AA1AC1B11B21B41B81C31C51C61C91CA1CC1D11D21D41D81E11E21E41E81F020F21721B21D21E22722B22D22E23323523623923A23C24724B24D24E25325525625925A25C26326526626926A26C27127227427828728B28D28E29329529629929A29C2A32A52A62A92AA2AC2B12B22B42B82C32C52C62C92CA2CC2D12D22D42D82E12E22E42E82F030730B30D30E31331531631931A31C32332532632932A32C33133233433834334534634934A34C35135235435836136236436837038338538638938A38C3913923943983A13A23A43A83B03C13C23C43C83D03E0Group gc:There are 210 10-bit patterns with RDS = +203F05F06F07707B07D07E09F0AF0B70BB0BD0BE0CF0D70DB0DD0DE0E70EB0ED0EE0F30F50F60F90FA0FC11F12F13713B13D13E14F15715B15D15E16716B16D16E17317517617917A17C18F19719B19D19E1A71AB1AD1AE1B31B51B61B91BA1BC1C71CB1CD1CE1D31D51D61D91DA1DC1E31E51E61E91EA1EC1F11F21F41F821F22F23723B23D23E24F25725B25D25E26726B26D26E27327527627927A27C28F29729B29D29E2A72AB2AD2AE2B32B52B62B92BA2BC2C72CB2CD2CE2D32D52D62D92DA2DC2E32E52E62E92EA2EC2F12F22F42F830F31731B31D31E32732B32D32E33333533633933A33C34734B34D34E35335535635935A35C36336536636936A36C37137237437838738B38D38E39339539639939A39C3A33A53A63A93AA3AC3B13B23B43B83C33C53C63C93CA3CC3D13D23D43D83E13E23E43E83F0Group gd:There are 120 10-bit patterns with RDS = +407F0BF0DF0EF0F70FB0FD0FE13F15F16F17717B17D17E19F1AF1B71BB1BD1BE1CF1D71DB1DD1DE1E71EB1ED1EE1F31F51F61F91FA1FC23F25F26F27727B27D27E29F2AF2B72BB2BD2BE2CF2D72DB2DD2DE2E72EB2ED2EE2F32F52F62F92FA2FC31F32F33733B33D33E34F35735B35D35E36736B36D36E37337537637937A37C38F39739B39D39E3A73AB3AD3AE3B33B53B63B93BA3BC3C73CB3CD3CE3D33D53D63D93DA3DC3E33E53E63E93EA3EC3F13F23F43F8Group ge:There are 45 10-bit patterns with RDS = +60FF17F1BF1DF1EF1F71FB1FD1FE27F2BF2DF2EF2F72FB2FD2FE33F35F36F37737B37D37E39F3AF3B73BB3BD3BE3CF3D73DB3DD3DE3E73EB3ED3EE3F33F53F63F93FA3FCGroup gf:There are 10 10-bit patterns with RDS = +81FF2FF37F3BF3DF3EF3F73FB3FD3FE


[0034] Each of the groups in Table 1 is further divided into subgroups of various sizes (see Table 2). The various subgroups map bits of user fragments determined in step 206, depending on the size of the user data fragment, into a 10-bit code word. For example, a user data fragment of 7 bits is mapped into a 7-bit subgroup, for example subgroup gb7. This group will be utilized when the second fragment at step 210 has a length of 7 bits. Group gb is divided into subgroups gb7, gb6, gb5 gb4 gb3 and gb2 with sizes of 128=27, 64=26, 32=25, 16=24, 8=23 and 4=22 respectively. Group gc is divided into subgroups gc7, gc6, gc4 and gc1 with sizes of 128=27, 64=26, 16=24 and 2=21 respectively. Group gd is divided into subgroups gd6,gd5, gd4 and gd3 with sizes of 64=26, 32=25, 16=24 and 8=23 respectively. Group ge is divided into subgroups ge5 and ge3 with sizes of 32=25 and 8=23 respectively. Group gf is divided into subgroups gf3 and gf1 with sizes of 8=23 and 2=21 respectively. The size of each subgroup is of a size 2m, which allows mapping of user data fragments of size m bits. Table 2 shows each of the various subgroups. In the table, the mapping is shown in the form “xxx:yyy”, wherein “xxx” is a user data fragment that is mapped into a 10-bit code word “yyy”. The values in the table are expressed in hexadecimal.
2TABLE 2Mapping Table of user fragments into ‘g’ group words.Subgroup gb7: (mapping of 7-bit data word into 10-bit code word)000:21B001:233002:235003:236004:22B005:239006:23A007:23C008:24B009:25300A:25500B:25600C:28B00D:25900E:25A00F:25C010:21D011:263012:265013:266014:22D015:269016:26A017:26C018:24D019:29301A:29501B:29601C:28D01D:29901E:29A01F:29C020:21E021:2A3022:2A5023:2A6024:22E025:2A9026:2AA027:2AC028:24E029:2C302A:2C502B:2C602C:28E02D:2C902E:2CA02F:2CC030:271031:2B1032:2D1033:2E1034:272035:2B2036:2D2037:2E2038:274039:2B403A:2D403B:2E403C:27803D:2B803E:2D803F:2E8040:11B041:133042:135043:136044:12B045:139046:13A047:13C050:11D051:163052:165053:166054:12D055:169056:16A057:16C058:14D059:19305A:19505B:19605C:18D05D:19905E:19A05F:19C060:11E061:1A3062:1A5063:1A6064:12E065:1A9066:1AA067:1AC068:14E069:1C306A:1C506B:1C606C:18E06D:1C906E:1CA06F:1CC070:171071:1B1072:1D1073:1E1074:172075:1B2076:1D2077:1E2078:174079:1B407A:1D407B:1E407C:17807D:1B807E:1D807F:1E8Subgroup gb6: (mapping of 6-bit data word into 10-bit code word)000:331001:313002:315003:316004:332005:319006:31A007:31C008:334009:32300A:32500B:32600C:33800D:32900E:32A00F:32C010:3C1011:343012:345013:346014:3C2015:349016:34A017:34C018:3C4019:38301A:38501B:38601C:3C801D:38901E:38A01F:38C020:0CE021:0EC022:0EA023:0E9024:0CD025:0E6026:0E5027:0E3028:0CB029:0DC02A:0DA02B:0D902C:0C702D:0D602E:0D502F:0D3030:03E031:0BC032:0BA033:0B9034:03D035:0B6036:0B5037:0B3038:03B039:07C03A:07A03B:07903C:03703D:07603E:07503F:073Subgroup gb5: (mapping of 5-bit data word into 10-bit code word)000:351001:352002:354003:358004:361005:362006:364007:368008:391009:39200A:39400B:39800C:3A100D:3A200E:3A400F:3A8010:0AE011:0AD012:0AB013:0A7014:09E015:09D016:09B017:097018:06E019:06D01A:06B01B:06701C:05E01D:05D01E:05B01F:057Subgroup gb4: (mapping of 4-bit data word into 10-bit code word)000:307001:30B002:30D003:30E004:370005:3B0006:3D0007:3E0008:0F8009:0F400A:0F200B:0F100C:08F00D:04F00E:02F00F:01FSubgroup gb3: (mapping of 3-bit data word into 10-bit code word)000:117001:127002:147003:187004:217005:227006:247007:287Subgroup gb2: (mapping of 2-bit data word into 10-bit code word)000:10F001:20F002:1F0003:2F0*****Subgroup gc7: (mapping of 7-bit data word into 10-bit code word)000:257001:25B002:25D003:25E004:267005:26B006:26D007:26E008:297009:29B00A:29D00B:29E00C:2A700D:2AB00E:2AD00F:2AE010:237011:23B012:23D013:23E014:2C7015:2CB016:2CD017:2CE018:273019:2B301A:2D301B:2E301C:27C01D:2BC01E:2DC01F:2EC020:275021:2B5022:2D5023:2E5024:276025:2B6026:2D6027:2E6028:279029:2B902A:2D902B:2E902C:27A02D:2BA02E:2DA02F:2EA030:21F031:22F032:24F033:28F034:2F1035:2F2036:2F4037:2F8038:077039:0B703A:0D703B:0E703C:07B03D:0BB03E:0DB03F:0EB040:157041:15B042:15D043:15E044:167045:16B046:16D047:16E048:197049:19B04A:19D04B:19E04C:1A704D:1AB04E:1AD04F:1AE050:137051:13B052:13D053:13E054:1C7055:1CB056:1CD057:1CE058:173059:1B305A:1D305B:1E305C:17C05D:1BC05E:1DC05F:1EC060:175061:1B5062:1D5063:1E5064:176065:1B6066:1D6067:1E6068:179069:1B906A:1D906B:1E906C:17A06D:1BA06E:1DA06F:1EA070:11F071:12F072:14F073:18F074:1F1075:1F2076:1F4077:1F8078:07D079:0BD07A:0DD07B:0ED07C:07E07D:0BE07E:0DE07F:0EESubgroup gc6: (mapping of 6-bit data word into 10-bit code word)000:31B001:333002:335003:336004:32B005:339006:33A007:33C008:34B009:35300A:35500B:35600C:38B00D:35900E:35A00F:35C010:31D011:363012:365013:366014:32D015:369016:36A017:36C018:34D019:39301A:39501B:39601C:38D01D:39901E:39A01F:39C020:31E021:3A3022:3A5023:3A6024:32E025:3A9026:3AA027:3AC028:34E029:3C302A:3C502B:3C602C:38E02D:3C902E:3CA02F:3CC030:371031:3B1032:3D1033:3E1034:372035:3B2036:3D2037:3E2038:374039:3B403A:3D4032:3E403C:37803D:3B803E:3D803F:3E8Subgroup gc4: (mapping of 4-bit data word into 10-bit code word)000:317001:03F002:05F003:06F004:327005:09F006:0AF007:0CF008:347009:0F300A:0F5002:0F600C:38700D:0F900E:0FA00F:0FCSubgroup gc1: (mapping of 1-bit data word into 10-bit code word)000:30F001:3F0*****Subgroup gd6: (mapping of 6-bit data word into 10-bit code word)000:357001:35B002:35D003:35E004:367005:36B006:36D007:36E008:397009:39B00A:39D00B:39E00C:3A700D:3AB00E:3AD00F:3AE010:337011:33B012:33D013:33E014:3C7015:3CB016:3CD017:3CE018:373019:3B301A:3D301B:3E301C:37C01D:3BC01E:3DC01F:3EC020:375021:3B5022:3D5023:3E5024:376025:3B6026:3D6027:3E6028:379029:3B902A:3D902B:3E902C:37A02D:3BA02E:3DA02F:3EA030:31F031:32F032:34F033:38F034:3F1035:3F2036:3F4037:3F8038:07F039:0BF03A:0DF032:0EF03C:0F703D:0FB03E:0FD03F:0FESubgroup gd5: (mapping of 5-bit data word into 10-bit code word)000:277001:2B7002:2D7003:2E7004:27B005:2BB006:2DB007:2EB008:27D009:2BD00A:2DD00B:2ED00C:27E00D:2BE00E:2DE00F:2EE010:177011:1B7012:1D7013:1E7014:17B015:1BB016:1DB017:1EB018:17D019:1BD01A:1DD01B:1ED01C:17E01D:1BE01E:1DE01F:1EESubgroup gd4: (mapping of 4-bit data word into 10-bit code word)000:15F001:16F002:19F003:1AF004:25F005:26F006:29F007:2AF008:1F5009:1F600A:1F900B:1FA00C:2F500D:2F600E:2F900F:2FASubgroup gd3: (mapping of 3-bit data word into 10-bit code word)000:13F001:1CF002:23F003:2CF004:1F3005:1FC006:2F3007:2FC*****Subgroup ge5: (mapping of 5-bit data word into 10-bit code word)000:377001:37B002:37D003:37E004:3B7005:3BB006:3BD007:3BE008:3D7009:3DB00A:3DD00B:3DE00C:3E700D:3EB00E:3ED00F:3EE010:17F011:1BF012:1DF013:1EF014:27F015:2BF016:2DF017:2EF018:1F7019:1FB01A:1FD01B:1FE01C:2F701D:2FB01E:2FD01F:2FESubgroup ge3: (mapping of 3-bit data word into 10-bit code word)000:35F001:36F002:39F003:3AF004:3F5005:3F6006:3F9007:3FA*****Subgroup gf3: (mapping of 3-bit data word into 10-bit code word)000:37F001:3BF002:3DF003:3EF004:3F7005:3FB006:3FD007:3FE


[0035] The third fragment is then mapped into an ‘h’ group word to maintain the running digital sum within +/−4. This mapping takes into account the current running digital sum of the system and the running digital sum of the ‘g’ group segment. The selection of the ‘h’ group code can be separated into three cases, depending on the current running digital sum of the system. The first case is if the current RDS is −4, the second case is if the RDS is −2 and the third case is if the RDS is 0. The cases of RDS being +4 or +2 are just the inverse of −4 and −2. Although there are different ways to group the ‘h’ groups, table 3 shows groupings according to various running digital sums. The ‘h’ groups can be chosen that correspond to collections from the ‘g’ subgroups. In some instances, the inverse, or −gxx, of the subgroup is chosen. Also, there are situations where the ‘h’ group word is larger (has more bits) than the corresponding mapping ‘g’ group (i.e. a fragment from the group ha8 is mapped to the group gc6). Here, the least significant bits of the third fragment are chosen to map the ‘h’ group according to the corresponding ‘g’ group.
3TABLE 3Mapping Table of user fragments into ‘h’ group words.Subgroup ha8 includes 256 patterns and they are from gc7, gc6 and gd6.Since 28 = 256, these code words are exactly enough for theencoding of 8-bit data words. Mappings of 8-bit data word to these10-bit code words of subgroup ha8 are:Data000 to 07F:gc7(128 patterns, RDS = +2)Data080 to 0BF:gc6(64 patterns, RDS = +2)Data0C0 to 0FF:gd6(64 patterns, RDS = +4)Subgroup ha6 includes 64 patterns and they are from gd5 and ge5.Mappings of 6-bit data word to these 10-bit code words are:Data000 to 01F:gd5 (32 patterns, RDS = +4)Data020 to 03F:ge5 (32 patterns, RDS = +6)Subgroup ha5 includes 32 patterns and they are from gc4 and gd4.Mappings of 5-bit data word to these 10-bit code words are:Data000 to 00F:gc4 (16 patterns, RDS = +2)Data010 to 01F:gd4 (16 patterns, RDS = +4)Subgroup ha4 includes 16 patterns and they are from gd3 and ge3.Mappings of 4-bit data word to these 10-bit code words are:Data000 to 007gd3(8 patterns, RDS = +4)Data008 to 00F:ge3(8 patterns, RDS = +6)Note that all “ha” patterns have RDS of +2, +4 or +6.*****Subgroup hb9 includes 512 patterns and they are from ha8, gb7, gb6, gb5,gb4, gb3 and gf3. Mappings of 9-bit data word to these 10-bitcode words are:Data000 to 0FF:ha8(256 patterns, RDS = +2, +4)Data100 to 17F:gb7(128 patterns, RDS = 0)Data180 to 1BF:gb6(64 patterns, RDS = 0)Data1C0 to 1DF:gb5(32 patterns, RDS = 0)Data1E0 to 1EF:gb4(16 patterns, RDS = 0)Data1F0 to 1F7:gb3(8 patterns, RDS = 0)Data1F8 to 1FF:gf3(8 patterns, RDS = +8)Subgroup hb6 includes 64 patterns and they are the same as ha6.Mappings of 6-bit data word to these 10-bit code words are:Data000 to 03F:ha6(64 patterns, RDS = +4, +6)Subgroup hb5 includes 32 patterns and they are the same as ha5.Mappings of 5-bit data word to these 10-bit code words are:Data000 to 01F:ha5(32 patterns, RDS = +2, +4)Subgroup hb4 includes 16 patterns and they are the same as ha4.Mappings of 4-bit data word to these 10-bit code words are:Data000 to 00F:ha4(16 patterns, RDS = +4, +6)All “hb” patterns have RDS of 0, +2, +4, +6 or +8.*****Subgroup hc9 includes 512 patterns and they are from ha8, gb7, gb6, gb5,gb4, gb3 gb2, gc1 and −gc1. Mappings of 9-bit data word to these 10-bitcode words are:Data000 to 0FF:ha8(256 patterns, RDS = +2, +4)Data100 to 17F:gb7(128 patterns, RDS = 0)Data180 to 1BF:gb6(64 patterns, RDS = 0)Data1C0 to 1DF:gb5(32 patterns, RDS = 0)Data1E0 to 1EF:gb4(16 patterns, RDS = 0)Data1F0 to 1F7:gb3(8 patterns, RDS = 0)Data1F8 to 1FB:gb2(4 patterns, RDS = 0)Data1FC to 1FD:gc1(2 patterns, RDS = +2)Data1FE to 1FF:−gc1(2 patterns, RDS = −2)Subgroup hc8 includes 256 patterns and they are from −gc7, −gc6and ha6. Mappings of 8-bit data word to these 10-bit code words are:Data000 to 07F:−gc7(128 patterns, RDS = −2)Data080 to 0BF:−gc6(64 patterns, RDS = −2)Data0C0 to 0FF:ha6(64 patterns, RDS = +4, +6)Subgroup hc6 includes 64 patterns and they are from ha5, −gc4 and ha4.Mappings of 6-bit data word to these 10-bit code words are:Data000 to 01F:ha5(32 patterns, RDS = +2, +4)Data020 to 02F:−gc4(16 patterns, RDS = −2)Data030 to 03F:ha4(16 patterns, RDS = +4, +6)All “hc” patterns have RDS of −2, 0, +2, +4, or +6.*****Subgroup hd9 includes 512 patterns and they are the same as hc9.Mappings of 9-bit data word to these 10-bit code words are:Data000 to 1FF:hc9(512 patterns, RDS = −2, 0, +2, +4)Subgroup hd8 includes 256 patterns and they are from −gc7, −gc6,gd5 and −gd5. Mappings of 8-bit data word to these 10-bit code words are:Data000 to 07F:−gc7(128 patterns, RDS = −2)Data080 to 0BF:−gc6(64 patterns, RDS = −2)Data0C0 to 0DF:gd5(32 patterns, RDS = +4)Data0E0 to 0FF:−gd5(32 patterns, RDS = −4)Subgroup hd7 includes 128 patterns and they are from −gd6, ha5, −gc4,gd3, and −gd3. Mappings of 8-bit data word to these 10-bit codewords are:Data000 to 03F:−gd6 (64 patterns, RDS = −4)Data040 to 05F:ha5(32 patterns, RDS = +2, +4)Data060 to 06F:−gc4 (16 patterns, RDS = −2)Data070 to 077:gd3(8 patterns, RDS = +4)Data078 to 07F:−gd3(8 patterns, RDS = −4)All “hd” patterns have RDS of −4, −2, 0, +2 or +4.*****Subgroup he9 includes 512 patterns and they are the equivalent to the in-verse of hc9. Mappings of 9-bit data word to these 10-bit code words are:Data000 to 1FF:−hc9(512 patterns, RDS = −4, −2, 0, +2)Subgroup he8 includes 256 patterns and they are the equivalent to the in-verse of hc8. Mappings of 8-bit data word to these 10-bit code words are:Data000 to 0FF:−hc8(256 patterns, RDS = −6, −4, +2)All “he” patterns have RDS of −6, −4, −2, 0, or +2.


[0036] The lookup tables can be assembled based on the current state and the ‘g’ group and ‘h’ group words. Tables 4 to 6 indicate how the 19-bit data words can be mapped into 20-bit code words. The 19-bit data word is broken into three fragments. The first fragment is a bit pattern of the most significant bits of the data word. The second and third fragments are mapped into ‘g’ and ‘h’ segments, respectively. The 20-bit code word is composed of two 10-bit code segments. The first code segment is selected from the ‘g’ group and the second code segment is selected from the ‘h’ group. Depending on the current state of the encoder, code words are chosen from the corresponding table. Tables for states −4, −2 and 0 are shown while state +4 uses the inverse code words for state −4 and state, +2 uses the inverse code words for state −2. In the lookup tables, “Pn.” stands for the particular pattern number of the mapping performed. There are 39 patterns for state −4, 19 patterns for state −2 and 16 patterns for state 0. The values “G type” and “H type” correspond to which ‘g’ and ‘h’ subgroup is in the particular pattern. These values can further be used when decoding the code word.
4TABLE 4Lookup table for data word when current state is −4.123


[0037]

5





TABLE 5








Lookup table for data word when current state is −2.












4









5















[0038]

6





TABLE 6










Lookup table for data word when current state is 0.







6















[0039] As an example, assume the 19-bit user data received in step 202 is 0×2A3EC=010 1010 0011 1110 1100 and the current state received in step 204 is −4. Assuming the leading bit is d18, d18=0, d17=1, d1=0, d15=1, d14=0, d13=1, d12=0, d11=0, d10=0, d9=1, d8=1, d7=1, d6=1, d5=1, d4=0, d3=1, d2=1, d1'0, d0=0. According to Table 4, which is for state −4, when d(18:15)=0101, which is the first fragment, d(14:9) (the second fragment) is mapped according to subgroup “gb6” to obtain the first 10-bit segment and d(8:0) (the third fragment) is mapped according to subgroup “hb9” to obtain the second 10-bit segment of the 20-bit code word. As ascertained from the data word, the second fragment d(14:9) is 010001=0×011. In step 210, according to the mapping table for subgroup “gb6”, the 10-bit segment should be 0×343=1101000011. For the second 10-bit segment of the code word, as obtained in step 212, the third fragment d(8:0)=111101100=0×1EC is mapped according to the mapping table for subgroup “hb9”. Data between 0×1E0=111100000 and 0×1EF=111101111 should use patterns from “gb4”. Here, the four least significant bits d(3:0)=1100=0×00C are mapped according to the mapping table for subgroup “gb4”. As a result, 0×00C maps into 0×08F=0010001111. Now, combining the first and second 10-bit segments in step 214 is performed to obtain the 20-bit code word of 1101000011 0010001111=0×D0C8F. The running digital sum of this code word is 0, thus the current state will remain −4(−4+0=−4).

[0040] In one embodiment, the unrestrained sequence of 101010 . . . is avoided. Code words having this sequence are eliminated. As a result, code words 0×AAAAA and 0×55555 are replaced by other code words, for example 0×83EAA and 0×43D55, respectively. These two examples are not used for other mappings and have the same RDS as the replaced patterns.

[0041] The details of the circuits and operations described below are examples and can be performed in hardware, software, firmware and/or combinations thereof. The functions of the circuits can be described with respect to various logic operations. In the case of circuits, these may be formed on one chip or various chips, as desired. Table 7 provides definitions for the symbols and logic operations used.
7TABLE 7Symbol definition:“|”Bitwise OR“&”Bitwise AND“{circumflex over ( )}”Bitwise XOR“!x”Inverse of bit x“!C(n:0)”Inverse of all bits of word C


[0042]
FIG. 3 illustrates a block diagram of an encoder 250 for encoding a user data word of 19 bits to a 20-bit code word. Encoder 250 communicates to a communications channel 252, which can comprise an arrangement of magnetic storage discs and heads as shown in FIG. 1. Channel 252 can also be other types of communication channels such as an optical, wireless or transmission line channel Encoder 250 receives as input an initialization signal, a user data word I18:0 and a word clock. Encoder 250 outputs a code word W19:0 to communication channel 252. An encoder input circuit 254 receives input to the encoder 250 as well as the next state of the system. The encoder input circuit 254 outputs a data word D18:0 and a pattern select value tt11:0 to encoder circuits 256, 258 and 260, identified as enc_r4, enc_r2 and enc_r0. Encoder circuit 254 also provides a state value to a GX encoder 262, an HX encoder 264 and an encoder output circuit 266. The GX encoder 262 and HX encoder 264 receive values from encoder circuits 256, 258 and 260 in order to generate the ‘g’ group words and the ‘h’ group words. The GX encoder 262 and HX encoder 264 provide the ‘g’ group words and ‘h’ group words to the encoder output circuit 266. Ultimately, output encoder circuit 266 provides a code word to communication channel 252.

[0043]
FIG. 4 illustrates a block diagram of encoder input circuit 254. Encoder input 254 includes a state register 270, a 19-bit data word block 272 and a pattern select circuit 274. Before the first data word is clocked into the input block, the initialization signal (Init) is used to initialize the state to zero. State is a four-bit sign value representing the current state. The next state value is received from the encoder output circuit 266 and is clocked in as the current state upon the rising edge of the word clock. Additionally, at 19-bit data word block 272, the data word I18:0 is clocked in upon a rising edge of the word clock. The 19-bit data word is sent to pattern select circuit 274. Pattern select circuit 274 prepares a value tt11:0 indicative of the four most significant bits of the data word. Encoder input circuit 254 operates in a manner shown in Table 8.
8TABLE 8Input: I18:0 (19 bits), Init, Word Clock, Next State3:0Output: D18:0 , tt11:0, State3:0Pattern Selecttt0 =!d18& d17&!d16&!d15tt1 =!d18& d17&!d16& d15tt2 =!d18& d17& d16&!d15tt3 =!d18& d17& d16& d15tt4 = d18&!d17&!d16&!d15tt5 = d18&!d17&!d16& d15tt6 = d18&!d17& d16&!d15tt7 = d18&!d17& d16& d15tt8 = d18& d17&!d16&!d15tt9 = d18& d17&!d16& d15tt10 = d18& d17& d16&!d15tt11 = d18& d17& d16& d15


[0044]
FIG. 5 illustrates a block diagram of encoder circuit 256, identified as enc_r4. Encoder circuit 256 includes a pattern select circuit 280 and a mux circuit 282. Encoder circuit 256 operates to select a code word when the current state is 4. Pattern select circuit 280 selects which of the 39 patterns of the lookup table shown in Table 4 is used given the data word d18:0. The value that pattern select circuit 280 issues is a 39-bit word indicating which pattern should be selected. Mux circuit 282 utilizes the select value S39:1 and the data word D18:0 to output a selection of which ‘g’ subgroup to use (g4s15:0), which bits of the data word will be mapped to the ‘g’ word (g4w6:0), which ‘h’ subgroup to use h415:0) and which bits of data word will be used to map the ‘h’ word (h4w8;0). The calculations of encoder circuit 256 are shown in Table 9.
9TABLE 9Input:d18,d17,d16,d15,d14,d13,d12,d11,d10,d9,d8,d7,d6,d5,d4,d3,d2,d1,d0 (19-bit Dataword)Output:g4w6,g4w5,g4w4,g4w3,g4w2,g4w1,g4w0   (7-bit word)g4s15,g4s14,g4s13,g4s12,g4s11,g4s10,g4s9,g4s8,g4s7,g4s6,g4s5,g4s4,g4s3,g4s2,g4s1,g4s0h4w8,h4w7,h4w6,h4w5,h4w4,h4w3,h4w2,h4w1,h4w0 (9-bit word)h4s15,h4s14,h4s13,h4s12,h4s11,h4s10,h4s9,h4s8,h4s7,h4s6,h4s5,h4s4,h4s3,h4s2,h4s1,h4s0Pattern Select of enc_r4t4 = tt0t5 = tt1t6 = tt2t7 = tt3t8 = tt4t9 = tt5ta = tt6tb = tt7:tc = tt8td = tt9te = tt10tf = tt11S1 =!d18&!d17&!d16S2 =!d18&!d17& d16S3 =t4S4 =t5S5 =t6S6 =t7:S7 =t8S8 =t9&!d14S9 =t9& d14S10=ta&!d14S11=ta& d14S12=tb&!d14S13=tb& d14S14=tc&!d14&!d13S15=tc&!d14& d13S16=tc& d14&!d13S17=tc& d14& d13S18=td&!d14&!d13S19=td&!d14& d13S20=td& d14&!d13S21=td& d14& d13S22=te&!d14&!d13S23=te&!d14& d13&!d12S24=te&!d14& d13& d12S25=te& d14&!d13&!d12S26=te& d14&!d13& d12S27=te& d14& d13&!d12S28=te& d14& d13& d12S29=tf&!d14&!d13&!d12S30=tf&!d14&!d13& d12S31=tf&!d14& d13&!d12S32=tf&!d14& d13& d12S33=tf& d14&!d13&!d12S34=tf& d14&!d13& d12&!d11S35=tf& d14&!d13& d12&d11S36=tf& d14& d13&!d12&!d11S37=tf& d14& d13&!d12&d11S38=tf& d14& d13& d12&!d11S39=tf& d14& d13& d12&d11MUX for GX and HX Encoder of enc_r4For GX:if (S1|S2|S4|S6|S7|S9|S12|S13|S16|S18|S21|S27|S32|S33){g4w(6:0) = (d15,d14,d13,d12,d11,d10,d9)}if (S3|S5|S8|S10|S11|S20|S22|S29|S31){g4w(6:0) = (d14,d13,d12,d11,d10, d9,d8)}if (S19|S30|S39){g4w(6:0) = (d13,d12,d11,d10, d9, d8,d7)}if (S14|S15|S17|S24|S26|S28|S38){g4w(6:0) = (d12,d11,d10, d9, d8, d7,d6)}if (S23|S25|S35|S37){g4w(6:0) = (d11,d10, d9, d8, d7, d6,d5)}if (S34|S36){g4w(6:0) = (d10, d9, d8, d7, d6, d5,d4)}if (S3|S14|S23|S34){g4s0=1,all other g4s=0}if (S8|S24|S35){g4s1=1,all other g4s=0}if (S1|S15|S25|S36){g4s2=1,all other g4s=0}if (S4|S26|S37){g4s3=1,all other g4s=0}if (S9|S38){g4s4=1,all other g4s=0}if (S16){g4s5=1,all other g4s=0}if (S27){g4s6=1,all other g4s=0}if (S2|S5|S17){g4s7=1,all other g4s=0}if (S6|S10|S28){g4s8=1,all other g4s=0}if (S18|S29){g4s9=1,all other g4s=0}if (S7|S11|S19){g4s10=1,all other g4s=0}if (S12|S20|S30){g4s11=1,all other g4s=0}if (S21|S31|S39){g4s12=1,all other g4s=0}if (S32){g4s13=1,all other g4s=0}if (S13|S22){g4s14=1,all other g4s=0}if (S33){g4s15=1,all other g4s=0}For HX:h4w(8:0) = (d8,d7,d6,d5,d4,d3,d2,d1,d0)if(S3|S8){h4s0=1,all other h4s=0}if(S14|S24){h4s1=1,all other h4s=0}if(S23|S35){h4s2=1,all other h4s=0}if(S34){h4s3=1,all other h4s=0}if(S1|S4|S9|S16|S27){h4s4=1,all other h4s=0}if(S15|S26|S38){h4s5=1,all other h4s=0}if(S25|S37){h4s6=1,all other h4s=0}if(S36){h4s7=1,all other h4s=0}if(S2|S6|S18){h4s8=1,all other h4s=0}if(S5|S10|S29){h4s9=1,all other h4s=0}if(S17|S28){h4s10=1,all other h4s=0}if(S7|S12|S21|S32){h4s11=1,all other h4s=0}if(S11|S20|S31){h4s12=1,all other h4s=0}if(S19|S30|S39){h4s13=1,all other h4s=0}if(S13|S33){h4s14=1,all other h4s=0}if(S22){h4s15=1,all other h4s=0}


[0045] Encoder circuits 258 and 260, shown in block diagrams in FIGS. 6 and 7, operate similar to encoder circuit 256. Encoder circuit 258 includes a pattern select circuit 290 that selects a particular pattern from the lookup table in Table 5 and mux circuit 292 indicates the appropriate ‘g’ and ‘’ subgroups and the bits of the data word that will be used for the ‘g’ and ‘h’ mappings. Encoder circuit 260 includes pattern select circuit 300 and mux circuit 302. Pattern select circuit 300 indicates which pattern should be used when the current state is zero. Mux circuit 302 outputs the appropriate ‘g’ and ‘h’ subgroups and the bits used for the respective ‘g’ and ‘h’ mappings. Encoder circuits 258 and 260 operate according to the tables shown in tables 10 and 11, respectively.
10TABLE 10Input:d18,d17,d16,d15,d14,d13,d12,d11,d10,d9,d8,d7,d6,d5,d4,d3,d2,d1,d0 (19-bit Dataword)tt11,tt10,tt9,tt8,tt7,tt6,tt5,tt4,tt3,tt2,tt1,tt0Output:g2w6,g2w5,g2w4,g2w3,g2w2,g2w1,g2w0 (7-bit word)g2s9,g2s8,g2s7,g2s6,g2s5,g2s4,g2s3,g2s2,g2s1,g2s0h2w8,h2w7,h2w6,h2w5,h2w4,h2w3,h2w2,h2w1,h2w0(9-bit word)h2s10,h2s9,h2s8,h2s7,h2s6,h2s5,h2s4,h2s3,h2s2,h2s1,h2s0Pattern Select of enc_r2t6 = tt2t7 = tt3t8 = tt4t9 = tt5ta = tt6tb = tt7:tc = tt8td = tt9te = tt10tf = tt11S1 =!d18&!d17&!d16S2 =!d18&!d17& d16S3 =!d18& d17&!d16S4 =t6S5 =t7:S6 =t8S7 =t9S8 =taS9 =tbS10=tc&!d14S11=tc& d14S12=td&!d14S13=td& d14S14=te&!d14S15=te& d14S16=tf&!d14&!d13S17=tf&!d14& d13S18=tf& d14&!d13S19=tf& d14& d13MUX for GX and HX Encoder of enc_r2For GX:if (S1|S2|S3|S4|S6|S8|S9|S11|S15|S19){g2w(6:0) = (d15,d14,d13,d12,d11,d10,d9)}if(S5|S7|S10|S13|S14|S18){g2w(6:0) = (d14,d13,d12,d11,d10, d9,d8)}if (S12){g2w(6:0) = (d13,d12,d11,d10, d9, d8,d7)}if (S16|S17){g2w(6:0) = (d12,d11,d10, d9, d8, d7,d6)}if (S1|S16){g2s0=1,all other g2s=0}if(S4){g2s1=1,all other g2s=0}if(S2|S5|S17){g2s2=1,all other g2s=0}if(S6|S10){g2s3=1,all other g2s=0}if(S11|S18){g2s4=1,all other g2s=0}if(S19){g2s5=1,all other g2s=0}if(S3|S7|S12){g2s6=1,all other g2s=0}if(S8|S13){g2s7=1,all other g2s=0}if(S9|S14){g2s8=1,all other g2s=0}if(S15){g2s9=1,all other g2s=0For HX:h2w(8:0) = (d8,d7,d6,d5,d4,d3,d2,d1,d0)if(S1|S4){h2s0=1,all other h2s=0}if(S16){h2s1=1,all other h2s=0}if(S2|S6|S11|S19){h2s2=1,all other h2s=0}if(S5|S10|S18){h2s3=1,all other h2s=0}if(S17){h2s4=1,all other h2s=0}if(S3|S8){h2s5=1,all other h2s=0}if(S7|S13){h2s6=1,all other h2s=0}if(S12){h2s7=1,all other h2s=0}if(S9){h2s8=1,all other h2s=0}if(S14){h2s9=1,all other h2s=0}if(S15){h2s10=1,all other h2s=0}


[0046]

11





TABLE 11










enc_r0








Input:
d18,d17,d16,d15,d14,d13,d12,d11,d10,d9,d8,d7,d6,d5,d4,d3,d2,



d1,d0 (19-bit Dataword)


Output:
g0w6,g0w5,g0w4,g0w3,g0w2,g0w1,g0w0 (7-bit word)



g0s8,g0s7,g0s6,g0s5,g0s4,g0s3,g0s2,g0s1,g0s0



h0w8,h0w7,h0w6,h0w5,h0w4,h0w3,h0w2,h0w1,h0w0



(9-bit word)



h0s7,h0s6,h0s5,h0s4,h0s3,h0s2,h0s1,h0s0







Pattern Select of enc_r0










t6 = tt2
t7 = tt3




t8 = tt4
t9 = tt5
ta = tt6
tb = tt7:


tc = tt8
td = tt9
te = tt10
tf = tt11








S1 =!d18&!d17&!d16
S2 =!d18&!d17& d16


S3 =!d18& d17&!d16
S4 =t6


S5 =t7:
S6 =t8


S7 =t9
S8 =ta


S9 =tb
S10=tc


S11=td&!d14
S12=td& d14


S13=te&!d14
S14=te& d14


S15=tf&!d14
S16=tf& d14







MUX for GX and HX Encoder of enc_r0


For GX:


if(S1|S2|S3|S5|S7|S9|S10|S14|S16)










{g0w(6:0) = (d15,d14,d13,d12,d11,d10,d9)
}







if(S4|S6|S8|S11|S13|S15)










{g0w(6:0) = (d14,d13,d12,d11,d10, d9,d8)
}







if(S12)










{g0w(6:0) = (d13,d12,d11,d10, d9, d8,d7)
}










if(S1|S4)
{g0s0=1,
all other g0s=0
}


if(S5|S11)
{g0s1=1,
all other g0s=0
}


if(S2|S6|S12)
{g0s2=1,
all other g0s=0
}


if(S7|S13)
{g0s3=1,
all other g0s=0
}


if(S14)
{g0s4=1,
all other g0s=0
}


if(S3|S8)
{g0s5=1,
all other g0s=0
}


if(S9|S15)
{g0s6=1,
all other g0s=0
}


if(S10)
{g0s7=1,
all other g0s=0
}


if(S16)
{g0s8=1,
all other g0s=0
}







For HX:


h0w(8:0) = (d8,d7,d6,d5,d4,d3,d2,d1,d0)










if(S1|S5)
{h0s0=1,
all other h0s=0
}


if(S4|S11)
{h0s1=1,
all other h0s=0
}


if(S2|S7|S14)
{h0s2=1,
all other h0s=0
}


if(S6|S13)
{h0s3=1,
all other h0s=0
}


if(S12)
{h0s4=1,
all other h0s=0
}


if(S3|S9)
{h0s5=1,
all other h0s=0
}


if(S8|S15)
{h0s6=1,
all other h0s=0
}


if(S10|S16)
{h0s7=1,
all other h0s=0
}










[0047]
FIG. 8 illustrates a block diagram of GX encoder 262. GX encoder 262 includes an GX encoder input mux 310, a plurality of subgroup encoder circuits 312 and a GX encoder output mux 314. GX encoder input mux 310 receives the ‘g’ values from the encoder circuits 256, 258 and 260 (g4w, g2w, g0w, g4w_sel, g2w_sel, g0w_sel). Input mux 310 also receives the current state from encoder input circuit 254. Encoder input mux 310 sends the appropriate ‘g’ bits (the second fragment) received through each of the plurality of subgroup encoder circuits 312 based on the ‘g’ select values and the current state. The plurality of encoder circuits 312 map the second fragment (gw_in6:0) according to the mapping table of Table 2. The mapped 10-bit segments are then output to the GX encoder output mux 314. In the event an inverse of the mapped subgroups is necessary, for example from enc_gx7 and enc_c6, inverter circuits 316 are provided to invert the output from these respective circuits and send it to the GX encoder output mux 314. The GX encoder output mux selects the appropriate 10-bit segment according to the ‘g’ select value sent from GX encoder input mux 310. The GX encoder 262 operates according to calculations shown in Table 12.


[0048]
FIG. 9 illustrates a block diagram of HX encoder 264, which operates similar to GX encoder 262. HX encoder 264 includes an HX encoder input mux 320, a plurality of subgroup encoder circuits 322 and an HX encoder output mux 324. HX encoder input mux 320 receives a signal indicative of the current state from the encoder input circuit 254 and ‘h’ values (h4w, h2w, h0w, h4s, h2s, h0s) from encoder circuits 256, 258 and 260. HX encoder input mux 320 selects the appropriate third fragment (either h4w, h2w and h0w) based on the current state and select values (h4s, h2s, h0s) and outputs the selection as hw_in. Also, HX encoder input mux 320 selects the particular subgroup based on the state and outputs a value h_sel based on the state. The plurality of subgroup encoder circuits 322 map the second fragment and send their respective mapped segments to the HX encoder output mux 324. The HX encoder output mux 324 selects the appropriate 10-bit segment based on h−sel. The 10-bit segment is then sent to encoder output circuit 266. The HX encoder 264 operates according to calculations shown in Table 13.
12TABLE 13HX EncoderInput:h4w(6:0), h2w(6:0), h0w(6:0), h4s(15:0), h2s(10:0), h0s(7:0),State(3:0)Output:hw(9:0)HX Encoder Input MuxInput:h4w(8:0), h2w(8:0), h0w(8:0), h4s(15:0), h2s(10:0), h0s(7:0),State(3:0)Output:hw_in(8:0), h_sel(16:0)State(3:0) is a 4-bit signed value representing the current state.if (State= −4 or State= 4) {hw_in(8:0) = h4w(8:0),h_sel(15:0) = h4s(15:0),h_sel(16) =0}if (State= −2 or State= 2) {hw_in(8:0) = h2w(8:0),h_sel(0) =0,h_sel(1) =0,h_sel(2) =0,h_sel(3) =0,h_sel(4) =h2s(0),h_sel(5) =h2s(1),h_sel(6) =0,h_sel(7) =0,h_sel(8) =h2s(2),h_sel(9) =h2s(3),h_sel(10) =h2s(4),h_sel(11) =h2s(5),h_sel(12) =h2s(6),h_sel(13) =h2s(7),h_sel(14) =h2s(8),h_sel(15) =h2s(9),h_sel(16) =h2s(10),}if (State= 0) {hw_in(8:0) = h0w(8:0),h_sel(0) =0,h_sel(1) =0,h_sel(2) =0,h_sel(3) =0,h_sel(4) =0,h_sel(5) =0,h_sel(6) =0,h_sel(7) =0,h_sel(8) =h0s(0),h_sel(9) =h0s(1),h_sel(10) =0,h_sel(11) =h0s(2),h_sel(12) =h0s(3),h_sel(13) =h0s(4),h_sel(14) =h0s(5),h_sel(15) =h0s(6),h_sel(16) =h0s(7),}Note: All the encoders enc_gc7, enc_gc6, enc_gc5, enc_gc4,enc_gc3, enc_gd6, enc_gd5, enc_gd4,enc_gd3, enc_ge5 andenc_ge3 used here in HX Encoder are identical to those definedin the GX Encoder.enc_ha8Input:A(7:0)Output:CW(9:0)if(!A7)CW(9:0) = enc_gc7(A(6:0));if(A7&!A6)CW(9:0) = enc_gc6(A(5:0));if(A7&A6)CW(9:0) = enc_gd6(A(5:0));Note: CW(9:0) = enc_gc7(A(6:0)); means CW(9:0) is equal to the 10-bitoutput of block enc_gc7 when A(6:0) is the input to it.enc_ha6Input:A(5:0)Output:CW(9:0)if(!A5)CW(9:0) = enc_gd5(A(4:0));if(A5)CW(9:0) = enc_ge5(A(4:0));enc_ha5Input:A(4:0)Output:CW(9:0)if(!A4)CW(9:0) = enc_gc4(A(3:0));if(A4)CW(9:0) = enc_gd4(A(3:0));enc_ha4Input:A(3:0)Output:CW(9:0)if(!A3)CW(9:0) = enc_gd3(A(2:0));if(A3)CW(9:0) = enc_ge3(A(2:0));enc_hb9Input:A(8:0)Output:CW(9:0)if(!A8)CW(9:0) = enc_ha8(A(7:0));if(A8&!A7)CW(9:0) = enc_gb7(A(6:0));if(A8&A7&!A6)CW(9:0) = enc_gb6(A(5:0));if(A8&A7&A6&!A5)CW(9:0) = enc_gb5(A(4:0));if(A8&A7&A6&A5&!A4)CW(9:0) = enc_gb4(A(3:0));if(A8&A7&A6&A5&A4&!A3)CW(9:0) = enc_gb3(A(2:0));if(A8&A7&A6&A5&A4& A3)CW(9:0) = enc_gf3(A(2:0));enc_gf3Input:A2,A1,A0Output:C9,C8,C7,C6,C5,C4,C3,C2,C1,C0gf3a= !A2;gf3a9= gf3a;gf3a8= gf3a;gf3a7= gf3a &( A1 | A0 );gf3a6= gf3a &( A1 | !A0 );gf3a5= gf3a &( A0 | !A1 );gf3a4= gf3a &( !A1 | !A0 );gf3a3= gf3a;gf3a2= gf3a;gf3a1= gf3a;gf3a0= gf3a;gf3b= A2;gf3b9= gf3b;gf3b8= gf3b;gf3b7= gf3b;gf3b6= gf3b;gf3b5= gf3b;gf3b4= gf3b;gf3b3= gf3b &( A1 | A0 );gf3b2= gf3b &( A1 | !A0 );gf3b1= gf3b &( A0 | !A1 );gf3b0= gf3b &( !A1 | !A0 );C9 = gf3a9 |gf3b9;C8 = gf3a8 |gf3b8;C7 = gf3a7 |gf3b7;C6 = gf3a6 |gf3b6;C5 = gf3a5 |gf3b5;C4 = gf3a4 |gf3b4;C3 = gf3a3 |gf3b3;C2 = gf3a2 |gf3b2;C1 = gf3a1 |gf3b1;C0 = gf3a0 |gf3b0;enc_hc9Input:A(8:0)Output:CW(9:0)if( ! (A8&A7&A6&A5&A4&A3) ){ CW(9:0) = enc_hb9(hw);}else{ if(!A2)CW(9:0) = enc_gb2(A(1:0));  if(A2&!A1)CW(9:0) = enc_gc1(A(0) );  if(A2& A1)CW(9:0) =!(enc_gc1(A(0)));}enc_gb2Input:A1,A0Output:C9,C8,C7,C6,C5,C4,C3,C2,C1,C0C9= A0;C8=!A0;C7= A1;C6= A1;C5= A1;C4= A1;C3= A1;C2=!A1;C1=!A1;C0=!A1;enc_gc1Input:A0Output:C9,C8,C7,C6,C5,C4,C3,C2,C1,C0C9= 1;C8= 1;C7= A0;C6= A0;C5= A0;C4= A0;C3=!A0;C2=!A0;C1=!A0;C0=!A0;enc_hc8Input:A(7:0)Output:CW(9:0)if(!A7)CW(9:0)=!(enc_gc7(A(6:0)));if(A7&!A6)CW(9:0)=!(enc_gc6(A(5:0)));if(A7&A6)CW(9:0)= enc_ha6(A(5:0));enc_hc6Input:A(5:0)Output:CW(9:0)if(!A5)CW(9:0)=!enc_ha5(A(4:0));if(A5&!A4)CW(9:0)=!(enc_gc4(A(3:0)));if(A5& A4)CW(9:0)= enc_ha4(A(3:0));enc_hd8Input:A(7:0)Output:CW(9:0)if(!(A7&A6&A5))CW(9:0)=enc_hc8(A(7:0));elseCW(9:0)=!(enc_gd5(A(4:0)));enc_hd7:Input:A(6:0)Output:CW(9:0)if(!A6)CW(9:0)=!(enc_gd6(A(5:0)));if(A6&!A5&A4&A3))CW(9:0)=  enc_hc6(A(5:0));if(A6& (A5&A4&A3))CW(9:0)=!(enc_gd3(A(2:0)));HX Encoder Output MuxInput:ha8(9:0), ha6(9:0), ha5(9:0), ha4(9:0), hb9(9:0), hc9(9:0),hc8(9:0), hc6(9:0), hd8(9:0), hd7(9:0), h_sel(16:0)Output:hw(9:0)hb6(9:0) = ha6(9:0)hb5(9:0) = ha5(9:0)hb4(9:0) = ha4(9:0)hd9(9:0) = hc9(9:0)he9(9:0) =!hc9(9:0)he8(9:0) =!hc8(9:0)hf9(9:0) =!hb9(9:0)If(h_sel0){hw(9:0)= ha8(9:0)}If(h_sel1){hw(9:0)= ha6(9:0)}If(h_sel2){hw(9:0)= ha5(9:0)}If(h_sel3){hw(9:0)= ha4(9:0)}If(h_sel4){hw(9:0)= hb9(9:0)}If(h_sel5){hw(9:0)= hb6(9:0)}If(h_sel6){hw(9:0)= hb5(9:0)}If(h_sel7){hw(9:0)= hb4(9:0)}If(h_sel8){hw(9:0)= hc9(9:0)}If(h_sel9){hw(9:0)= hc8(9:0)}If(h_sel10){hw(9:0)= hc6(9:0)}If(h_sel11){hw(9:0)= hd9(9:0)}If(h_sel12){hw(9:0)= hd8(9:0)}If(h_sel13){hw(9:0)= hd7(9:0)}If(h_sel14){hw(9:0)= he9(9:0)}If(h_sel15){hw(9:0)= he8(9:0)}If(h_sel16){hw(9:0)= hf9(9:0)}


[0049]
FIG. 10 illustrates a block diagram of encoder output circuit 266. Encoder output circuit 266 includes form code word circuit 330 and RDS calculator 332. Form code word circuit 334 combines the code words gw and hw received from the GX encoder and HX encoder, respectively, to form the code word. Also, if the state is negative, the entire code word is inversed to output the correct value. The output of form code word circuit 330 is sent to the communication channel 252 and RDS calculator 332. RDS calculator 332 receives the code word and the current state. RDS calculator 332 adds the values of the code word and the state to output the next state to the encoder input circuit 254, where it is used for a subsequent encoding. Encoder output circuit 266 operates according to calculations shown in Table 14.
13TABLE 14Encoder Output BlockInput:gw(9:0), hw(9:0), State(3:0)Output:W(19:0), NextState(3:0)Form Code Wordif (State<=0){W(19:10) = gw(9:0);W(9:0) = hw(9:0);}if (State>0){W(19:10) =!gw(9:0);W(9:0) =!hw(9:0);}if( W(19:0)==0xAAAAA)W(19:0) = 0x83EAA;if( W(19:0)==0x55555)W(19:0) = 0x43D55;RDS CalculatorHW=W19+W18+W17+W16+W15+W14+W13+W12+W11+W10+W9+W8+W7+W6+W5+W4+W3+W2+W1+W0RDS = (2 * HW) −20NextState= State + RDSNote that Hamming weight (HW) of the code Word W(19:0) is the sum of the 20 code bits. The running digital sum (RDS) of the code word is calculated by subtracting the number of “0” by the number of “1” in the code word. For example, if there are 13 “1” (HW = 13) and number of “0” is # (20−HW), the RDS is HW− (20−HW)= (2*HW) −20. In a sequence of code words, the cumulative RDS is the RDS of all bits from the beginning of the first code word to the end of the current code word. Note that the cumulative RDS in this design must be equal to either −4, −2, 0, 2 or 4. This number is also considered as the state of the encoder.


[0050]


[0051]
FIG. 11 illustrates a method 350 of decoding information received from communication channel 252. At step 352, the 20-bit code word is received from communication channel 252. Next, at step 354, the ‘g’ and ‘h’ bit segments from the code word are separated. At step 356, the ‘g’ 10-bit segment is decoded and at step 358 the ‘h’ 10-bit segment is decoded. Ultimately, at step 360, the 19-bit data word is formed and output.

[0052]
FIG. 12 illustrates a decoder 370 that decodes information received from communication channel 252. Decoder 370 includes a decoder input circuit 372, a GX decoder 374, an HX decoder 376 and a decoder output circuit 378. As discussed in more detail below, the decoder input circuit 372 receives an initialization signal, the code word W19:0 and a word clock. The decoder input circuit 372 ascertains the state from the code word and separates the code word into a ‘g’ segment gcp9:0 and an ‘h’ segment hcp9:0. The ‘g’ segments and the ‘h’ segments are sent to the GX decoder 374 and HX decoder 376, respectively. The GX decoder 374 and the HX decoder 376 decode the respective segments and provide an output to decoder output circuit 378. The decoder output circuit 378 forms a 19-bit data word using the state value sent from decoder input 372 and outputs the 19-bit data word I18:0.

[0053]
FIG. 13 illustrates a block diagram of decoder input circuit 372. Decoder input circuit 372 includes a state evaluator circuit 380, a state register 382, a 20-bit code word register 384 and an input mux 386. The initialization signal is sent to state evaluator circuit 380 and resets the state at the beginning of a first code word that is received from communication channel 252. The word clock initializes state register 382 and 20-bit code word register 384. The code word W19:0 is sent to the 20-bit code word register 384. The 20-bit code word is sent to state evaluator circuit 380 and input mux 386. Input mux 386 separates the 20-bit code word into a ‘g’ segment gcp and an ‘h’ segment hcp. Decoder input circuit 372 operates according to the calculations in Table 15.
14TABLE 15Decoder InputInput:W(19:0), Init, Word ClockOutput:gcp(9:0), hcp(9:0), State(3:0)The Init signal is used to initialize Next State(3:0) to zero before the firstclock signal. The rising edge of the Word Clock can be used to clock-inthe 20-bit code word W(19:0) and shift the Next State to the State register.The State Evaluator is for calculating the Running Digital Sum (RDS) ofthe code word and the cumulative RDS. The RDS of the code wordW(19:0) is:RDS = (2*HW)−20 where HW is the Hamming weight of W(19:0)Next State = State + RDSTherefore, the State represents the cumulative RDS of all code bits up tillthe end of the last code word.INPUT MUXif( wm(19:0)==0x83EAA)wm(19:0) = 0xAAAAA;if( wm(19:0)==0x43D55)wm(19:0) = 0x55555;if(State<=0){gcp(9:0)= wm(19:10);hcp(9:0)= wm(9:0);}if(State>0){gcp(9:0)=!wm(19:10);hcp(9:0)=!wm(9:0);}


[0054]
FIG. 14 illustrates a block diagram of GX decoder 374. GX decoder 374 receives ‘g’ segment gcp from decoder input circuit 372. GX decoder 374 includes digital sum circuit 390, inverter 392, pattern select 394, a plurality of ‘g’ subgroup decoders 396 and a GX output mux 398. Digital sum calculator 390 determines the 30 digital sum of ‘g’ segment gcp. If the digital sum of the ‘g’ segment gcp is less than zero, the inverter 392 will invert the ‘g’ segment gcp. After passing through inverter 392, a ‘g’ word gw is sent to the pattern generator 394 and plurality of ‘g’ subgroup decoders 396. Pattern selector 394 determines a 36-bit pattern based on the 10-bit word. This 36-bit pattern is used in each of the plurality of subgroup decoders 396 in order to determine the appropriate data value for the ‘g’ group word. Each of the plurality of subgroup decoders send a value indicative of the subgroup to GX output mux 398. GX output 398 sends the appropriate ‘g’ word gdw and ‘g’ type to decoder output circuit 378. Additionally, a value gm indicative of the ‘g’ type is sent to HX decoder 376 in order to select the appropriate ‘h’ word. GX decoder 374 operates according to the calculations in Table 16.


[0055]
FIG. 15 illustrates a block diagram of HX decoder 376. HX decoder 376 includes a first pattern generator 400, an inverter 402, a second pattern generator 404, a plurality of subgroup decoders 406 and an HX output mux 408. The first pattern generator 400 generates a 36-bit pattern based on the ‘h’ word hcp. Second pattern generator 404 generates a 36-bit pattern based on the inverse of ‘h’ word hcp. These values are provided to the plurality of subgroup decoders 406. The plurality of subgroup decoders 406 determine the appropriate values to be sent to HX output mux 408. Based on the gm and state values, the appropriate ‘h’ word hdw and ‘h’ type are sent to decoder output circuit 378. HX decoder 374 operates according to the calculations in Table 17.
15TABLE 17HX DecoderInput:hcp(9:0), gm(3:0), State(3:0)Output:hdw(8:0), Htype(7:0)INVInput:hcp(9:0)Output:hwi(9:0)hwi(9:0) = !hcp(9:0)gen_p10 is the same as that in GX Decoder.dec_haInput:hw(9:0), x(3:0), y(15:0), z(15:0)Output:hadw(8:0), haht(7:0)( dec_gc, dec_gd, dec_ge and get_ds ) are identical to those inGX_DecoderInput MuxInput:gcdw(6:0), gddw(6:0), gedw(6:0), gcgt(7:0), gdgt(7:0),gegt(7:0), hds(4:0)Output:gdw(6:0), gt(7:0)if(hds=2){gdw(6:0) =gcdw(6:0);gt(7:0) =gcgt(7:0);}if(hds=4){gdw(6:0) =gddw(6:0);gt(7:0) =gdgt(7:0);}if(hds=6){gdw(6:0) =gedw(6:0);gt(7:0) =gegt(7:0);}Output_haInput:gdw(6:0), gt(7:0)Output:hdw(8:0), ht(7:0)if(gt=0x17){hdw(8:0) =gdw(6:0);ht(7:0) =0x08;}if(gt=0x16){hdw(8:0) =gdw(6:0) |0x80;ht(7:0) =0x08;}if(gt=0x26){hdw(8:0) =gdw(6:0) |0xC0;ht(7:0) =0x08;}if(gt=0x25){hdw(8:0) =gdw(6:0);ht(7:0) =0x06;}if(gt=0x35){hdw(8:0) =gdw(6:0) |0x20;ht(7:0) =0x06;}if(gt=0x14){hdw(8:0) =gdw(6:0);ht(7:0) =0x05;}if(gt=0x24){hdw(8:0) =gdw(6:0) |0x10;ht(7:0) =0x05;}if(gt=0x23){hdw(8:0) =gdw(6:0);ht(7:0) =0x04;}if(gt=0x33){hdw(8:0) =gdw(6:0) |0x08;ht(7:0) =0x04;}Note: [hdw(8:0) =gdw(6:0)] means [hdw(8) =hdw(7) =0,hdw(6:0) =gdw(6:0)]dec_hbInput:hw(9:0), x(3:0), y(15:0), z(15:0)Output:hbdw(8:0), hbht(7:0)( dec_gb, dec_gc, dec _gd, dec_ge, dec_gf and get_ds ) areidentical to those in GX_DecoderInput MuxInput:gbdw(6:0), gcdw(6:0), gddw(6:0), gedw(6:0), gfdw(6:0),gbgt(7:0), gcgt(7:0), gdgt(7:0), gegt(7:0) gfgt(7:0), hds(4:0)Output:gdw(6:0), gt(7:0)if(hds=0){gdw(6:0) =gbdw(6:0);gt(7:0) =gbgt(7:0);}if(hds=2){gdw(6:0) =gcdw(6:0);gt(7:0) =gcgt(7:0);}if(hds=4){gdw(6:0) =gddw(6:0);gt(7:0) =gdgt(7:0);}if(hds=6){gdw(6:0) =gedw(6:0);gt(7:0) =gegt(7:0);}if(hds=8){gdw(6:0) =gfdw(6:0);gt(7:0) =gfgt(7:0);}Output_hbInput:gdw(6:0), gt(7:0)Output:hdw(8:0), ht(7:0)if(gt=0x17){hdw(8:0) =gdw(6:0);ht(7:0) =0x19;}if(gt=0x16){hdw(8:0) =gdw(6:0) |0x80;ht(7:0) =0x19;}if(gt=0x26){hdw(8:0) =gdw(6:0) |0xC0;ht(7:0) =0x19;}if(gt=0x07){hdw(8:0) =gdw(6:0) |0x100;ht(7:0) =0x19;}if(gt=0x06){hdw(8:0) =gdw(6:0) |0x180;ht(7:0) =0x19;}if(gt=0x05){hdw(8:0) =gdw(6:0) |0x1C0;ht(7:0) =0x19;}if(gt=0x04){hdw(8:0) =gdw(6:0) |0x1E0;ht(7:0) =0x19;}if(gt=0x03){hdw(8:0) =gdw(6:0) |0x1F0;ht(7:0) =0x19;}if(gt=0x43){hdw(8:0) =gdw(6:0) |0x1F8;ht(7:0) =0x19;}if(gt=0x25){hdw(8:0) =gdw(6:0);ht(7:0) =0x16;}if(gt=0x35){hdw(8:0) =gdw(6:0) |0x20;ht(7:0) =0x16;}if(gt=0x14){hdw(8:0) =gdw(6:0);ht(7:0) =0x15;}if(gt=0x24){hdw(8:0) =gdw(6:0) |0x10;ht(7:0) =0x15;}if(gt=0x23){hdw(8:0) =gdw(6:0);ht(7:0) =0x14;}if(gt=0x33){hdw(8:0) =gdw(6:0) |0x08;ht(7:0) =0x14;}Note: [hdw(8:0) =gdw(6:0)] means [hdw(8) =hdw(7) =0,hdw(6:0) =gdw(6:0)]dec_hcInput:hw(9:0), x(3:0), y(15:0), z(15:0), ihw(9:0), ix(3:0), iy(15:0),iz(15:0)Output:hcdw(8:0), hcht(7:0)Note that the 36-bit input ixyz is the combination of ix(3:0), iy(15:0)and iz(15:0).( dec_gb, dec_gc, dec _gd, dec_ge and get_ds ) are identical to thosein Gx_DecoderInput MuxInput:igcdw(6:0), gbdw(6:0), gcdw(6:0), gddw(6:0), gedw(6:0),igcgt(7:0), gbgt(7:0), gcgt(7:0), gdgt(7:0), gegt(7:0), hds(4:0)Output:gdw(6:0), gt(7:0)if(hds=−2){gdw(6:0) =igcdw(6:0);gt(7:0) =igcgt(7:0) |0x80;}if(hds=0){gdw(6:0) =gbdw(6:0);gt(7:0) =gbgt(7:0);}if(hds=2){gdw(6:0) =gcdw(6:0);gt(7:0) =gcgt(7:0);}if(hds=4){gdw(6:0) =gddw(6:0);gt(7:0) =gdgt(7:0);}if(hds=6){gdw(6:0) =gedw(6:0);gt(7:0) =gegt(7:0);}Output_hcInput:gdw(6:0), gt(7:0)Output:hdw(8:0), ht(7:0)if(gt=0x17){hdw(8:0) =gdw(6:0);ht(7:0) =0x29;}if(gt=0x16){hdw(8:0) =gdw(6:0) |0x80;ht(7:0) =0x29;}if(gt=0x26){hdw(8:0) =gdw(6:0) |0xC0;ht(7:0) =0x29;}if(gt=0x07){hdw(8:0) =gdw(6:0) |0x100;ht(7:0) =0x29;}if(gt=0x06){hdw(8:0) =gdw(6:0) |0x180;ht(7:0) =0x29;}if(gt=0x05){hdw(8:0) =gdw(6:0) |0x1C0;ht(7:0) =0x29;}if(gt=0x04){hdw(8:0) =gdw(6:0) |0x1E0;ht(7:0) =0x29;}if(gt=0x03){hdw(8:0) =gdw(6:0) |0x1F0;ht(7:0) =0x29;}if(gt=0x02){hdw(8:0) =gdw(6:0) |0x1F8;ht(7:0) =0x29;}if(gt=0x11){hdw(8:0) =gdw(6:0) |0x1FC;ht(7:0) =0x29;}if(gt=0x91){hdw(8:0) =gdw(6:0) |0x1FE;ht(7:0) =0x29;}if(gt=0x97){hdw(8:0) =gdw(6:0);ht(7:0) =0x28;}if(gt=0x96){hdw(8:0) =gdw(6:0) |0x80;ht(7:0) =0x28;}if(gt=0x25){hdw(8:0) =gdw(6:0) |0xC0;ht(7:0) =0x28;}if(gt=0x35){hdw(8:0) =gdw(6:0) |0xE0;ht(7:0) =0x28;}if(gt=0x14){hdw(8:0) =gdw(6:0);ht(7:0) =0x26;}if(gt=0x24){hdw(8:0) =gdw(6:0) |0x10;ht(7:0) =0x26;}if(gt=0x94){hdw(8:0) =gdw(6:0) |0x20;ht(7:0) =0x26;}if(gt=0x23){hdw(8:0) =gdw(6:0) |0x30;ht(7:0) =0x26;}if(gt=0x33){hdw(8:0) =gdw(6:0) |0x38;ht(7:0) =0x26;}Note: [hdw(8:0) =gdw(6:0)] means [hdw(8) =hdw(7) =0,hdw(6:0) =gdw(6:0)]dec_hdInput:hw(9:0), x(3:0), y(15:0), z(15:0), ihw(9:0), ix(3:0), iy(15:0),iz(15:0)Output:hddw(8:0), hdht(7:0)( dec_gb, dec_gc, dec_gd and get_ds ) are identical to those inGx_DecoderOutput of the INV block is the bitwise inverse of its input.Input MuxInput:igddw(6:0), igcdw(6:0), gbdw(6:0), gcdw(6:0), gddw(6:0),igdgt(7:0), igcgt(7:0), gbgt(7:0), gcgt(7:0), gdgt(7:0), hds(4:0)Output:gdw(6:0), gt(7:0)if(hds=−4){gdw(6:0) =igddw(6:0);gt(7:0) =igdgt(7:0) |0x80;}if(hds=−2){gdw(6:0) =igcdw(6:0);gt(7:0) =igcgt(7:0) |0x80;}if(hds=0){gdw(6:0) =gbdw(6:0);gt(7:0) =gbgt(7:0);}if(hds=2){gdw(6:0) =gcdw(6:0);gt(7:0) =gcgt(7:0);}if(hds=4){gdw(6:0) =gddw(6:0);gt(7:0) =gdgt(7:0);}Output_hdInput:gdw(6:0), gt(7:0)Output:hdw(8:0), ht(7:0)if(gt=0x17){hdw(8:0) =gdw(6:0);ht(7:0) =0x39;}if(gt=0x16){hdw(8:0) =gdw(6:0) |0x80;ht(7:0) =0x39;}if(gt=0x26){hdw(8:0) =gdw(6:0) |0xC0;ht(7:0) =0x39;}if(gt=0x07){hdw(8:0) =gdw(6:0) |0x100;ht(7:0) =0x39;}if(gt=0x06){hdw(8:0) =gdw(6:0) |0x180;ht(7:0) =0x39;}if(gt=0x05){hdw(8:0) =gdw(6:0) |0x1C0;ht(7:0) =0x39;}if(gt=0x04){hdw(8:0) =gdw(6:0) |0x1E0;ht(7:0) =0x39;}if(gt=0x03){hdw(8:0) =gdw(6:0) |0x1F0;ht(7:0) =0x39;}if(gt=0x02){hdw(8:0) =gdw(6:0) |0x1F8;ht(7:0) =0x39;}if(gt=0x11){hdw(8:0) =gdw(6:0) |0x1FC;ht(7:0) =0x39;}if(gt=0x91){hdw(8:0) =gdw(6:0) |0x1FE;ht(7:0) =0x39;}if(gt=0x97){hdw(8:0) =gdw(6:0);ht(7:0) =0x38;}if(gt=0x96){hdw(8:0) =gdw(6:0) |0x80;ht(7:0) =0x38;}if(gt=0x25){hdw(8:0) =gdw(6:0) |0xC0;ht(7:0) =0x38;}if(gt=0xA5){hdw(8:0) =gdw(6:0) |0xE0;ht(7:0) =0x38;}if(gt=0xA6){hdw(8:0) =gdw(6:0);ht(7:0) =0x37;}if(gt=0x14){hdw(8:0) =gdw(6:0) |0x40;ht(7:0) =0x37;}if(gt=0x24){hdw(8:0) =gdw(6:0) |0x50;ht(7:0) =0x37;}if(gt=0x94){hdw(8:0) =gdw(6:0) |0x60;ht(7:0) =0x37;}if(gt=0x23){hdw(8:0) =gdw(6:0) |0x70;ht(7:0) =0x37;}if(gt=0xA3){hdw(8:0) =gdw(6:0) |0x78;ht(7:0) =0x37;}dec_heInput:hw(9:0), x(3:0), y(15:0), z(15:0), ihw(9:0), ix(3:0), iy(15:0),iz(15:0)Output:hedw(8:0), heht(7:0)Description of Block dec_hc is shown before.Since patterns of group “he” are the inverse of group “hc”, dec_he issame as dec_hc with the input inverted. Note here that input hw ofdec_he is used as input ihw of dec_hc and input ihw of dec_he is used asinput hw of dec_hc. Similarly, xyz of dec_he is connected to ixyz ofdec_hc and vice versa.hedw(8:0) = hdw(8:0) of dec_hcModify htheht(7:4) = [0, 1, 0, 0]heht(3:0) = ht(3:0) of ht from dec_hcdec_hfInput:ihw(9:0), ix(3:0), iy(15:0), iz(15:0)Output:hfdw(8:0), hfht(7:0)Description of Block dec_hb is shown before.Since patterns of group “ht” are the inverse of group “hb”, dec_hf issame as dec_hb with the input inverted. Note that input ihw of dec_hf isused as input hw of dec_hb. Similarly, ixyz of dec_hf is conndcted toxyz of dec_hb.hfdw(8:0) = hdw(8:0) of dec_hbModify hthfht(7:4) = [0, 1, 0, 1]hfht(3:0) = ht(3:0) of ht from dec_hbHx Output MuxInput:hadw(7:0), hbdw(8:0), hcdw(8:0), hddw (8:0), hedw(8:0),hfdw(8:0),haht(7:0), hbht(7:0), hcht(7:0), hdht (7:0), heht(7:0), hfht(7:0),gm(3:0), State(3:0)Output:hdw(8:0), Htype(7:0)If(State< −4)State= −4;If(State> 4)State= 4;If(State= −4 or State= 4){if(gm=9){hdw(8:0) =hadw(8:0);Htype(7:0) =haht(7:0);}if(gm=0){hdw(8:0) =hbdw(8:0);Htype(7:0) =hbht(7:0);}if(gm=1){hdw(8:0) =hcdw(8:0);Htype(7:0) =hcht(7:0);}if(gm=2){hdw(8:0) =hddw(8:0);Htype(7:0) =hdht (7:0);}if(gm=3){hdw(8:0) =hedw(8:0);Htype(7:0) =heht(7:0);}}If(State= −2 or State= 2){if(gm=9){hdw(8:0) =hbdw(8:0);Htype(7:0) =hbht(7:0);}if(gm=0){hdw(8:0) =hcdw(8:0);Htype(7:0) =hcht(7:0);}if(gm=1){hdw(8:0) =hddw(8:0);Htype(7:0) =hdht(7:0);}if(gm=2){hdw(8:0) =hedw(8:0);Htype(7:0) =heht(7:0);}if(gm=3){hdw(8:0) =hfdw(8:0);Htype(7:0) =hfht(7:0);}}If(State= 0){if(gm=9){hdw(8:0) =hcdw(8:0);Htype(7:0) =hcht(7:0);}if(gm=0){hdw(8:0) =hddw(8:0);Htype(7:0) =hdht(7:0);}if(gm=1){hdw(8:0) =hedw(8:0);Htype(7:0) =heht(7:0);}if(gm=2){hdw(8:0) =hfdw(8:0);Htype(7:0) =hfht(7:0);}}


[0056]
FIG. 16 illustrates a block diagram of decoder output circuit 378. Decoder output circuit 378 includes a form 19-bit data word circuit 410. The data word circuit 410 receives the ‘g’ word gdw, and ‘h’ word hdw, ‘g’ type, ‘h’ type and state. Using calculations, the data word circuit 410 outputs the user data word I18:0. The operation of decoder output circuit 378 is performed according to the calculations in Table 18.
16TABLE 18Decoder OutputInput:gdw(6:0), hdw(8:0), Gtype(7:0), Htype(7:0), State(3:0)Output:I(18:0)if(State==−4 or 4){ if( (gt==0x07)&&(ht==0x19) ){I(18:16) = [0, 0, 0];  I(15:9) = gdw(6:0);I(8:0) = hdw(8:0); } if( (gt==0x17)&&)ht==0x29) ){I(18:16) = [0, 0, 1];  I(15:9) = gdw(6:0);I(8:0) = hdw(8:0); } if( (gt==0x97)&&(ht==0x08) ){I(18:15) = [0, 1, 0, 0];  I(14:8) = gdw(6:0);I(7:0)hdw(7:0); } if( (gt==0x06)&&(ht==0x19) ){I(18:15) = [0, 1, 0, 1];  I(14:9) = gdw(5:0);I(8:0) = hdw(8:0); } if( (gt==0x17)&&(ht==0x28) ){I(18:15) = [0, 1, 1, 0];  I(14:8) = gdw(6:0);I(7:0) = hdw(7:0); } if( (gt==0x16)&&(ht==0x29) ){I(18:15) = [0, 1, 1, 1];  I(14:9) = gdw(5:0);I(8:0) = hdw(8:0); } if( (gt==0x26)&&(ht==0x39) ){I(18:15) = [1, 0, 0, 0];  I(14:9) = gdw(5:0);I(8:0) = hdw(8:0); } if( (gt==0x96)&&(ht==0x08) ){I(18:14) = [1, 0, 0, 1, 0];  I(13:8) = gdw(5:0);I(7:0) = hdw(7:0); } if( (gt==0x05)&&(ht==0x19) ){I(18:14) = [1, 0, 0, 1, 0];  I(13:9) = gdw(4:0);I(8:0) = hdw(8:0); } if( (gt==0x16)&&(ht==0x28) ){I(18:14) = [1, 0, 1, 0, 0];  I(13:8) = gdw(5:0);I(7:0) = hdw(7:0); } if( (gt==0x26)&&(ht==0x38) ){I(18:14) = [1, 0, 1, 0, 1];  I(13:8) = gdw(5:0);I(7:0) = hdw(7:0); } if( (gt==0x25)&&(ht==0x39) ){I(18:14) = [1, 0, 1, 1, 0];  I(13:9) = gdw(4:0);I(8:0) = hdw(8:0); } if( (gt==0x35)&&(ht==0x49) ){I(18:14) = [1, 0, 1, 1, 1];  I(13:9) = gdw(4:0);I(8:0) = hdw(8:0); } if( (gt==0x97)&&(ht==0x06) ){I(18:13) = [1, 1, 0, 0, 0, 0];  I(12:6) = gdw(6:0);I(5:0) = hdw(5:0); } if( (gt==0x07)&&(ht==0x16) ){I(18:13) = [1, 1, 0, 0, 0, 1];  I(12:6) = gdw(6:0);I(5:0) = hdw(5:0); } if( (gt==0x04)&&(ht==0x19) ){I(18:13) = [1, 1, 0, 0, 1, 0];  I(12:9) = gdw(3:0);I(8:0) = hdw(8:0); } if( (gt==0x17)&&(ht==0x26) ){I(18:13) = [1, 1, 0, 0, 1, 1];  I(12:6) = gdw(6:0);I(5:0) = hdw(5:0): } if( (gt==0x14)&&(ht==0x29) ){I(18:13) = [1, 1, 0, 1, 0, 0];  I(12:9) = gdw(3:0);I(8:0) = hdw(8:0); } if( (gt==0x26)&&(ht==0x37) ){I(18:13) = [1, 1, 0, 1, 0, 1];  I(12:7) = gdw(5:0);I(6:0) = hdw(6:0); } if( (gt==0x25)&&(ht==0x38) ){I(18:13) = [1, 1, 0, 1, 1, 0];  I(12:8) = gdw(4:0);I(7:0) = hdw(7:0); } if( (gt==0x24)&&(ht=0x39) ){I(18:13) = [1, 1, 0, 1, 1, 1];  I(12:9) = gdw(3:0);I(8:0) = hdw(8:0); } if( (gt==0x35)&&(ht==0x48) ){I(18:13) = [1, 1, 1, 0, 0, 0];  I(12:8) = gdw(4:0);I(7:0) = hdw(7:0); } if( (gt==0x97)&&(ht==0x05) ){I(18:12) = [1, 1, 1, 0, 0, 1, 0];  I(11:5) = gdw(6:0);I(4:0) = hdw(4:0); } if( (gt==0x96)&&(ht==0x06) ){I(18:12) = [1, 1, 1, 0, 0, 1, 1];  I(11:6) = gdw(5:0);I(5:0) = hdw(5:0); } if( (gt==0x07)&&(ht==0x15) ){I(18:12) = [1, 1, 1, 0, 1, 0, 0];  I(11:5) = gdw(6:0);I(4:0) = hdw(4:0); } if( (gt==0x06)&&(ht==0x16) ){I(18:12) = [1, 1, 1, 0, 1, 0, 1];  I(11:6) = gdw(5:0);I(5:0) = hdw(5:0); } if( (gt==0x03)&&(ht==0x19) ){I(18:12) = [1, 1, 1, 0, 1, 1, 0];  I(11:9) = gdw(2:0);I(8:0) = hdw(8:0); } if( (gt==0x16)&&(ht==0x26) ){I(18:12) = [1, 1, 1, 0, 1, 1, 1];  I(11:6) = gdw(5:0);I(5:0) = hdw(5:0); } if( (gt==0x14)&&(ht==0x28) ){I(18:12) = [1, 1, 1, 1, 0, 0, 0];  I(11:8) = gdw(3:0);I(5:0) = hdw(5:0); } if( (gt==0x25)&&(ht==0x37) ){I(18:12) = [1, 1, 1, 1, 0, 0, 1];  I(11:7) = gdw(4:0);I(6:0) = hdw(6:0); } if( (gt==0x24)&&(ht==0x38) ){I(18:12) = [1, 1, 1, 1, 0, 1, 0];  I(11:8) = gdw(3:0);I(7:0) = hdw(7:0); } if( (gt==0x23)&&(ht==0x39) ){I(18:12) = [1, 1, 1, 1, 0, 1, 1];  I(11:9) = gdw(2:0);I(8:0) = hdw(8:0); } if( (gt==0x33)&&(ht==0x49) ){I(18:12) = [1, 1, 1, 1, 1, 0, 0];  I(11:9) = gdw(2:0);I(8:0) = hdw(8:0); } if( (gt==0x97)&&(ht==0x04) ){I(18:11) = [1, 1, 1, 1, 1, 0, 1, 0];  I(10:4) = gdw(6:0);I(3:0) = hdw(3:0); } if( (gt==0x96)&&(ht==0x05) ){I(18:11) = [1, 1, 1, 1, 1, 0, 1, 1];  I(10:5) = gdw(5:0);I(4:0) = hdw(4:0); } if( (gt==0x07)&&(ht==0x14) ){I(18:11) = [1, 1, 1, 1, 1, 1, 0, 0];  I(10:4) = gdw(6:0);I(3:0) = hdw(3:0); } if( (gt==0x06)&&(ht==0x15) ){I(18:11) = [1, 1, 1, 1, 1, 1, 0, 1];  I(10:5) = gdw(5:0);I(4:0) = hdw(4:0); } if( (gt==0x05)&&(ht==0x16) ){I(18:11) = [1, 1, 1, 1, 1, 1, 1, 0];  I(10:6) = gdw(4:0);I(5:0) = hdw(5:0); } if( (gt==0x24)&&(ht==0x37) ){I(18:11) = [1, 1, 1, 1, 1, 1, 1, 1];  I(10:7) = gdw(3:0);I(6:0) = hdw(6:0); }} if(State==−2 or 2){ if( (gt==0x97)&&(ht==0x19) ){I(18:16) = [0, 0, 0];  I(15:9) = gdw(6:0);I(8:0) = hdw(8:0); } if( (gt==0x07)&&(ht==0x29) ){I(18:16) = [0, 0, 1];  I(15:9) = gdw(6:0);I(8:0) = hdw(8:0); } if( (gt==0x17)&&(ht==0x39) ){I(18:16) = [0, 1, 0];  I(15:9) = gdw(6:0);I(8:0) = hdw(8:0); } if( (gt==0x96)&&(ht==0x19) ){I(18:15) = [0, 1, 1, 0];  I(14:9) = gdw(5:0);I(8:0) =hdw(8:0); } if( (gt==0x07)&&(ht==0x28) ){I(18:15) = [0, 1, 1, 1];  I(14:8) = gdw(6:0);I(7:0) = hdw(7:0); } if( (gt==0x06)&&(ht==0x29) ){I(18:15) = [1, 0, 0, 0];  I(14:9) = gdw(5:0);I(8:0) = hdw(8:0); } if( (gt==0x17)&&(ht==0x38) ){I(18:15) = [1, 0, 0, 1];  I(14:8) = gdw(6:0);I(7:0) = hdw(7:0); } if( (gt==0x16)&&(ht==0x39) ){I(18:15) = [1, 0, 1, 0];  I(14:9) = gdw(5:0);I(8:0) = hdw(8:0); } if( (gt==0x26)&&(ht==0x49) ){I(18:15) = [1, 0, 1, 1];  I(14:9) = gdw(5:0);I(8:0) = hdw(8:0); } if( (gt==0x06)&&(ht==0x28) ){I(18:14) = [1, 1, 0, 0, 0]  I(13:8) = gdw(5:0);I(7:0) = hdw(7:0); } if( (gt==0x05)&&(ht==0x29) ){I(18:14) = [1, 1, 0, 0, 1]  I(13:9) = gdw(4:0);I(8:0) = hdw(8:0); } if( (gt==0x17)&&(ht==0x37) ){I(18:14) = [1, 1, 0, 1, 0];  I(13:7) = gdw(6:0);I(6:0) = hdw(6:0); } if( (gt==0x16)&&(ht==0x38) ){I(18:14) = [1, 1, 0, 1, 1];  I(13:8) = gdw(5:0);I(7:0) = hdw(7:0); } if( (gt==0x26)&&(ht==0x48) ){I(18:14) = [1, 1, 1, 0, 0];  I(13:8) = gdw(5:0);I(7:0) = hdw(7:0); } if( (gt==0x35)&&(ht==0x59) ){I(18:14) = [1, 1, 1, 0, 1];  I(13:9) = gdw(4:0);I(8:0) = hdw(8:0); } if( (gt==0x97)&&(ht==0x16) ){I(18:13) = [1, 1, 1, 1, 0, 0];  I(12:6) = gdw(6:0);I(5:0) = hdw(5:0); } if( (gt==0x07)&&(ht==0x26) ){I(18:13) = [1, 1, 1, 1, 0, 1];  I(12:6) = gdw(6:0);I(5:0) = hdw(5:0); } if( (gt==0x05)&&(ht==0x28) ){I(18:13) = [1, 1, 1, 1, 1, 0];  I(12:8) = gdw(4:0);I(7:0) = hdw(7:0); } if( (gt==0x04)&&(ht==0x29) ){I(18:13) = [1, 1, 1, 1, 1, 1];  I(12:9) = gdw(3:0);I(8:0) = hdw(8:0); }} if(State==0){ if( (gt==0x97)&&(ht==0x29) ){I(18:16)[0, 0, 0];  I(15:9) = gdw(6:0);I(8:0) = hdw(8:0); } if( (gt==0x07)&&(ht==0x39) ){I(18:16)[0, 0, 1];  I(15:9) = gdw(6:0);I(8:0) = hdw(8:0); } if( (gt==0x17)&&(ht==0x49) ){I(18:16)[0, 1, 0];  I(15:9) = gdw(6:0);I(8:0) = hdw(8:0); } if( (gt==0x97)&&(ht==0x28) ){I(18:15) = [0, 1, 1, 0];  I(14:8) = gdw(6:0);I(7:0) = hdw(7:0); } if( (gt==0x96)&&(ht==0x29) ){I(18:15) = [0, 1, 1, 1];  I(14:9) = gdw(5:0);I(8:0) = hdw(8:0); } if( (gt==0x07)&&(ht==0x38) ){I(18:15) = [1, 0, 0, 0];  I(14:8) = gdw(6:0);I(7:0) = hdw(7:0); } if( (gt==0x06)&&(ht==0x39) ){I(18:15) = [1, 0, 0, 1];  I(14:9) = gdw(5:0);I(8:0) = hdw(8:0); } if( (gt==0x17)&&(ht==0x48) ){I(18:15) = [1, 0, 1, 0];  I(14:8) = gdw(6:0);I(7:0) = hdw(7:0); } if( (gt==0x16)&&(ht==0x49) ){I(18:15) = [1, 0, 1, 1];  I(14:9) = gdw(5:0);I(8:0) = hdw(8:0); } if( (gt==0x16)&&(ht==0x59) ){I(18:15) = [1, 1, 0, 0];  I(14:9) = gdw(5:0);I(8:0) = hdw(8:0); } if( (gt==0x96)&&(ht==0x28) ){I(18:14) = [1, 1, 0, 1, 0];  I(13:8) = gdw(5:0);I(7:0) = hdw(7:0); } if( (gt==0x07)&&(ht==0x37) ){I(18:14) = [1, 1, 0, 1, 1];  I(13:7) = gdw(6:0);I(6:0) = hdw(6:0); } if( (gt==0x06)&&(ht==0x38) ){I(18:14) = [1, 1, 1, 0, 0];  I(13:8) = gdw(5:0);I(7:0) = hdw(7:0); } if( (gt==0x05)&&(ht==0x39) ){I(18:14) = [1, 1, 1, 0, 1];  I(13:9) = gdw(4:0);I(8:0) = hdw(8:0); } if( (gt==0x16)&&(ht==0x48) ){I(18:14) = [1, 1, 1, 1, 0];  I(13:8) = gdw(5:0);I(7:0) = hdw(7:0); } if( (gt==0x25)&&(ht==0x59) ){I(18:14) = [1, 1, 1, 1, 1]  I(13:9) = gdw(4:0);I(8:0) = hdw(8:0); }}


[0057] In summary, a method (200) of encoding digital information in a system is provided. The method (200) includes receiving (202) a sequence of user bits and calculating (204) a running digital sum (RDS) of the system. In addition, a code word is generated (214) based on the sequence of user bits and the RDS of the system to maintain the RDS of the system calculated with the code word to within a selected range.

[0058] Another embodiment of the present invention relates to a system (100, 250) for generating a code word from a sequence of user bits. The system (100, 250) has an input circuit (254) adapted to receive the sequence of user bits and a calculation circuit (332) adapted to calculate the running digital sum (RDS) of the system. An encoder (250) is also provide that is adapted to generate a code word based on the sequence of user bits and the RDS of the system to maintain the RDS of the system calculated with the code word to within a selected range.

[0059] It is to be understood that even though numerous characteristics and advantages of various embodiments of the invention have been set forth in the foregoing description, together with details of the structure and function of various embodiments of the invention, this disclosure is illustrative only, and changes may be made in detail, especially in matters of structure and arrangement of parts within the principles of the present invention to the full extent indicated by the broad general meaning of the terms in which the appended claims are expressed. For example, the particular elements may vary depending on the particular application for the communication system while maintaining substantially the same functionality without departing from the scope and spirit of the present invention. In addition, although the preferred embodiment described herein is directed to a coding system for a disc drive, it will be appreciated by those skilled in the art that the teachings of the present invention can be applied to system such as satellite communications and cellular phones, without departing from the scope and spirit of the present invention.

Claims
  • 1. A method of encoding digital information in a system comprising : receiving a sequence of user bits; calculating a running digital sum (RDS) of the system; and generating a code word based on the sequence of user bits and the RDS of the system to maintain the RDS of the system calculated with the code word to within a selected range.
  • 2. The method of claim 1 and further comprising: generating a first segment of the code word based on the sequence of user bits and the RDS of the system, the first segment further having a RDS; and generating a second segment of the code word based on the sequence of user bits and the RDS of the first segment.
  • 3. The method of claim 2 wherein the sequence of user bits is 19 bits and the first segment and the second segment are both 10 bits.
  • 4. The method of claim 1 wherein the selected range is +/−4.
  • 5. The method of claim 1 wherein the sequence of user bits is 19 bits and the code word that is generated is 20 bits.
  • 6. The method of claim 1 and further comprising: separating the sequence of user bits into a first fragment, a second fragment and a third fragment based on the RDS of the system; mapping the second fragment to a first segment of the code word based on the length of the first fragment and the RDS of the system, the first segment having an RDS; mapping the third fragment to a second segment of the code word based on the length of the second fragment and the RDS of the first segment; and combining the first segment and the second segment to form the code word.
  • 7. The method of claim 6 wherein the sequence of user bits is 19 bits, the code word is 20 bits, the first fragment is less than 9 bits, the second fragment is less than 8 bits and the third fragment is less than 10 bits, wherein a number of bits in the first fragment, the second fragment and the third fragment is 19.
  • 8. A system for generating a code word from a sequence of user bits, comprising: an input circuit adapted to receive the sequence of user bits; a calculation circuit adapted to calculate the running digital sum (RDS) of the system; an encoder adapted to generate a code word based on the sequence of user bits and the RDS of the system to maintain the RDS of the system calculated with the code word to within a selected range.
  • 9. The system of claim 8, wherein the encoder further comprises: a first encoder circuit adapted to generate a first segment of a code word based on the sequence of user bits and the running digital sum of the system, the first segment further having an RDS; and a second encoder circuit adapted to generate a second segment of the code word based on the sequence of user bits and the running digital sum of the first segment.
  • 10. The system of claim 9 wherein the encoder further comprises: a third encoder circuit adapted to separate the sequence of user bits into first, second and third fragments based on a first state and transmit the second fragment to the first encoder circuit and transmit the third fragment to the second encoder circuit; a fourth encoder circuit adapted to separate the sequence of user bits into first, second and third fragments based on a second state and transmit the second fragment to the first encoder circuit and transmit the third fragment to the second encoder circuit; and a fifth encoder circuit adapted to separate the sequence of user bits into first, second and third fragments based on a third state and transmit the second fragment to the first encoder circuit and transmit the third fragment to the second encoder circuit.
  • 11. The system of claim 10 wherein the first encoder is adapted to select one of the second fragments from the third, fourth and fifth encoder circuits based on the RDS of the system and map said second fragment to the first segment of the code word and the second encoder is adapted to select one of the third fragments based on the RDS of the system and map the third fragment to the second segment of the code word.
  • 12. The system of claim 11 wherein the sequence of user bits is 19 bits, the code word is 20 bits, the first fragment is less than 9 bits, the second fragment is less than 8 bits and the third fragment is less than 10 bits, wherein a number of bits in the first fragment, the second fragment and the third fragment is 19.
  • 13. The system of claim 8, wherein the encoder is further adapted to: separate the sequence of user bits into a first fragment, a second fragment and a third fragment based on the RDS of the system; map the second fragment to a first segment of the code word based on the length of the first fragment and the RDS of the system, the first segment having an RDS; map the third fragment to a second segment of the code word based on the length of the second fragment and the RDS of the first segment; and combine the first segment and the second segment to form the code word.
  • 14. The system of claim 8 wherein the selected range is +/−4.
  • 15. The system of claim 8 wherein the sequence of user bits is 19 bits and the code word that is generated is 20 bits.
  • 16. The system of claim 8 and further comprising: a disc drive; a disc within the disc drive; and a write transducer adapted to receive the code word from the encoder and write the code word to the disc.
  • 17. An encoder system, comprising: means for receiving a sequence of 19 bits; means for calculating a running digital sum of the system; and means for generating a code word of 20 bits based on the sequence of user bits and the RDS of the system to maintain the RDS of the system calculated with the code word to within a selected range.
  • 18. The encoder system of claim 17 and further comprising: means for generating a first 10-bit segment of the code word bsed on the sequence of user bits and the RDS of the system, the first segment further having an RDS; and, means for generating a second 10-bit segment of the code word based on the sequence of user bits and the RDS of the first segment.
  • 19. The encoder system of claim 17 and further comprising: means for separating the sequence of user bits into a first fragment, a second fragment and a third fragment based on the RDS of the system; means for mapping the second fragment to a first segment of the code word based on the length of the first fragment and the RDS of the system, the first segment having an RDS; means for mapping the third fragment to a second segment of the code word based on the length of the second fragment and the RDS of the first segment; and means for combining the first segment and the second segment to form the code word.
  • 20. A method of decoding a code word, comprising: receiving a code word; identifying a state value associated with the code word; and generating a sequence of user bits based on the code word and the state value.
  • 21. The method of claim 20 and further comprising: separating the code word into a first segment and a second segment, generating a first portion of the sequence of user bits based on the first segment; and generating a second portion of the sequence of user bits based on the state value and the first segment.
  • 22. The method of claim 21 and further comprising: generating a third portion of the sequence of user bits based on the length of the first portion and the length of the second portion.
  • 23. The method of claim 21 wherein the sequence of user bits is 19 bits and the first segment and the second segment are both 10 bits.
  • 24. A digital communication system, comprising: a communication channel; an encoder system comprising: an input circuit adapted to receive the sequence of user bits; a calculation circuit adapted to calculate the running digital sum (RDS) of the system; an encoder adapted to generate a code word-based on the sequence of user bits and the RDS of the system to maintain the RDS of the system calculated with the code-word to within a selected range; and an output circuit adapted to transmit the code word to the communication channel; and a decoder system comprising: an input circuit adapted to receive a code word from the communication channel; a state evaluator adapted to identify a state value associated with the code word; and a decoder adapted to generate a sequence of user bits based on the code word and the state value.
  • 25. The system of claim 24, wherein the encoder further comprises: a first encoder circuit adapted to generate a first segment of a code word based on the sequence of user bits and the running digital sum of the system, the first segment further having an RDS; and a second encoder circuit adapted to generate a second segment of the code word based on the sequence of user bits and the running digital sum of the first segment.
  • 26. The system of claim 25 wherein the encoder further comprises: a third encoder circuit adapted to separate the sequence of user bits into first, second and third fragments based on a first state and transmit the second fragment to the first encoder circuit and transmit the third fragment to the second encoder circuit; a fourth encoder circuit adapted to separate the sequence of user bits into first, second and third fragments based on a second state and transmit the second fragment to the first encoder circuit and transmit the third fragment to the second encoder circuit; and a fifth encoder circuit adapted to separate the sequence of user bits into first, second and third fragments based on a third state and transmit the second fragment to the first encoder circuit and transmit the third fragment to the second encoder circuit.
  • 27. The system of claim 26 wherein the first encoder is adapted to select one of the second fragments from the third, fourth and fifth encoder circuits based on the RDS of the system and map said second fragment to the first segment of the code word and the second encoder is adapted to select one of the third fragments based on the RDS of the system and map the third fragment to the second segment of the code word.
  • 28. The system of claim 27 wherein the sequence of user bits is 19 bits, the code word is 20 bits, the first fragment is less than 9 bits, the second fragment is less than 8 bits and the third fragment is less than 10 bits, wherein a number of bits in the first fragment, the second fragment and the third fragment is 19.
  • 29. The system of claim 24, wherein the encoder is further adapted to: separate the sequence of user bits into a first fragment, a second fragment and a third fragment based on the RDS of the system; map the second fragment to a first segment of the code word based on the length of the first fragment and the RDS of the system, the first segment having an RDS; map the third fragment to a second segment of the code word based on the length of the second fragment and the RDS of the first segment; and combine the first segment and the second segment to form the code word.
  • 30. The system of claim 24 wherein the selected range is +/−4.
  • 31. The system of claim 24 wherein the sequence of user bits is 19 bits and the code word that is generated is 20 bits.
  • 32. The system of claim 24 wherein the decoder is further adapted to: separate the code word into a first segment and a second segment; generate a first portion of the sequence of user bits based on the first segment; and generate a second portion of the sequence of user bits based on the state value and the first segment.
  • 33. The system of claim 24 wherein the decoder is further adapted to: generate a third portion of the sequence of user bits based on the length of the first portion and the length of the second portion.
CROSS-REFERENCE TO RELATED APPLICATION

[0001] This application claims priority from U.S. Provisional Application 60/409,156 filed on Sep. 9, 2002 for inventor Kinhing P. Tsang and entitled DC FREE CODE DESIGN WITH STATE DEPENDENT MAPPING.

Provisional Applications (1)
Number Date Country
60409156 Sep 2002 US