Patent Application
20100254491
The subject matter disclosed herein relates to DC-offset compensation in digital receivers.
In digital communication systems, transmission signals are produced by the modulation of a carrier signal with digital data to be transmitted. The digital data is commonly transmitted in packets wherein each packet includes a number of data bits. After the transmitted signal is received, the signal requires demodulation in order to recover the data.
Radio receiver architectures commonly employ direct conversion receivers, such as homodyne receivers, to perform the demodulation of a received signal. A local oscillator operating at the carrier signal frequency is used to mix down the received signal to produce in-phase (I) and quadrature (Q) baseband signals. The direct conversion receiver converts the incoming carrier signal directly to baseband, in both I and Q components, without use of any intermediate frequencies. However, direct conversion receivers have some drawbacks. For example, a DC-offset can be introduced post-demodulation, due to a frequency offset between the transmitter and RX local oscillator. Additionally, in some systems the DC-offset component can be several decibels (dB) larger than the information signal, and thus DC-offset compensation is required for information signal recovery.
One way to compensate for DC-offset is to estimate the mean value of the received packet, subtract the estimate from the received signal, and then feed the signal to the decoder. However, the standard estimate of the mean value tends to introduce a bias in the calculated DC-offset if the number of transmitted ones and zeros are not equal in the data used for the estimate. The bias in the calculated DC-offset could be large enough to cause an increase the bit error rate of the receiver.
Therefore, there is a need for an enhanced method and system to remove DC-offset components.
Briefly, a DC-offset component compensation system is presented. The system includes a sorter to separate positive samples and negative samples of the input signal. The system further includes a positive sample average generator for calculating a positive sample average according to a number of positive samples in the input signal and a negative sample average generator for calculating a negative sample average according to a number of negative samples in the input signal. A balanced average generator is provided for receiving positive and negative sample averages from the positive and negative sample average generators and for generating a reference signal. The system further includes a subtractor for subtracting the reference signal from the input signal to generate a DC-offset compensated output signal.
In one embodiment, a digital radio receiver system is provided. The digital radio receiver system includes a radio front end to receive a modulated signal, and a digital receiver module comprising an analog to digital converter to digitize the modulated signal and a digital down converter to convert the digitized modulated signal to a baseband signal. A baseband processor having a DC compensating module, a timing recovery module, a bit detector, and a frame synchronization module is provided. The baseband processor is configured to generate a demodulated DC-offset compensated output signal. The digital receiver module and the baseband processor are implemented on a digital processor. The DC compensating module implements a sorter to compute separate positive sample and negative sample averages and a balanced average generator to generate a DC-offset compensated output signal.
In one embodiment, a method for compensating a DC-offset in a digital receiver is presented. The method includes segregating a positive sample and a negative sample from an input signal and computing autoregressive averages of the positive samples and the negative samples. The method further includes adding the averages of the positive samples and the negative samples, calculating a balanced average of the added averages, subtracting the balanced average from the input signal, and generating a DC-offset compensated output signal from the subtraction.
These and other features, aspects, and advantages of the present invention will become better understood when the following detailed description is read with reference to the accompanying drawings in which like characters represent like parts throughout the drawings, wherein:
Radio front-end module 12 is configured to amplify signals received from an antenna 18. Digital receiver module 14 includes an analog to digital converter 20 to convert the signals from radio front-end module 20 to digital signals. Digital receiver module 14 further includes a digital down converter 22 (DDC) to convert a digitized signal centered at a carrier frequency to a base-band signal centered at zero frequency. In addition to down conversion, DDCs typically decimate to a lower sampling rate, allowing further signal processing by lower speed processors.
Traditional DC compensation techniques include simple averaging techniques. In binary digital receivers employing non-return-to-zero (NRZ) modulating waveforms, such detection techniques include polarity comparisons. In such techniques, a positive binary 1 may be detected when the demodulated waveform is greater than zero (e.g. a positive voltage), and a negative binary 0 may be detected when the demodulated waveform is less than zero (e.g. a negative voltage). However, the zero (or DC) level may drift with respect to a fixed external reference, giving rise to a DC-offset. A simple average of the detected waveform, as used in the art, can be biased if the number of transmitted 1s and 0s is not equal over a short duration resulting in incorrect DC compensation. Such DC-offset in the signal may degrade the receiver bit error performance along with the presence of noise. Embodiments described herein use balanced averaging to overcome such shortcomings discussed above.
In one example of operation, the sorter 42 receives demodulated input signal 44 and segregates the positive samples 46 and the negative samples 48 from the input signal 44. The input signal 44 is also buffered during these operations into the input signal buffer 61. Input signal buffer 61, for example, may include a first in first out (FIFO) memory. Divider 54 computes the positive sample average 47 by way of dividing the added positive samples (from positive sample adder 50) with the number of positive samples 53 stored in counter 52. Similarly, divider 60 computes the negative sample average 49 by way of dividing the added negative samples (from negative sample adder 56) with the number of negative samples 57 stored in counter 58. The mean generator is configured to generate a reference signal 65 by multiplying a fraction (for example 0.5) by the summed up positive and negative sample averages from summer 62. Subtractor 66 is configured for subtracting the reference signal 65 from the input signal 44 (from the input signal buffer 61) to generate a DC-offset compensated output signal 68. A bit detector may be configured to receive such output signal 68 to detect positive binary 1 when the output signal 68 is greater than zero (e.g. a positive voltage). Further, a negative binary 0 may be detected when the output signal 68 is less than zero (e.g. a negative voltage).
During an operation of the DC compensating system 74, input signal 44 is sorted out, one sample at a time, into positive samples 46 and negative samples 48 by sorter 42 depending on the polarity of the sample. An autoregressive averaging is performed by the first autoregressive loop and the second autoregressive loop. The first autoregressive loop adds the sorted positive sample 46 to the autoregressive coefficient-scaled contents of memory register 80 at the positive sample adder 50. The operation is performed for every new incoming positive sample from sorter 42.
It may be noted that the loop calculations are performed according to corresponding polarity of the sample. For example, only one of the two loops is active for a given input sample, wherein the first autoregressive loop is for positive samples and the second autoregressive loop for negative samples. In an exemplary embodiment, if a positive sample is detected, then the first autoregressive loop is in operation updating the value in positive memory register 80. The second autoregressive loop remains idle, and the value of negative memory register 84 remains unchanged. Similarly if a negative sample is detected, then the second autoregressive loop is in operation, updating the value in the negative memory register 84. The first autoregressive loop remains idle, and the value of positive memory register 80 remains unchanged. Further, the two loops include multiplying the stored samples (in memory registers 80, 84) with an autoregressive co-efficient 76 at the multipliers 78 and 82 respectively for the positive samples and the negative samples.
For each input sample of either polarity (positive or negative) autoregressive positive sample average 86 and autoregressive negative sample average 88 are summed up at adder 90 and multiplied by a fraction, for example 0.5, within the balance average generator. Gain multiplier 92 is coupled to the balance average generator and multiplies the balanced averages 91 with the gain co-efficient 94 (which is one minus the autoregressive co-efficient 76) to generate a normalized balanced average 93. Subtractor 66 is configured to subtract normalized balanced average 93 from input signal 44 to generate the DC-offset compensated output signal. A bit detector (not shown) may be coupled to subtractor 66 for further processing of the output signal 96 as discussed earlier.
The output of the first fixed AR averaging loop (a fixed point autoregressive positive sample average 108) and the second AR averaging loop (a fixed point autoregressive negative sample average 110) are added at an adder 112. A gain multiplier 92 coupled to a gain co-efficient 94 is configured to normalize the balanced averages 91. A rounding block 114 and a right bitwise arithmetic shifter 116 are coupled to the gain multiplier 92. A subtractor 66 configured to generate an output signal 118 is coupled to the right bitwise arithmetic shifter 116 and the input signal 44.
In one example of operation of the DC compensating system 100 implementing a fixed point autoregressive average generator, multiple bits (or samples) of input signal 44 are sorted, one sample at a time, into positive samples 46 and negative samples 48 by sorter 42 depending on the polarity of the sample. A fixed point autoregressive averaging is performed by the first fixed point autoregressive loop and the second fixed point autoregressive loop. The first fixed point autoregressive loop performs a bitwise left shift at arithmetic shifter 102. The left shifted samples are summed with the autoregressive coefficient-scaled contents of register 80 at the positive sample adder 50. The added positive samples are rounded in a rounding module 106, and then right shifted at right bitwise arithmetic shifter 104. Right shifted samples are stored in positive memory register 80. The operation is performed for every new incoming positive sample from sorter 42.
It may be noted that the loop calculations are only performed when a sample of the correct polarity is present. For example, only one of the two loops is active for a given input sample, wherein the first fixed point autoregressive loop is for positive samples and the second fixed point autoregressive loop for negative samples. In an exemplary embodiment, if a positive sample is detected, then the first fixed point autoregressive loop is in operation updating the value in positive memory register 80. The second fixed point autoregressive loop remains idle, and the value of negative memory register 84 remains unchanged. Similarly if a negative sample is detected, then the second fixed point autoregressive loop is in operation, updating the value in negative memory register 84. The first fixed point autoregressive loop remains idle, and the value of positive memory register 80 remains unchanged. Further, the two loops include multiplying the stored samples (in memory registers 80, 84) with an autoregressive co-efficient 76 at the multipliers 78 and 82 respectively for the positive samples and the negative samples.
For each input sample of either polarity (positive or negative), fixed point autoregressive positive sample average 108 and fixed point autoregressive negative sample average 110 are summed up at adder 112 and multiplied by the gain co-efficient 94 at the gain multiplier 92 coupled to the summer 112. Normalized signal 111 from adder 112 is rounded in a rounding block 114. A rounded sample 115 is obtained by right shifting samples bitwise at the arithmetic shifter 116. Subtractor 66 is configured to subtract the shifted samples 115 from input signal 44 to generate the DC-offset compensated output signal 118. A bit detector may be coupled to subtractor 66 for further processing the output signal 118 as discussed earlier.
Advantageously, various embodiments of the invention, when implemented within DC compensating systems eliminates the need for “spectral whitening” at the transmitter and makes the receiver much more versatile when dealing with long runs of 1s or 0s. Further, for receivers designed for frequency modulated (FM) signals, embodiments of the invention help in mitigating the effects of frequency mismatch that may bias the output signal such that there are no zero crossings, resulting in effective non-return-to-zero detection and synchronization.
While only certain features of the invention have been illustrated and described herein, many modifications and changes will occur to those skilled in the art. It is, therefore, to be understood that the appended claims are intended to cover all such modifications and changes as fall within the true spirit of the invention.
