Patent Application
20070140292
The present disclosure pertains to communication systems and, more particularly, to de-interleaver synchronization methods and apparatus.
As broadcast technology and digital communication has progressed, the communication of audio, video, and data has moved from communications between a fixed transmitter (e.g., a television broadcaster) and a fixed receiver (e.g., a television in a viewer's home) to communications that are received and processed by mobile devices (e.g., cellular telephones, etc.). One standard for communications to mobile devices is the Digital Video Broadcasting-Handheld (DVB-H) standard, which is a technical specification for bringing broadcast services to handheld receivers. This standard was formally adopted as ETSI standard EN 302 304 in November 2004.
DVB-H is the latest development within the set of DVB transmission standards. DVB-H technology adapts the successful Digital Video Broadcasting-Terrestrial (DVB-T) system for digital terrestrial television to the specific requirements of handheld, battery-powered receivers. DVB-H offers a downstream channel at high data rates that can be used standalone or as an enhancement of mobile telecommunications networks, which many typical handheld terminals are able to access.
DVB-H uses a coded orthogonal frequency domain modulation (OFDM) scheme such that data are modulated and de-modulated in blocks by Fast Fourier Transform (FFT) and Inverse Fast Fourier Transform (IFFT) functions. DVB-H allows for 2048 (2K), 4K, and 8K point FFTs and IFFTs. A subset of the carriers in these blocks contains useful data. The remaining carriers are pilot carriers, transmission parameter signaling (TPS) carriers, or empty carriers. Nevertheless, the notation of the 2K, 4K, or 8K block or symbol is used throughout this document to refer to the entire set of useful data carriers.
To provide error correction functionality, concatenated convolutional and Reed-Solomon (RS) codes are used. Interleaving and de-interleaving of data is an important aspect of the encoding and decoding process.
Additionally, DVB-H uses time slicing technology to reduce power consumption for small handheld terminals. That is, information is transmitted as data bursts in small time slots. The front end of the receiver switches on only for the time slot when the data burst of a selected service is on air. Within this short period of time a high data rate is received and can be stored in a buffer. This buffer can either store the downloaded applications or play out live streams. The achievable power saving depends on the relation of the on/off-time. In DVB-H synchronization between the data transmitter and the data receiver must be achieved before received data is meaningful. To conserve power in the mobile unit, rapid synchronization before each time slot is important. That is, ideally the receiver should be powered for a minimal amount of time to synchronize before receiving information in the time slot. As will be appreciated by those having ordinary skill in the art, at high data rates synchronization time makes a large contribution to the duty cycle of the receiver.
An added feature of the DVB-H standard is that DVB-H accommodates a deep symbol interleaver. The standard symbol interleaver used in DVB-H interleaves the data in each OFDM symbol independently. The deep symbol interleaver uses the interleaver pattern used in the 8K OFDM mode to interleave multiple symbols if the system is using the 2K or 4K symbol size. Thus, the deep symbol interleaver interleaves data from two consecutive OFDM symbols if the 4K OFDM mode is being used and interleaves data from four consecutive OFDM symbols if the 2K OFDM mode is being used.
In standard operation, the DVB-H symbol interleaver alternates between two different patterns in consecutive realizations. These patterns are denoted as the even interleaver phase and the odd interleaver phase. In order to receive the DVB-H signal properly, the receiver must alternate between the de-interleaver patterns corresponding to the correct phases in lockstep with the alternating interleaver phases at the transmitter.
When the standard interleaver is in use, the receiver can determine the correct de-interleaver phase to use from the scattered pilot pattern. Since the pilot pattern has a period of four OFDM symbols, specification of the correct pilot phase in the current symbol also specifies the correct de-interleaver phase to use. This approach fails to synchronize the de-interleaver, however, when the 2K OFDM mode is combined with the deep symbol interleaver. Since the deep symbol interleaver interleaves four consecutive 2K symbols, the knowledge of the correct pilot phase does not enable the receiver to determine the correct deep symbol de-interleaver pattern.
One proposed solution is to perform synchronization in 2K mode with a transmission parameter signaling (TPS), but this is not desirable. As noted above, a symbol de-interleaver must be synchronized before every time slot. Using TPS information for synchronization requires up to 68 symbols for synchronization. Thus, to ensure synchronization by the start of the time slot, the receiver must be awake at least 68 symbols before the time slot to accommodate worst-case synchronization delay. As will be readily appreciated by those having ordinary skill in the art, this synchronization time reduces the power efficiency of the receiver.
Although the following discloses example systems including, among other components, hardware and software executed on hardware, it should be noted that such systems are merely illustrative and should not be considered as limiting. For example, it is contemplated that any or all of these hardware and software components could be embodied exclusively in dedicated hardware, exclusively in software, exclusively in firmware or in some combination of hardware, firmware and/or software. Accordingly, while the following describes example systems, persons of ordinary skill in the art will readily appreciate that the examples are not the only way to implement such systems.
As shown in
As described below in detail, the transmitter 102 receives programming content from various sources and processes and broadcasts the same via an antenna 106 to the mobile unit 104. Programming content may take various forms such as, for example, audio information, video information, data, and/or any combination of audio, video, or data. The programming content may be provided to the transmitter 102 in digital and compressed format. For example, the programming content may be video that is compressed into a Moving Pictures Experts Group (MPEG) format, such as MPEG-1, MPEG-2, or the like. Alternatively, the programming content may be provided to the transmitter 102 in an analog format and the transmitter 102 may digitize the same. The transmitter 102 is compliant with the DVB-H specification entitled “Annex 2 ETS 300 744 with 4k.doc,” which is available from a number of sources and is incorporated herein by reference, and processes information according to the DVB-H standard. The transmitter 102 outputs DVB-H signals for transmission to the antenna 106, which distributes the same over a geographical area. Of course, while one antenna 106 is shown in
The mobile unit 104 receives the transmitted DVB-H signals and processes the same to produce, for example, video and audio that may be observed and heard by a user of the mobile unit 104. For example, the mobile unit 104 may include a display screen 108 on which video included in the programming content may be displayed. As described in detail below, the mobile unit 104 may efficiently synchronize the de-interleaver of the mobile unit to handle 2K interleaved information. Thus, as described below, the mobile unit 104 may realize relatively lower power consumption relative to TPS de-interleaver synchronization.
As shown in
The multiplexer 202 receives a bitstream, which may include a number of MPEG-2 packets, such as the one shown at reference numeral 300 of
Referring briefly to
The result of the operation of the multiplexer 202 is a bitstream such as that shown in
The bitstream from the multiplexer 202, such as the bitstream shown in
The output of the outer coder 204 is provided to the outer interleaver 206. The outer interleaver 206 may be, for example, a convolutional interleaver having 12 branches, with each branch having a different delay and the first branch having no delay. When the outer interleaver 206 operates, the synchronization headers 502 always follow the no delay path. Thus, as shown at reference numeral 600 of
The output of the outer interleaver 206 is coded by an inner coder 208, which may be implemented as a known convolutional encoder and the bits may be interleaved by the inner bit interleaver 210. As will be readily appreciated by those having ordinary skill in the art, the inner bit interleaver 210 may shuffle, for example, 126 bits in a known and predictable manner.
Subsequently, the shuffled bits are coupled to an inner symbol interleaver 212 that may shuffle symbols in 8K, 4K, or 2K segments. As is known by those having ordinary skill in the art, 2K OFDM symbols are combined with virtual 8K interleaver symbols, which may be odd and even phases of a four symbol pilot signal, to produce an 8K symbol stream, which will completely fill an 8K symbol buffer in an inner bit de-interleaver. For example, referring to
Because the 2K symbols are combined with alternating even and odd symbol patterns to generate an 8K symbol stream (as shown in
The shuffled symbols from the inner symbol interleaver 212 are then mapped to a Quadrature Amplitude Modulation (QAM) constellation by the mapper 214. As will be readily appreciated by those having ordinary skill in the art, groups of bits may be mapped to a single constellation point. For example, two bits may be mapped to a single point in a Quadrature Phase Shift Keying (QPSK) constellation, four bits may be mapped to a single 16-QAM constellation point, or six bits may be mapped to a single 64-QAM constellation point.
Data representing the constellation points (e.g., in-phase and quadrature magnitudes) are processed by the OFDM 216 to produce carriers representing the constellation points. The carriers are generated in the frequency domain and processed by an IFFT to produce a time domain signal that is converted to an analog format by the D/A 218 and appropriately upconverted by the RF block 220. The output of the RF block 220 may be further amplified as appropriate for broadcast by the antenna 106.
Importantly, no matter what coding or interleaving is used in the transmit lineup 200, the synchronization bytes (e.g., 0×47 or 0×B8) preceding every 203 bytes of information 604 are visible. As described below, it is this information that will be used to quickly synchronize a receive lineup.
An example receive lineup, such as may be found in the mobile unit 104 of
As described above, the transmit lineup 200 receives a bitstream, such as an MPEG bitstream, and converts that bitstream into signals for transmission. In operation, the receive lineup 800 receives the transmitted signals and processes such signals to recover the bitstream originally provided to the transmit lineup 200. In this manner, the bitstream may be distributed to multiple mobile units as a broadcast signal and those mobile units may process the broadcast signal to receive the bitstream. In addition, the receive lineup 800 uses information in the stream to quickly synchronize the inner symbol de-interleaver 812 even when 2K symbol interleaving is used by the transmit lineup 200.
The antenna 802 receives the broadcast signal including the OFDM components that were used to transmit coded and interleaved information. The signals received by the antenna 802 are processed by the receive RF block 804, which may downconvert or otherwise process the received signals to baseband signals before they are converted to the digital signals by the A/D 806 and equalized by the equalizer 808.
The equalized signals, which represent in-phase and quadrature magnitudes, are mapped to constellation points. For example, if QPSK is used, the in-phase and quadrature components are mapped to a constellation QPSK point representing two symbols. By way of an alternative example, if 64-QAM is used for modulation, the in-phase and quadrature components are mapped to a constellation point representing six symbols. That is, the mapper 810 performs the inverse of the mapping performed by the mapper 214 of
The output of the mapper 810 is provided to the inner symbol de-interleaver 812. As described in further detail below in conjunction with an example implementation of the inner symbol de-interleaver, the inner symbol de-interleaver 812 buffers 8K symbols and attempts to de-interleave the symbols, but must first be synchronized. If, for example, 8K or 4K interleaving was used in the transmit lineup 200, the inner symbol de-interleaver 812 easily synchronizes and de-interleaves the symbols. However, if 2K interleaving was performed with odd and even symbol patterns, the synchronization detector 818 works with the inner symbol de-interleaver 812 to achieve synchronization. As described in detail below, the synchronization detector 818 searches for the synchronization headers at the output of the inner decoder 816. Synchronization headers are spaced every 204 bytes. Therefore, when a number of consecutive synchronization headers are received with the proper spacing the synchronization detector 818 informs the inner symbol de-interleaver 812 that it is properly phased. The situation in which a number of consecutive and properly spaced synchronization headers are detected is commonly referred to as Reed-Solomon lock (RS lock).
If the interleaving is 4K or 8K interleaving, the remainder of the system functions as is known by those having ordinary skill in the art. Thus, the remaining description will focus on the case in which 2K interleaving with odd and even symbol patterns are used for interleaving. In this case, the inner symbol de-interleaver 812 is either properly phased with respect to the buffered symbols or is improperly phased. If phasing is proper, the inner bit de-interleaver 814 and the inner decoder 816 cooperate to result in an output signal from the inner decoder 816 including a number of consecutive synchronization headers (e.g., 0×47 or 0×B8) (i.e., RS lock has been achieved). That is, the output of the inner decoder 816 is an MPEG transport stream that looks similar to the bitstream 600 of
Conversely, if the phasing of the inner symbol de-interleaver 812 is not synchronized, an appropriate number of consecutive synchronization headers will not be received by the synchronization detector 818 (i.e., RS lock has not been achieved). Thus, the synchronization detector 818 will inform the inner symbol de-interleaver 812 to correct synchronization. As described in detail below, the signal from the synchronization detector 818 may inhibit phase changes in the inner symbol de-interleaver 812 until RS lock is achieved. In most cases, worst case synchronization time will be 8 OFDM symbols, which is a significant decrease over the time is takes to synchronize using TPS bits. When RS lock has been achieved, the inner symbol de-interleaver 812 resumes the odd and even symbol pattern alternations to remain synchronized. When synchronization is achieved, the inner symbol de-interleaver 812 may re-process symbols that were processed with the incorrect synchronization, thereby recovering information that was missed during asynchronous periods. Alternatively, the inner symbol de-interleaver 812 may process received symbols with two patterns that are out of phase with one another, which will result in one of the processed bitstreams being synchronized. The inner symbol de-interleaver 812 may then select the proper bitstream for output.
As will be readily appreciated, once synchronization is achieved, the outer de-interleaver 820, the outer decoder 822, and the demultiplexer 824 function to reconstruct the MPEG bitstream that was encoded, interleaved, modulated, and transmitted.
As shown in
The comparator 902 may rely on a list of synchronization bytes stored in the synchronization byte storage 904 as a basis for comparison. For example, the synchronization byte storage 904 may store 0×47 and 0×B8. Alternatively, any other information that may be used as an indicator of inner de-interleaver synchronization may be stored in the synchronization byte storage 904.
In operation, when the comparator 902 detects a number of consecutive matches (i.e., matches spaced 204 bytes apart) between the symbols from the inner decoder and the synchronization bytes stored in the synchronization byte storage 904 (i.e., RS lock), the comparator 902 outputs an enable signal to the inner symbol de-interleaver 812 to enable the inner symbol de-interleaver to alternate between odd and even symbols patterns to maintain synchronization.
In the alternative, when no match exists (i.e., when RS lock is not achieved), the comparator 902 does not output the enable signal and the inner symbol de-interleaver 812 is prevented from switching between odd and even symbol patterns and, therefore, only outputs a single symbol pattern (i.e., either the odd symbol pattern or the even symbol pattern). This mode of attempting to find synchronization will continue until synchronization is achieved or TPS information has been processed to determine the correct interleaver mode. Further detail regarding the operation of the inner symbol de-interleaver 818 is provided below.
As shown in
In particular, when enabled (i.e., when RS lock is achieved), the selector 1010 alternates between enabling the even phase pattern generator 1006 and the odd phase pattern generator 1008 every four symbols to maintain synchronization. However, when synchronization is not achieved (i.e., no RS lock), the selector 1010 is not enabled and, therefore, does not alternatively enable the pattern generators 1006, 1008. Rather, in such an instance, the selector 1010 only enables one of the pattern generators 1006, 1008, and continues to enable that symbol pattern generator until synchronization is achieved, as detected by the synchronization detector 818. Because, as described above, the synchronization header information is not disturbed by the encoding and interleaving process, fixing the symbol pattern combined with the buffered 8K signal will eventually result in synchronization when received data has been combined with the selected symbol pattern (i.e., odd or even) selected by the receiver to achieve synchronization.
A flow diagram of an example synchronization process 1100 is shown in
The process 1100 may be initiated by, for example, a mobile unit, such as the mobile unit 104 of
When initiated, the process 1100, fixes the phase of the symbol de-interleaver (block 1102). For example, the process 1100 may set the symbol de-interleaver to use only the odd symbol pattern or only the even signal pattern. Fixing the symbol pattern to either odd or even enables a determination as to when synchronization occurs because when the symbol pattern is synchronized, MPEG synchronization bytes will be visible, as described below.
After the phase of the symbol de-interleaver is fixed (block 1102), the process 1100 receives and buffers incoming symbols (block 1104). The buffered symbols are then de-interleaved using the fixed phase of the symbol de-interleaver (block 1106). Of course, the synchronization may not be correct for the chosen symbol de-interleaver phase and the information resulting from the symbol de-interleaving may be unintelligible or meaningless. On the other hand, if synchronization is proper using the fixed symbol de-interleaver phase, the result of the de-interleaving will be subsequently meaningful, as described below.
To determine if synchronization is proper, the process 1100 performs bit de-interleaving on the de-interleaved symbols (block 1108) and performs inner decoding on the results (block 1110). At this point, the process 1100 determines if RS lock has occurred. In one example, RS lock may be determined by receipt of a sufficient number of consecutive synchronization bytes, such as synchronization bytes from MPEG headers (i.e., 0×47 and 0×B8), in the decoded and de-interleaved information (block 1112).
When synchronization bytes (or a sufficient number of them) are detected (i.e., RS lock has occurred) (block 1112), the phase of the symbol de-interleaver is proper for the frame being processed and, therefore, the phase of the symbol de-interleaver will need to change (e.g., from odd to even or from even to odd) to the properly synchronized with the next frame of symbols. Thus, when synchronization bytes are detected (block 1112), the process begins symbol de-interleaver phase alternation (block 1114), which will keep the de-interleaver in synchronization with the received symbols.
If synchronization bytes are not found or the number of consecutive synchronization bytes is not sufficient (i.e., RS lock has not been achieved) (block 1112), the process 1100 may determine if the number of bytes processed without synchronization has exceeded a byte count. If the byte count has not been exceeded the de-interleaver synchronization is improper, but will be proper at a future time when the transmitted signal is interleaved with a different phase symbol pattern, which occurs every four symbols at the transmitter. Thus, the process 1100 continues to receive and buffer incoming symbols (block 1104) and to process those symbols according to blocks 1106, 1108, and 1110, until synchronization bytes are detected (block 1112).
Once synchronization (i.e., RS lock) is achieved, the process 1100 may end or pass control back to a calling routine because the inner symbol de-interleaver is synchronized and, therefore, meaningful data may be received and processed.
The odd phase branch 1202 includes an inner symbol de-interleaver 1210 having an initial phase fixed to be odd. The inner symbol de-interleaver 1210 is coupled to an inner bit de-interleaver 1212, which is further coupled to an inner decoder 1214. An output from the inner decoder 1214 is coupled to a synchronization detector 1216.
The even phase branch 1204 is substantially similar to the odd phase branch 1202, but includes an inner symbol de-interleaver 1220 having an initial phase fixed to be even. The inner symbol de-interleaver 1220 is coupled to an inner bit de-interleaver 1222, which is further coupled to an inner decoder 1224. An output from the inner decoder 1224 is coupled to a synchronization detector 1226.
In operation, symbols from the mapper are coupled to both of the de-interleavers 1210 and 1220. As noted above, the de-interleavers 1210 and 1220 have opposite, fixed initial phases. Thus, the phase of one of the de-interleavers 1210 or 1220 will be proper. When the phase is proper, information from the inner decoder (e.g., either the inner decoder 1214 or the inner decoder 1224) will include synchronization information (e.g., a synchronization byte). The synchronization information, or consecutive occurrences thereof, is detected by a synchronization detector associated with the either the odd phase branch 1202 or the even phase branch 1204. The synchronization detector that detects the synchronization information (i.e., RS lock) informs the inner symbol de-interleaver associated with the detected synchronization information to begin phase alternation to maintain synchronization. The synchronization detector that does not detect synchronization information and, therefore, does not achieve RS lock, because its branch is not properly synchronized will eventually disable its associated inner symbol de-interleaver. The determination to disable the unsynchronized inner symbol de-interleaver may be based on an elapsed time since synchronization was detected, or may be based on communication from the synchronization detector that detected synchronization.
When synchronization bytes are detected (block 1312), the process 1300 begins symbol phase alternation of the de-interleaver from which the synchronization was detected (block 1314). Subsequently, the de-interleaver from which synchronization was not detected is disabled (block 1316).
A synchronization detector 1430 receives output from each of the inner decoders 1414 and 1424 and determines which of the branches 1402 or 1404 is synchronized by examining the decoder outputs for synchronization bytes. When a number of properly spaced synchronization bytes are received (i.e., when RS lock is achieved), the synchronization detector 1430 informs an arbiter 1432 of the branch (i.e., the branch 1402 or the branch 1404) from which the synchronization bytes came. The arbiter 1432 then selects for output the corresponding output from the inner decoder 1414 or 1424. Subsequently, the arbiter 1432 alternates selection of the odd and even branches to maintain synchronization and the synchronization detector 1430 is no longer needed for that time slot.
As shown in
As shown in
The processor 1602 may be any type of processing unit, such as a microprocessor and/or a DSP. The processor 1602 may include on-board A/D and D/A converters.
The memories 1604 that are coupled to the processor 1602 may be any suitable memory devices and may be sized to fit the storage and operational demands of the system 1600. The memories 1604 may also store instructions to implement the receive lineup of
An input port 1614 may be coupled to an antenna or other hardware from which input signals, such as broadcast signals, are provided.
The display device 1616 may be, for example, a liquid crystal display (LCD) display or any other suitable device that acts as an interface between the processor 1602 and a user. The display device 1616 includes any additional hardware required to interface a display screen to the processor 1602.
Although certain apparatus constructed in accordance with the teachings of the invention have been described herein, the scope of coverage of this patent is not limited thereto. On the contrary, this patent covers every apparatus, method and article of manufacture fairly falling within the scope of the appended claims either literally or under the doctrine of equivalents.
