The present invention is related to a debounce circuit, and particularly to a debounce circuit adopting D flip-flops.
During a system control process, signals are transmitted between components where the output signal of the previous stage usually serves as the input signal of the next stage. However, during transmitting signals, the signals output from the components, such as the signals input by a keyboard or keys, are not ones with ideal and perfect waveforms. According to the physical nature, when a characteristic or an electrical level is instantly changed, it is unable to change the state immediately. Instead, a reaction is produced, and before the signal enters the stable output state, a bounce phenomenon occurs where multiple digits 0 and 1 alternately move up and down in view of digital signal. The phenomenon makes the system treat the signal at the input terminal thereof as a continuous input signal, which leads a state misjudgement and an error message.
In particular for some devices of a system, in terms of the setting of logic judgment, once a state-changing phenomenon is detected out, the system would enter a phase to process the voltage or the error message. Even further, an unstable signal may cause a system shutdown or crash. In this regard, prior to inputting the output signals of the devices to the components of the next stage, a debounce circuit is used to debounce the signals such that the input signals are transferred to the output signals through a debounce delay buffer until the state gets stable; and at the time, the signals are input to the components of the next stage.
The debounce circuit of the prior art usually takes samples of an input signal, and the sampling frequency must be more than ten times higher than the frequency of the input signal. When the input signal is in transition (for example, from logic value 0 to 1 or from 1 to 0) and the sampled input signal contains consecutive is or Os, the system determines that the input signal has reached to a steady state and can output the debounced signal.
However, the sampling frequency required for the debounce circuit of the prior art must be more than ten times higher than the frequency of the input signal. For some electronic devices, it is not possible to provide the signal with such high sampling frequency. Further, since the conventional debounce circuit must continuously sample a certain number of consecutive is or Os to confirm that the input signal has reached to a steady state, the setup time of the device is shortened due to oversampling. When the setup time is shortened excessively, it may cause the components to receive erroneous signals.
An embodiment discloses a debounce circuit comprising a sampling circuit to sample an input signal four times at two adjacent rising edges and two adjacent falling edges of a first clock signal to determine a voltage level of the first output signal, a voltage level of the second output signal, a voltage level of the third output signal and a voltage level of the fourth output signal, and a logic gate for performing an AND operation or an OR operation on the first output signal, the second output signal, the third output signal, and the fourth output signal to output a debounced signal. The first clock signal has at least one of the two adjacent rising edges between the two adjacent falling edges and at least one of the two adjacent falling edges between the two adjacent rising edges.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
In an embodiment, the sampling circuit 50 includes a rising edge trigger module 101 and a falling edge trigger module 102. The rising edge trigger module 101 is used to sample the input signal Sw to determine the voltage level of the first output signal S1 and sample the first output signal S1 to determine the voltage level of the third output signal S3 when the first clock signal CK1 is at the rising edge. The falling edge trigger module 102 is used to sample the input signal Sw to determine the voltage level of the second output signal S2 and sample the second output signal S2 to determine the voltage level of the fourth output signal S4 when the first clock signal CK1 is at the falling edge.
In detail, since the debounced signal Db1 is used for an active high circuit in this embodiment, the logic gate 150 adopted here is an OR gate. When either one of the first output signal S1, the second output signal S2, the third output signal S3, and the fourth output signal S4 has a digital logic value of 1, the logic gate 150 would output the debounce signal Db1 with the digital logic value of 1. In contrast, only when the first output signal S1, the second output signal S2, the third output signal S3, and the fourth output signal S4 all have digital logic values of 0, the logic gate 150 would output the debounced signal Db1 with the digital logic value of 0. Therefore, even during the time t1 to t11, the input signal Sw is disturbed by a noise 30 causing the first output signal S1 to be low between times t5 and t7 and the second output signal S2 to be low between times t6 and t8. It also causes the third output signal S3 to be low between times t7 and t9, and the fourth output signal S4 to be low between times t8 and t10. Since the digital logic values of the first output signal S1, the second output signal S2, the third output signal S3, and the fourth output signal S4 are not all Os from time ta to t11, the digital logic value of the debounced signal Db1 can be maintained at 1 between times ta and t11. Therefore, the digital logic value of the debounced signal Db1 does not bounce due to the noise 30.
The principle of the debounce circuit 100 in this embodiment can be explained as follows. The rising edge trigger module 101 can output the first output signal S1 and the third output signal S3 generated by sampling the input signal Swat two adjacent rising edges of the first clock signal CK1. The falling edge trigger module 102 can output the second output signal S2 and the fourth output signal S4 by sampling the input signal Sw at two adjacent falling edges of the first clock signal CK1. Overall, the rising edge trigger module 101 and the falling edge trigger module 102 sample the input signal Sw four times at four adjacent signal edges of the first clock signal CK1 (two rising edges and two falling edges). In addition, in the embodiment, because the debounced signal Db1 is for an active high circuit, the logic gate 150 can be an OR gate to perform OR operation on the output signals S1, S2, S3, and S4 to output the debounced signal Db1. Since the time span of the input signal Sw bouncing due to the noise 30 is not long (less than two periods T of the first clock signal CK1), the debounced signal Db1 generated by the debounce circuit 100 through the sampling and the OR operation is not affected by the noise 30.
Please refer to both
Then, when the first clock signal CK1 is pulled to high at time t3, the rising edge trigger module 101 samples the input signal Sw to maintain the voltage level of the first output signal S1 at high. Meanwhile, the rising edge trigger module 101 samples the first output signal S1 at time t3 to output the third output signal S3, and the voltage level of the third output signal S3 is pulled to high. Then, when the first clock signal CK1 is pulled to low at time t4, the falling edge trigger module 102 samples the input signal Sw to maintain the voltage level of the second output signal S2 at high. Meanwhile, the falling edge trigger module 102 samples the second output signal S2 at time t4 to output the fourth output signal S4, and the voltage level of the fourth output signal S4 is pulled to high.
Between times t4 and t6, the waveform of the input signal Sw is disturbed by the noise 30. When the first clock signal CK1 is pulled to high at time t5, the voltage level of the first output signal S1 sampled from the input signal Sw is pulled to low. Since the response time of the rising edge trigger module 101 is not zero, there is a latency between the falling edge of the first output signal S1 and the rising edge of the first clock signal CK1. Due to the latency, the voltage level of the first output signal S1 at time t5 remains high. When the rising edge trigger module 101 samples the first output signal S1 at time t5 to output the third output signal S3, the voltage level of the third output signal S3 remains high. Because of the waveform of the input signal Sw being affected by the noise 30, when the first clock signal CK1 is pulled to low at time t6, the voltage level of the second output signal S2 sampled from the input signal Sw is pulled to low. Since the response time of the falling edge trigger module 102 is not zero, there is a latency between the falling edge of the second output signal S2 and the falling edge of the first clock signal CK1. Due to the latency, the voltage level of the second output signal S2 at time t6 remains high. When the falling edge trigger module 102 samples the second output signal S2 at time t6 to output the fourth output signal S4, the voltage level of the fourth output signal S4 remains high.
After time t6 the noise 30 is removed, so the waveform of the input signal Sw returns to normal. Therefore, when the first clock signal CK1 is pulled to high at time t7, the rising edge trigger module 101 samples the input signal Sw and the voltage level of the first output signal S1 is pulled to high. Since the response time of the rising edge trigger module 101 is not zero, there is latency between the rising edge of the first output signal S1 and the rising edge of the first clock signal CK1. Due to the latency, the voltage level of the first output signal S1 at time t7 remains low. When the rising edge trigger module 101 samples the first output signal S1 at time t7 to output the third output signal S3, the voltage level of the third output signal S3 is pulled to low. Then, when the first clock signal CK1 is pulled to low at time t8, the falling edge trigger module 102 samples the input signal Sw and pull the voltage level of the second output signal S2 to high. Since the response time of the falling edge trigger module 102 is not zero, there is a latency between the rising edge of the second output signal S2 and the falling edge of the first clock signal CK1. Due to the latency, the voltage level of the second output signal S2 at time t8 remains low. After the falling edge trigger module 102 samples the second output signal S2 at time t8 to output the fourth output signal S4, the voltage level of the fourth output signal S4 is pulled to low.
When the first clock signal CK1 is pulled to high at time t9, the rising edge trigger module 101 samples the input signal Sw and maintains the voltage level of the first output signal S1 at high. Meanwhile, the rising edge triggers module 101 samples the first output signal S1 at time t9 to output the third output signal S3, and the voltage level of the third output signal S3 is pulled to high. Then, when the first clock signal CK1 is pulled to low at time t10, the falling edge trigger module 102 samples the input signal Sw and maintains the voltage level of the second output signal S2 at high. Meanwhile, the trigger module 102 samples the second output signal S2 at time t10 to output the fourth output signal S4, and the voltage level of the fourth output signal S4 is pulled to high.
This paragraph explains the advantage of the debounce circuit 100 comparing with the prior art. Under the same condition with the same noise 30 in
In the embodiment of the present invention, the rising edge trigger module 101 comprises a first D flip-flop 110 and a third D flip-flop 130, and the falling edge trigger module 102 comprises a second D flip-flop 120 and a fourth D flip-flops 140. The first D flip-flop 110 comprises a data input terminal D receiving the input signal Sw and a clock input terminal CK receiving the first clock signal CK1. It further comprises a first data output terminal Q outputting the first output signal S1. When the first clock signal CK1 is switched from 0 to 1, the logic value of the first output signal S1 outputted by the first data output terminal Q is equal to the logic value of the input signal Sw. Overall, the first D flip-flop 110 samples the input signal Sw and outputs the sampled values when the first clock signal CK1 is at the rising edge.
The second D flip-flop 120 comprises a data input terminal D receiving the input signal Sw and a clock input terminal CK receiving the second clock signal CK2. It further comprises a first data output terminal Q outputting the second output signal S2. The second clock signal CK2 has the same frequency as the first clock signal CK1 but is inverted from the first clock signal CK1. The second clock signal CK2 can be generated by inputting the first clock signal CK1 through a first inverter 122. When the second clock signal CK2 is switched from 0 to 1, the logic value of the second output signal S2 outputted by the first data output terminal Q is equal to the logic value of the input signal Sw. Overall, the second D flip-flop 120 samples the input signal Sw and outputs the sampled values when the first clock signal CK1 is at the falling edge.
The third D flip-flop 130 comprises a data input terminal D receiving the first output signal S1 and a clock input terminal CK receiving the first clock signal CK1. It further comprises a first data output terminal Q outputting the third output signal S3. When the first clock signal CK1 is switched from 0 to 1, the logic value of the third output signal S3 outputted by the first data output terminal Q is equal to the logic value of the first output signal S1. Overall, the third D flip-flop 130 samples the first output signal S1 and outputs the sampled values when the first clock signal CK1 is at the rising edge.
The fourth D flip-flop 140 comprises a data input terminal D receiving the second output signal S2 and a clock input terminal CK receiving the second clock signal CK2. It further comprises a first data output terminal Q outputting the fourth output signal S4. When the second clock signal CK2 is switched from 0 to 1, the logic value of the fourth output signal S4 outputted by the first data output terminal Q is equal to the logic value of the second output signal S2. Overall, the fourth D flip-flop 140 samples the second output signal S2 and outputs the sampled values when the first clock signal CK1 is at the falling edge.
In addition, in this embodiment, a setup terminal S, a reset terminal R, and the second data output terminal
At time T0, the input signal Sw is about to be switched from low to high. However, due to the interference 330 between times T1 and T2, the signal Dw without debouncing process would have a low pulse 31. In contrast, even with interference 330, the signal Dp and the debounced signal Db1 would not have the pulse 31. However, since the debounce circuit of the prior art must continuously sample the input signal Sw to get consecutive 1s, the signal Dp is pulled to a high level at time T5. Therefore, the setup time of the device using the debounce circuit of the prior art is excessively shortened due to oversampling. The period of the first clock signal CK1 is T, and the time span between times T1 and T5 is approximately four periods 4T in the first clock signal CK1. In contrast, the debounce circuit 100 of the present invention adopts the first D flip-flop 110 and the third D flip-flop 130 to sample when the first clock signal CK1 is at the rising edges, and adopts the second D flip-flop 120 and the fourth D flip-flop 140 to sample when the first clock signal CK1 is at the falling edges. Thus, the sample rate is greater than which of the prior art, and the frequency of the first clock signal CK1 does not need to be excessively high. Assuming that the frequency of the input signal Sw is fa, and the frequency of the first clock signal CK1 and the second clock signal CK2 is fb, then the relation of the frequencies is 2fa≤fb≤5fa. In other words, a frequency fb of the first clock signal CK1 and the second clock signal CK2 may be greater than or equal to twice the frequency of the input signal Sw and may be less than or equal to five times the frequency of the input signal Sw. In addition, the debounced signal Db1 output by the debounce circuit 100 is pulled to high at time T1, and the debounced signal Db1 remains high at least until time T6. Therefore, with the debounce circuit 100 of the present invention, the setup time of the device is not excessively shortened, and in which ensures the accuracy of the signal received.
The debounce circuit 400 also includes a sampling circuit 50. The sampling circuit 50 includes a rising edge trigger module 101 and a falling edge trigger module 102. The rising edge trigger module 101 is configured to sample the input signal Sw to determine the voltage level of the first output signal S1 when the first clock signal CK1 is at the rising edge and to sample the first output signal S1 to determine the voltage level of the third output signal S3. The falling edge trigger module 102 is configured to sample the input signal Sw to determine the voltage level of the second output signal S2 when the first clock signal CK1 is at the falling edge and to sample the second output signal S2 to determine the voltage level of the fourth output signal S4. Similarly, the rising edge trigger module 101 can include a first D flip-flop 110 and a third D flip-flop 130, and the falling edge trigger module 102 can include a second D flip-flop 120 and a fourth D flip-flop 140.
In detail, since the debounced signal Db2 is for an active low circuit in this embodiment, the logic gate 450 adopted here is an AND gate. When either one of the first output signal S1, the second output signal S2, the third output signal S3, and the fourth output signal S4 has a digital logic value of 0, the logic gate 450 would output the debounce signal Db2 with the digital logic value of 0. In contrast, only when the first output signal S1, the second output signal S2, the third output signal S3, and the fourth output signal S4 all have digital logic values of 1, the logic gate 450 would output the debounced signal Db2 with the digital logic value of 1. Therefore, even during the time t1 to t11, the input signal Sw is disturbed by a noise 530 causing the first output signal S1 to be high between times t5 and t7 and the second output signal S2 to be high between times t6 and t8. It also causes the third output signal S3 to be high between times t7 and t9, and the fourth output signal S4 to be high between times t8 and t10. Since the digital logic values of the first output signal S1, the second output signal S2, the third output signal S3, and the fourth output signal S4 are not all is at the times ta to t11, the digital logic value of the debounced signal Db1 can be maintained at 0 between times ta and t11. Therefore, the digital logic value of the debounced signal Db1 does not bounce due to the noise 530.
This paragraph explains the advantage of the debounce circuit 400 comparing with the prior art. Under the same condition with the same noise 530 in
Please refer to both
Then, when the first clock signal CK1 is pulled to high at time t3, the rising edge trigger module 101 samples the input signal Sw to maintain the voltage level of the first output signal S1 at low. Meanwhile, the rising edge trigger module 101 samples the first output signal S1 at time t3 to output the third output signal S3, and the voltage level of the third output signal S3 is pulled to low. Then, when the first clock signal CK1 is pulled to low at time t4, the falling edge trigger module 102 samples the input signal Sw to maintain the voltage level of the second output signal S2 at low. Meanwhile, the falling edge trigger module 102 samples the second output signal S2 at time t4 to output the fourth output signal S4, and the voltage level of the fourth output signal S4 is pulled to low.
Between times t4 and t6, the waveform of the input signal Sw is disturbed by the noise 530. When the first clock signal CK1 is pulled to high at time t5, the voltage level of the first output signal S1 sampled from the input signal Sw is pulled to high. Since the response time of the rising edge trigger module 101 is not zero, there is latency between the rising edge of the first output signal S1 and the rising edge of the first clock signal CK1. Due to the latency, the voltage level of the first output signal S1 at time t5 remains low. After the rising edge trigger module 101 samples the first output signal Slat time t5 to output the third output signal S3, the voltage level of the third output signal S3 remains low. Similarly, the waveform of the input signal Sw is disturbed by the noise 530. When the first clock signal CK1 is pulled to low at time t6, the voltage level of the second output signal S2 sampled from the input signal Sw is pulled to high. Since the response time of the falling edge trigger module 102 is not zero, there is latency between the rising edge of the second output signal S2 and the falling edge of the first clock signal CK1. Due to the latency, the voltage level of the second output signal S2 at time t6 remains low. After the falling edge trigger module 102 samples the second output signal S2 at time t6 to output the fourth output signal S4, the voltage level of the fourth output signal S4 remains low.
After time t6 the noise 530 is removed, so the waveform of the input signal Sw returns to normal. Therefore, when the first clock signal CK1 is pulled to high time t7, the rising edge trigger module 101 samples the input signal Sw and the voltage level of the first output signal S1 is pulled to low. Since the response time of the rising edge trigger module 101 is not zero, there is latency between the falling edge of the first output signal S1 and the rising edge of the first clock signal CK1. Due to the latency, the voltage level of the first output signal S1 at time t7 remains high. After the rising edge trigger module 101 samples the first output signal S1 at time t5 to output the third output signal S3, the voltage level of the third output signal S3 is pulled to high. Then, when the first clock signal CK1 is pulled to low at time t8, the falling edge trigger module 102 samples the input signal Sw and the voltage level of the second output signal S2 is pulled to low. Since the response time of the falling edge trigger module 102 is not zero, there is latency between the rising edge of the second output signal S2 and the falling edge of the first clock signal CK1. Due to the latency, the voltage level of the second output signal S2 at time t8 remains high. After the falling edge trigger module 102 samples the second output signal S2 at time t8 to output the fourth output signal S4, the voltage level of the fourth output signal S4 is pulled to high.
When the first clock signal CK1 is pulled to high at time t9, the rising edge trigger module 101 samples the input signal Sw and maintains the voltage level of the first output signal S1 at low. Meanwhile, the rising edge triggers module 101 samples the first output signal S1 at time t9 to output the third output signal S3, and the voltage level of the third output signal S3 is pulled to low. Then, when the first clock signal CK1 is pulled to low at time t10, the falling edge trigger module 102 samples the input signal Sw and maintains the voltage level of the second output signal S2 at low. Meanwhile, the trigger module 102 samples the second output signal S2 at time t10 to output the fourth output signal S4, and the voltage level of the fourth output signal S4 is pulled to low.
In summary, the debounce circuit of the present invention includes a rising edge trigger module, a falling edge trigger module and a logic gate. The rising edge trigger module can output two signals generated by sampling the input signal at two adjacent rising edges of the clock signal, and the falling edge trigger module can output two signals generated by sampling the input signal at two adjacent falling edges of the clock signal. Overall, the rising edge trigger module and the falling edge trigger module sample the input signal four times at four adjacent signal edges of the clock signal. In addition, the present invention determines the logic gate to be an OR gate or an AND gate respectively based on whether the debounced signal is used for active high circuit or active low circuit and performs an OR operation or an AND operation on the outputted signals to generate the debounced signal. Since time span of the input signal bouncing due to a noise is not excessively long (less than the period of the two sampling clocks), the debounced signal generated by the debounce circuit of the present invention is not affected by the noise. Furthermore, since the debounce circuit of the present invention uses the rising edge trigger module to sample at the rising edge of the clock signal and uses the falling edge trigger module to sample at the falling edge of the clock signal, the sample rate is greater so the frequency of the clock signal for sampling does not need to be excessively high. In addition, the setup time of the debounce circuit of the present invention is not excessively shortened due to oversampling, in which ensures the accuracy of the signal received.
Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.
Number | Date | Country | Kind |
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201811388021.X | Nov 2018 | CN | national |