DEBUG DEVICE FOR DETECTING BUS TRANSMISSION AND METHOD THEREOF

Abstract

This invention relates to a debug device and method thereof and is applied to detect transmission on a bus in a computer system having a CPU, a north bridge chip and a south bridge chip. The debug device consists of a processing unit, a comparing unit and a recording unit. The processing unit receives a first address signal and a second address signal from the north bridge chip, and correspondingly transmits an index signal and a test data to the north bridge chip. The comparing unit compares the first and the second address signal to generate a comparing signal. And the recording unit records the first and the second address signal and the comparing signal. The north bridge chip connects to the south bridge chip via a bus, and the debug device also connects to the south bridge chip. Therefore the north bridge chip and the debug device transmit to both through the south chip.

Description

DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates a block diagram of a preferred embodiment;

FIG. 2 illustrates a block diagram of another preferred embodiment; and

FIG. 3 illustrates a flowchart of a preferred embodiment.

DETAILED DESCRIPTION

In the normal start up process, the CPU fetches a dialog session initiation protocol (SIP) from a boot initial address in the basic input output system (BIOS) to obtain necessary initial setup values. However, these initial setup values are written by the system designer. Therefore, the system designer has to test the optimal values and its stable range before the computer works. As stated in the prior art, manual testing is operated by repeatedly writing a test value each time to obtain the optimal result. This invention utilizes a debug device to automatically test series of values in a certain or random range by the computer system, and writes the best optimal setup values in the BIOS.

Please refer to FIG. 1, which depicts a block diagram of a preferred embodiment of this invention. The debug device 10a of this invention includes a processing unit 12a, a comparing unit 14a and a recording unit 16a. The debug device 10a is connected to a south bridge chip 20 via a peripheral component interface (PCI) bus. The south bridge chip 20 is connected to a north bridge chip 30 via a link. The north bridge chip 30 is connected to the CPU 40 via a front side bus (FSB). The south bridge 30 is further connected to a BIOS 50 via a low pin count (LPC) bus.

The operation of the debug device 10a stimulates the data transmission flow after the computer system has started up. Instead of fetching data from the BIOS 50 to the CPU 40, data is synthesized by the debug device 10a and transmitted to the north bridge chip 30 through the south bridge chip 20. When the computer system is powered on, the CPU 40 generates a booting signal and delivers it to the north bridge chip 30 via the FSB. The north bridge chip 30 blocks the booting signal to stop the booting signal being delivered to the BIOS 50. Later the north bridge chip 30 generates a first address signal and delivers the first address signal to the south bridge chip 20 via the link bus. In the prior art system, the south bridge chip 20 should deliver the first address signal to the BIOS 50 for accessing corresponding initial data. Instead, the debug device 10a of this invention intercepts the first address signal that should be delivered to the BIOS 50 via the PCI bus. As a result, the BIOS 50 will not perform any function. The debug device 10a then provides the first address signal to the recording unit 12a and the comparing unit 14a for further operations.

After receiving the first address signal, the processing unit 12a generates a corresponding index signal and delivers it to the north bridge chip 30 through the south bridge chip 20. The north bridge chip 30 as well generates a second address signal corresponding to the index signal and delivers it to the debug device 10a through the south bridge chip 20. The debug device 10a will deliver a test data to the north bridge chip 30 after receiving the second address signal. The test data can be generated in random or specific way. The comparing unit 14a generates a comparing signal according to the first address signal and the second address signal. Then the recording unit 16a records the first address signal, the second address signal and the comparing signal.

The debug device 10a also issues a retry signal to the CPU 40 after receiving the second address signal. The CPU 40 then issues a booting signal to the north bridge chip 30 again, making the north bridge chip 30 generates another first address signal. The procedure repeats above mentioned processes as a complete cycle. The north bridge chip 30 will issue a retry signal to the CPU 40 as a response to show that the booting signal is invalid. The CPU 40 then issues another booting signal, and the north bridge chip 30 again responses another retry signal. In this fashion, the north bridge chip 30 successfully blocks the access of the CPU 40 to the BIOS 50 and delivers the address signals to the debug device 10a for detection.

The debug device 10a may deliver different address signals to the north bridge chip 30, for example a serious of continuous address signals. Also, the debug device 10a can scan addresses in the whole region or a specific one to detect at which address transmission error may occur, such as transmission interrupt. Furthermore, the debug device 10a may compare and record each signal, even output these signals to display on the screen during detection. Therefore, the system designer may observe variations of each signal to gain more understanding about the bus transmission between the north bridge chip 30 and the south bridge chip 20. The recorded values in the recording unit 16a may inform system designer at which address the error occurs, and be a reference for future design.

Except getting error information from different address signals, it can also be performed by generating test data in specific order, such as sequentially changing value of certain bits. Variations of data bits can test the sensitivity which may also influence the stability of bus transmission. The system designer may modify errors on bit change to improve the performance of the link bus.

FIG. 2 depicts a block diagram of another embodiment of the debug device. As shown in FIG. 2, the debug device 10b includes a processing unit 12b, a comparing unit 14a and a recording unit 16b. The computer system in FIG. 2, same as that in FIG. 1, includes a CPU 40, a north bridge chip 30 and a south bridge chip 20. The CPU 40 and the north bridge chip 30 are connected to each other via a FSB; the north bridge chip 30 and the south bridge chip 20 are connected via a link bus. But differs to FIG. 1, the debug device 10b is connected to the south bridge chip 20 via a LPC bus as well as the BIOS 50. Therefore, the debug device 10b may intercept signals from the south bridge chip 20, preventing the BIOS 50 from receiving or feeding back signals to the north bridge chip 30. The operation of this embodiment is the same as that of FIG. 1. The north bridge chip 30 blocks a booting signal from the CPU 40 and delivers a first address signal to the debug device 10b. Then the debug device 10b returns an index signal to the north bridge chip 30. The north bridge chip 30 again transmits a second address signal to the debug device 10b in reply to the index signal. The debug device 10b then transmits a test data to the north bridge chip 30 and issues a retry signal to the CPU 40. Except that the debug device 10b is connected to the south bridge chip 20 via the LPC bus, other details are same as described in the previous embodiment and will not be repeated here. Please refer to the above description for better understanding.

A flowchart of a preferred embodiment is illustrated in FIG. 3. Please refer with FIG. 1. First in step S1, issue a booting signal from the CPU 40 to the north bridge chip 30. In step S2, block the booting signal and deliver a first signal from the north bridge chip 30 to the debug device 10a. In step S3, deliver a second signal from the debug device 10a to the north bridge chip 30 according to the first signal. In step S4, deliver a third signal from the north bridge chip 30 to the debug device according to the second signal. In step S5, generate a comparing signal according to the first signal and the third signal, and return a test data from the debug device 10a to the north bridge chip 30. In the final step S6, record the first signal, the third signal and the comparing signal, and issue a retry signal to the CPU 40. In step S2 to step S6, the north bridge chip 30 and the debug device 10a transfer signals and data to each other through the south bridge chip 20. The test result of this embodiment may be applied to improve the stability of bus transmission between the north bridge chip 30 and the south bridge chip 20 of the computer system, and also be applied as initial setup reference.

Concluded from above, this invention provides a debug device and a method therefore by connecting a debug device to the PCI bus or a LPC bus, even dispose the debug device in the BIOS, to block the CPU accessing data from the BIOS. The present invention is also applied to transfer address signals and test data between the north bridge chip and the debug device for detecting bus transmission between the north bridge chip and the south bridge chip. This invention has the advantage of saving labor effort and time spent by automatic scan. Efficiency and accuracy can be improved greatly, and the purpose of obtaining the optimal setup of the computer system may be easily achieved.

Please note that the embodiments disclosed herein are not referred to limit the scope of this invention. Other embodiments with equivalent variations or modification on shape, construction or features are taken as part of the present invention. The scope of the present invention is determined by the following claims.

Claims

1. A debug device, coupled to a computer system comprising a CPU, a north bridge chip, a south bridge chip, the debug device comprises: a processing unit, for receiving a first address signal and a second address signal from said north bridge chip and delivering an index signal and a test data to said north bridge chip;a comparing unit, for comparing said first address signal and said second address signal to generate a comparing signal; anda recording unit, for recording said first address signal, said second address signal and said comparing signal.

2. The debug device according to claim 1, wherein said first address signal and said second address signal are delivered to said processing unit through said south bridge chip; said index signal and said test data are delivered to said north bridge chip through said south bridge chip.

3. The debug device according to claim 2, wherein said debug device is connected to said south bridge chip via a PCI bus or a LPC bus.

4. The debug device according to claim 1, wherein said processing unit generates said index signal according to said first address signal and said test data according to said second address signal.

5. The debug device according to claim 1, wherein said north bridge confirms said test data is received.

6. The debug device according to claim 6, wherein said test data is generated in random or a specific way.

7. A detection method, for detecting between a computer system and a debug device, wherein said computer system comprises a CPU, a north bridge chip and a south bridge chip, comprising: delivering an address signal from said north bridge chip to said debug device;delivering a test data from said debug device to said north bridge chip; andconfirming said test data is received by said north bridge chip.

8. The detection method according to claim 8, wherein said north bridge chip and said debug device deliver said address signal and said test data through said south bridge chip.

9. The detection method according to claim 9, wherein said debug device is connected to said south bridge chip via a PCI bus or a LPC bus.

10. The detection method according to claim 8, said step of delivering said address signal from said north bridge chip to said debug device comprising: receiving a booting signal from said CPU to said north bridge chip.

11. The detection method according to claim 8, said step of confirming said test data is received by said north bridge chip comprising: issuing a retry signal from said debug device to said CPU, and said CPU issuing said booting signal to said north bridge chip.

12. The detection method according to claim 8, said step of delivering said test data from said debug device to said north bridge chip comprising: generating said data in random or a specific way.

13. A detection method, for detecting between a computer system and a debug device, said computer system comprises a CPU, a north bridge chip and a south bridge chip, comprising: delivering a first address signal from said north bridge chip to said debug device;delivering an index signal from said debug device to said north bridge chip;delivering a second address signal from said north bridge chip o said debug device;delivering a test data from said debug device to said north bridge chip;generating a comparing signal according to said first address signal and said second address signal by said debug device; andissuing a retry signal from said debug device to said CPU.

14. The detection method according to claim 15, wherein said first address signal, said second address signal, said index signal and said test data are transmitted between said north bridge chip and said debug device through said south bridge chip.

15. The detection method according to claim 16, wherein said debug device is connected to said south bridge chip via a PCI bus or a LPC bus.

16. The detection method according to claim 15, said step of delivering said first address signal from said north bridge chip to said debug device comprising: issuing a booting signal from said CPU to said north bridge chip.

17. The detection method according to claim 19, wherein said retry signal enforces said CPU issuing said booting signal.

18. The detection method according to claim 15, said step of generating a comparing signal according to said first address signal and said second address signal by said debug device comprising: recording said first address signal, said second address signal and said comparing signal.

19. The detection method according to claim 15, wherein said first address signal, said second address signal and said comparing signal may be generated in monotonic series.

20. The detection method according to claim 15, said step of delivering said test data from said debug device to said north bridge chip comprising: confirming said data is received by said north bridge chip.

21. The detection method according to claim 15, wherein said test data is generated in random or a specific way.