Claims
- 1. Apparatus for generating clock control signals in a microprogrammed digital processing system having a plurality of circuitized chips, each of the chips having local switching points therein, said apparatus comprising:
- (a) first circuit means, located on each chip requiring same, for generating, when started, a fixed number of clock timing signals;
- (b) master clock circuit means, operatively coupled to each of said first circuit means, for generating clock signals and for synchronously driving said first circuit means with respect to each other;
- (c) second circuit means, operatively coupled to said first circuit means, for receiving and decoding operation codes of the micro instructions and for deriving OP-CODE control signals therefrom for use, in conjunction with said clock signals, in developing clock control signals for application to the switching points of each of the individual chips; and
- (d) third circuit means responsive to said OP-CODES and operatively coupled to each of said first circuit means for generating a reset signal therefor to reset each of said first circuit means to their initial timing interval whenever the need arises at any point within a timing cycle to reduce the maximum number of clock timing signals provided per cycle by said first circuit means.
- 2. The apparatus according to claim 1 wherein said third circuit means includes logic circuit means responsive to said OP-CODE control signals for causing generation of said reset signal whenever a micro instruction requires less than the maximum number of clock timing signals available per cycle from said first circuit means.
- 3. The apparatus according to claim 2 wherein said second circuit means includes centralized decoding circuit means for receiving and decoding the operation codes and for generating OP-CODE control signals therefrom for application to the switchng points of each of the individual chips.
- 4. The apparatus according to claim 3 which additionally comprises signal routing means, for operatively coupling by circuit lines of equal length said master clock circuit means and each of said first circuit means.
- 5. The apparatus according to claim 2 wherein said second circuit means includes decentralized decoding circuit means, located on each chip, for receiving and decoding the operation codes and for generating OP-CODE control signals therefrom for application to the switching points of each of the individual chips.
- 6. The apparatus according to claim 5 which additionally comprises signal routing means, for operatively coupling by circuit lines of equal length said master clock circuit means and each of said first circuit means.
Priority Claims (1)
Number |
Date |
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Kind |
2853523 |
Dec 1978 |
DEX |
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Parent Case Info
This is a continuation of application Ser. No. 98,573 filed Nov. 29, 1979, now abandoned.
US Referenced Citations (6)
Continuations (1)
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Number |
Date |
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Parent |
98573 |
Nov 1979 |
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