Patent Grant
8019453
1. Field of the Invention
The present invention relates to a decimator and a decimating method for digital signal processing (DSP), and more particularly to a decimator and a decimating method for multi-channel audio processing.
2. Description of the Related Art
a) is a spectrum distribution diagram of a television multi-track stereo (MTS) audio specified by the US broadcast television systems committee (BTSC). The television MTS audio 10 is a composite signal, which includes a single-track (L+R) signal 101, a pilot signal 102, a stereo difference (L−R) signal 103, a second audio program (SAP) signal 104 and a professional channel signal 105.
The single-track (L+R) signal 101 is a base band signal, with a frequency of about 15 KHz. The frequency Fh of the pilot signal 102 is 15.734 KHz, which equals a horizontal scanning frequency of the BTSC video. The stereo difference (L−R) signal 103 is an amplitude modulation signal of the double sideband suppressed carrier (DSB_SC), with a central frequency of 2*Fh. The central frequency of the second audio program (SAP) signal 104 is 5*Fh, with the frequency spectrum ranging from +10 KHz to −10 KHz. The central frequency of the professional channel signal 105 is 6.5*Fh, with the frequency spectrum ranging from +3 KHz to −3 KHz.
b) is a schematic block diagram of the circuit of the BTSC television multi-track stereo audio 10 for decimation. A stereo difference signal 103a is obtained after the television multi-track stereo (MTS) audio 10 is mixed and decimated for 2Fh through a frequency mixer 120. Since the second audio program (SAP) signal 104 employs frequency modulation (FM), the pilot signal 102 may not be sent together when the transmitting side transmits the second audio program (SAP) signal 104. Accordingly, the receiving side cannot perform coherent demodulation. Therefore, after the television MTS audio 10 is mixed and decimated for 5Fh through the frequency mixer 120, a second audio program in-phase (SAP_I) signal 104a and a second audio program quadrature phase (SAP_Q) signal 104b are respectively obtained and sent to a frequency discriminator 140 for FM demodulation.
The mixed and decimated stereo difference signal 103a, the second audio program in-phase (SAP_I) signal 104a and the second audio program quadrature phase (SAP_Q) signal 104b are mainly base band signals, but still having certain high-frequency signals derived from the mixing and decimating process.
The sampling frequencies of the single-track signal 101, the stereo difference signal 103a, the second audio program in-phase (SAP_I) signal 104a and the second audio program quadrature phase (SAP_Q) signal 104b are decimated through four decimators 135, 132, 133 and 134 (referring to
During the digital signal processing of the decimators 131, 132, 133 and 134, in order to reduce the sampling frequency and avoid the aliasing of the frequency spectrum, a finite impulse response (FIR) filter is employed to act as a low-pass filter for the frequency domain and reduce the sampling frequency for the time domain. Additionally, the high-frequency signals derived from the mixing and decimating process can be filtered through the low-pass filtering process of the FIR filter.
c) is a schematic block diagram of the circuit of a second order FIR filter 160, which can be implemented to the previous stage of the decimators 131, 132, 133 and 134. The input signal 161 is converted into a first delay input signal 162 after being delayed by a time delayer 165. The first delay input signal 162 is converted into a second delay input signal 163 after being delayed by a time delayer 166. The signals 161, 162 and 163 are respectively multiplied with the corresponding impulse response coefficients 161h, 162h and 163h by multipliers 161m, 162m and 163m, the products are added together by an adder 167, and thereby the summation is an output signal 168.
The actual FIR filter generally requires an extremely large order. If the conventional register is used to act as a time delayer, the manufacturing cost of the hardware circuits including the four decimators (shown in
d) is a spectrum distribution diagram of a television multi-track stereo audio 11 regulated by the Electronic Industries Association of Japan (EIA-J). The audio 11 includes a single-track (L+R) signal 111, a stereo difference (L−R) signal 113 or a second audio program (SAP) signal 114, and a pilot identification signal 115. The transmitting side of the television stereo audio system for the EIA-J does not simultaneously transmit both the stereo difference (L−R) signal 113 and the second audio program (SAP) signal 114. The receiving side obtains signal data according to the amplitude modulation performance of the pilot identification signal 115, and the transmitted signal is the stereo difference (L−R) signal 113 or the second audio program (SAP) signal 114.
e) is a schematic block diagram of the circuit of the audio 11 for decimation. After the audio 11 received by the receiving side is decimated for 2Fh by a frequency mixer 121, either the single-track (L+R) signal and the stereo difference (L−R) signal 113 or the single-track (L+R) signal and the second audio program quadrature phase (SAP) signal 114 are obtained.
After the single-track (L+R) signal 111 is decimated by a decimator 151, a single-track (L+R) signal 111b is obtained. The stereo difference (L−R) signal 113 includes a stereo difference in-phase (L−R_I) signal 113a and a stereo difference quadrature phase (L−R_Q) signal 113b. After the signals 113a and 113b are decimated by the decimators 153 and 154 respectively, a stereo difference in-phase (L−R_I) signal 113c and a stereo difference quadrature phase (L−R_Q) signal 113d are obtained. Alternatively, the second audio program (SAP) signal 114 includes a second audio program in-phase (SAP_I) signal 114a and a second audio program quadrature phase (SAP_Q) signal 114b. After the signals 114a and 114b are decimated by the decimators 153 and 154, a second audio program in-phase (SAP_I) signal 114c and a second audio program quadrature phase (SAP_Q) signal 114d are obtained. The FM demodulation of the stereo difference in-phase (L−R_I) signal 113c and the second audio program in-phase (SAP_I) signal 114c share the same path, and the FM demodulation of the stereo difference quadrature phase (L−R_Q) signal 113d and the second audio program quadrature phase (SAP_Q) signal 114d also share the same path.
Compared with the single-track (L+R) signal 111b, the stereo difference in-phase (L−R_I) signal 113c and the stereo difference quadrature phase (L−R_Q) signal 113d need to be demodulated through a frequency discriminator 141, and thus a period of latency is necessary for such demodulation. Therefore, the single-track (L+R) signal 111 shall be transmitted later than the stereo difference (L−R) signal 113 by 20 microseconds at the transmitting side in compliance with the regulation of EIA-J so as to separate a left single-track signal from a right single-track signal. However, the processing time required is sometimes more than 20 microseconds for demodulating the stereo difference in-phase (L−R_I) signal 113c and the stereo difference quadrature phase (L−R_Q) signal 113d through the frequency discriminator 141, and consequently the latency for separating the left single-track signal from the single-track signal is not consistent.
An objective of the present invention is to provide a decimator and a decimating method to perform the digital signal processing of multi-channel audio, which is capable of reducing the manufacturing costs of hardware circuits as well as their power consumption. Additionally, the present invention may also be applied to other multi-channel digital signals, and is not limited to audio signals.
To achieve the above objective, the present invention provides a decimator for multi-channel audio with random access memory (RAM) as a basic configuration. The decimator for multi-channel audio comprises a memory, a controller and a processing unit. The processing unit is coupled to the memory, and used to perform digital signal processing to decimate the input multi-channel digital signal. The memory is used to store two kinds of data from different inputting paths; one is an input multi-channel digital signal from the decimator, and the other is the multi-channel operational data from the processing unit, i.e., the multi-channel audio after decimation. The controller is coupled to the memory, and used to control the writing and reading of data into and from the memory such that the memory finishes the digital signal processing for decimation together with the processing unit.
The controller regulates the control timing according to the following steps. First, the input multi-channel audio data is written into the memory. The processing unit retrieves the multi-channel audio from the memory to perform digital signal processing for decimation, and then the multi-channel operational data after decimation is similarly written into the memory for storage. Finally, the decimated multi-channel operational data stored in the memory is read and outputted to a subsequent level circuit.
In the present invention, a single decimator with a memory as a basic configuration is used to replace the four decimators in the conventional circuit. Compared with the conventional decimator circuit, the decimator circuit of the present invention reduces the required chip area by about 35% when being verified by the actual process.
In addition, the time delayer of the decimator can be implemented by a memory cell of the memory without the problem of high-frequency transition of the logic level of the register as with the conventional architecture, and thereby the power consumption is significantly reduced.
The decimator of the present invention outputs at least one FM modulation audio component to a frequency discriminator for FM demodulation. The frequency discriminator comprises an FIR filter and an FM demodulator. The FM demodulation audio component is first low-pass filtered by the FIR filter, and then is FM demodulated by the FM demodulator. The time delayer of the FIR filter is also implemented by a memory cell of the memory.
If the single-track signal and the stereo difference signal of the television multi-track stereo audio system are received at different times with a predetermined timing difference, the stereo difference signal can be further FM demodulated. The decimating method of the present invention further comprises a steps of: performing a time delay of at least one sampling unit for the single-track signal, wherein the time delay equals the sum of the time required for FM demodulating the stereo difference signal and the time difference.
The invention will be described according to the appended drawings in which:
a) is a spectrum distribution diagram of a BTSC television multi-track stereo audio;
b) is a schematic block diagram of the BTSC television multi-track stereo audio for decimation;
c) is a schematic circuit diagram of a second order FIR filter;
d) is a spectrum distribution diagram of an EIA-J television multi-track stereo audio;
e) is a schematic block diagram of the EIA-J television multi-track stereo audio for decimation;
Unlike the conventional art, the four input signals in the present invention are digital signals processed for decimation by a single decimator 20, instead of being processed by four decimators, as shown in
The decimator 20 comprises a RAM 210, a RAM controller 220, a processing unit 230, a multiplex 240 and a demultiplex 250.
The RAM 210 is a single port memory having an input port 210D and an output port 210Q, and is used to store two kinds of data from different inputting paths. One of the inputting data types is the input data of the decimator 20 such as a single-track signal 201, a stereo difference signal 203, a second audio program quadrature phase (SAP_I) signal 204a or a second audio program quadrature phase (SAP_Q) signal 204b, and the other is processed data retrieved from the processing unit 230.
The RAM controller 220 is used to control the writing and reading of the data into or from the RAM 210 such that the RAM 210 finishes the digital signal processing for decimation together with the processing unit 230. The RAM controller 220 utilizes a read/write control signal 221 and an address bus signal 223 to determine into which a certain address of the RAM 210 the data entering the input port 210D is written, or to read the data from a certain address of the RAM 210 and then output the data via the output port 210Q.
In this embodiment, the RAM controller 220 regulates the control timing and repeatedly performs the time division on audios from four different paths, i.e., the single-track signal 201, the stereo difference signal 203, the second audio program in-phase (SAP_I) signal 204a and the second audio program quadrature phase (SAP_Q) signal 204b, inputted from the previous stage circuit according to the following steps of (a)-(c). Then, the audio after being decimated is outputted to the next stage circuit through time division, until all the input audios have been processed.
(a) First, the RAM controller 220 outputs a multiplex control signal 224 to control the multiplex 240, and outputs the read/write control signal 221 and the address bus signal 223 to the RAM 210, such that the audio input by the previous stage circuit may be written into the RAM 210.
(b) Next, the RAM controller 220 outputs the read/write control signal 221 and the address bus signal 223 to the RAM 210, and reads the individual audio stored in the RAM 210 for the processing unit 230 to perform the low pass filtering on the frequency domain and to perform the digital signal process for decimation on the time domain, thereby generating corresponding operational data, i.e., the audio signal data after being decimated, as mentioned above. The operational data are then written into the RAM 210 again.
(c) The RAM controller 220 reads the audio stored in the RAM 210 after being decimated, and outputs a demultiplex control signal 225 to control the demultiplex 250, such that the demultiplex 250 outputs the operational data such as the single-track signal 201b, the stereo difference signal 203b, the second audio program in-phase (SAP_I) signal 204c and the second audio program quadrature phase (SAP_Q) signal 204d to the next stage circuit through time division.
In view of the above, supposing the original sampling frequency of the four audios is 384 KHz, if the decimator 20 with 8 multiples is employed to reduce the sampling frequency, the sampling frequency of the four audios may be reduced to 48 KHz.
The digital signal process for the low-pass filtering performed by the processing unit 230 may be achieved by an FIR filter, and meanwhile the high-frequency signals derived from the decimating process may be filtered by the low-pass filtering process of the FIR filter. The time delayer of the FIR filter can be implemented as a memory cell of the RAM 210.
As for the decimator of the present invention with a memory as the basic structure, a single decimator may be used to replace the conventional four decimators. Upon being verified by the TSMC process of 0.18 μm, when the decimator circuit of the present invention is compared with the conventional decimator circuit, the decimator circuit of the present invention may reduce the areas by about 35%.
In addition, the time delayer of the decimator in the present invention may be implemented as a memory cell of the memory, and thus the problem of high-frequency transition of the logic level of the register does not occur when the FIR filter is operated, thereby effectively reducing power consumption.
Supposing the time required for demodulating the stereo difference in-phase (L−R_I) signal 403c and the stereo difference quadrature phase (L−R_Q) signal 403d in this embodiment by the frequency discriminator 350 is 38.2 microseconds, the single-track monophonic (L+R) signal at the transmitting end should be transmitted later than the stereo difference (L−R) signal for about 20 microseconds according to the EIA-J regulation as mentioned above, and there is a time difference with a predetermined value of 20 microseconds between the single-track signal (L+R) and the stereo difference (L−R) signal when they are received at the receiving end. Therefore, an additional latency of 18.2 microseconds must be added between the input single-track signal 401 and the output single-track signal 401b of the decimator 20, so as to accurately separate a left single-track signal from a right single-track signal.
Supposing the sampling frequency of the single-track signal 401 is 384 KHz, the single-track signal 401 may be delayed for 7 sampling units during the decimating process, and thus the resulting latency is 7/384000 seconds, i.e., 18.2 microseconds.
The above-described embodiments of the present invention are intended to be illustrative only. Numerous alternative embodiments may be devised by persons skilled in the art without departing from the scope of the following claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 95107735 A | Mar 2006 | TW | national |
| 95132842 A | Sep 2006 | TW | national |
| Number | Name | Date | Kind |
|---|---|---|---|
| 5138452 | Soloff | Aug 1992 | A |
| 6061655 | Xue et al. | May 2000 | A |
| Number | Date | Country |
|---|---|---|
| 2416692 | Jan 2001 | CN |
| Number | Date | Country | |
|---|---|---|---|
| 20070211903 A1 | Sep 2007 | US |
