Decision timing synchronous circuit and receiver circuit

Abstract

A circuit includes: a portion for performing a logical operation based on a binary modulated signal and a cyclic signal; serial-to-parallel converter for sampling a operation output for parallel output; correlation filter having multiple digital filters for allowing the parallel signal values to pass therethrough; maximum difference detector for detecting a maximum difference in a period during which a difference between the maximum and minimum output signal values from digital filters is greater than a threshold; timing detector for detecting the inversion timing of each output signal value; and decision timing exterminating portion for determining decision timing based on the maximum difference and the detected inversion timing.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram illustrating the internal configuration of a receiver circuit according to a first embodiment of the present invention;

FIG. 2 is a view illustrating the relation between an output signal from a signal detector and an output signal from a preamble signal generator according to the first embodiment;

FIGS. 3A and 3B are views schematically illustrating signal sequences corresponding to sampling timing for detecting decision timing according to the first embodiment;

FIG. 4 is a view illustrating the relation between an output signal from the signal detector and an output signal from the preamble signal generator according to the first embodiment;

FIG. 5 is explanatory view illustrating an output from an S/P converter according to the first embodiment;

FIG. 6 is an explanatory view illustrating a process for detecting a “0” crossing point according to the first embodiment;

FIG. 7 is an explanatory view illustrating how a position is extended according to the first embodiment;

FIG. 8 is a block diagram illustrating the internal configuration of a receiver circuit according to a second embodiment;

FIGS. 9A and 9B are explanatory views for illustrating an interpolation process according to the second embodiment;

FIG. 10 is a block diagram illustrating the internal configuration of a receiver circuit according to a third embodiment;

FIG. 11 is an explanatory view illustrating coarse quantization and fine quantization processes according to the third embodiment;

FIG. 12 is a block diagram illustrating the internal configuration of a receiver circuit according to a fourth embodiment;

FIG. 13 is an explanatory view illustrating a frame structure according to the fourth embodiment; and

FIG. 14 is an explanatory view illustrating a process for detecting a “0” crossing point according to a fifth embodiment.

Claims

1. A decision timing synchronous circuit comprising: logical operation means for performing a logical operation based on a binary signal of a received modulated signal and a cyclic signal repeated regularly in a predetermined cycle;serial-to-parallel conversion means for receiving an operational output from the logical operation means and for sampling the operational output with predetermined sampling timing within one inversion cycle of the cyclic signal and then delivering the sampled value as a parallel signal value;correlation filter means having a plurality of digital filters for allowing each parallel signal value output from the serial-to-parallel conversion means to pass separately therethrough;maximum difference detection means for detecting a maximum difference in a period of timing during which a difference between a maximum value and a minimum value of each of the output signal values is equal to or greater than a threshold value, within one inversion cycle of the cyclic signal as a fundamental cycle based on each output signal value having passed through each of the digital filters of the correlation filter means;inversion timing detection means for determining a polarity of each of the output signal values having passed through each of the digital filters of the correlation filter means to detect polarity inversion timing; anddecision timing determination means for determining the timing detected by the inversion timing detection means as decision timing, when the maximum difference is detected by the maximum difference detection means.

2. The decision timing synchronous circuit according to claim 1, wherein the maximum difference detection means has a cycle extension portion for holding each of the output signal values from each of the digital filters and for extending the fundamental cycle to detect the maximum difference.

3. The decision timing synchronous circuit according to claim 1, wherein the inversion timing detection means has an interpolation portion for interpolating an intermediate value between each of the output signals based on each of the output signal values from each of the digital filters, and detects polarity inversion timing based on a polarity of a value including an interpolated value.

4. The decision timing synchronous circuit according to claim 1, comprising synchronization accuracy control means for adjusting a number of the parallel signal values while holding parallel signal intervals at equal intervals, based on each of the parallel signal values within one inversion cycle output from the serial-to-parallel conversion means, and for providing the adjusted number of the parallel signal values to the correlation filter means.

5. The decision timing synchronous circuit according to claim 4, wherein the synchronization accuracy control means decimates the parallel signal values at equal intervals so that the parallel signal interval is extended.

6. The decision timing synchronous circuit according to claim 5, wherein the synchronization accuracy control means adds each of the parallel signal values accepted, in a particular partial period within one inversion cycle, to the parallel signal interval adjusted to have an extended signal interval, so that the parallel signal interval is reduced.

7. The decision timing synchronous circuit according to claim 1, comprising word detection means for acquiring a demodulated binary signal of the received modulated signal having been demodulated, using decision timing determined by the decision timing determination means, and for detecting a word by comparison with a predefined word pattern, thereby determining a decision timing based on the word detection.

8. The decision timing synchronous circuit according to claim 1, wherein the inversion timing detection means determines, as inversion timing, a position indicating an intermediate value between a maximum value and a minimum value of each of the output signal values output from each of the digital filters.

9. The decision timing synchronous circuit according to claim 1, wherein the inversion timing detection means determines, as inversion timing, a timing approximated before and after a timing at which a polarity of each of the output signal values output from each of the digital filters is inverted.

10. The decision timing synchronous circuit according to claim 1, wherein the inversion timing detection means detects inversion timing by comparison between magnitudes of each of the output signal values output from the digital filters.

11. A receiver circuit comprising: binarization means for binarizing a received modulated signal supplied;a decision timing synchronous circuit for determining decision timing based on the binary signal of the received modulated signal binarized by the binarization means; anddemodulation means for demodulating the binary signal of the received modulated signal from the binarization means using the decision timing determined by the decision timing synchronous circuit,wherein the decision timing synchronous circuit corresponds to the decision timing synchronous circuit according to claim 1.

12. The decision timing synchronous circuit according to claim 4, wherein the synchronization accuracy control means decimates the parallel signal values at equal intervals to perform a coarse adjustment of synchronization accuracy, and determines a partial period within one inversion cycle based on the coarse adjustment result to perform a fine adjustment of synchronization accuracy in the partial period.

13. The decision timing synchronous circuit according to claim 12, wherein the synchronization accuracy control means receives a switching instruction to perform an adjustment switching between the coarse adjustment and fine adjustment of synchronization accuracy based on the switching instruction.