Patent Application
20090019068
The present invention relates generally to video display, more specifically the present invention relates to method and apparatus for reduced memory decoding of video signals.
In digital program signal decoding such as the MPEG decoding, in particular, HD (High Definition) type decoding, the demand for memory bandwidth is very high as compared with the lower resolution types. For example, MPEG-II at the 1080i (Main Profile at high Level), the motion compensation operations need at least 400 megabytes per second (Mbytes/s) for the worst case scenario (i.e. the requirement for a safe design).
However, in some applications, the final requisite presentation image resolution is not as high as the incoming bit stream. For example, the presentation resolution can be 720×480 even though the input bitstream has higher resolution than 720×480 thereby taking up more bandwidth. Furthermore, in the mobile applications, the presentation resolution can be even lower, say, 360×240. In the meantime, the power consumption requirement is much tighter in mobile applications. Therefore, any intermediately processing that can be eliminated helps.
Traditional decoding method and apparatus decodes the bitstream with full resolution. The decoding process then scales the image into final presentation solutions. As can be seen, the required memory bandwidth is high as well as demanding in that for HD decoding if conducted with full resolutions.
It is therefore desirable to devise a decoding apparatus and method with much less memory access requirement for such applications than the full resolution decoding.
In an audio/video (A/V) system, the display image size is reduced to save memory size and bandwidth.
In an audio/video (A/V) system, the display image size is reduced on the block level to save memory size and bandwidth.
In an audio/video (A/V) system, the display image size is reduced on the block level to save memory size and bandwidth.
In an audio/video (A/V) system, the display image size is reduced on the block level to save memory size and bandwidth (e.g. memory access), while still maintaining a predetermined final display resolution and quality.
In mobile communication systems, the display image size is reduced to save memory size and bandwidth.
In mobile communication systems, the display image size is reduced on the block level to save memory size and bandwidth.
In mobile communication systems, the display image size is reduced on the block level to save memory size and bandwidth.
In mobile communication systems, the display image size is reduced on the block level to save memory size and bandwidth (e.g. memory access), while still maintaining a predetermined final display resolution and quality.
A decoder decoding at a block level provided. The decoder comprises: a down-scalar receiving a multiplicity of blocks of data and down-scaling the blocks of data at the block level and storing the down-scaled data in a memory; and an output device for outputting the down-scaled blocks of data at the block level.
A receiver having a decoder decoding at a block level provided. The decoder comprises: a down-scalar receiving a multiplicity of blocks of data and down-scaling the blocks of data at the block level and storing the down-scaled data in a memory; and an output device for outputting the down-scaled blocks of data at the block level.
The purpose of this invention is to optimize the memory access and therefore memory bandwidth requirements, while maintaining an acceptable the final display resolution and quality. In the meantime the system costs and power consumption will be substantially reduced.
The accompanying figures, where like reference numerals refer to identical or functionally similar elements throughout the separate views and which together with the detailed description below are incorporated in and form part of the specification, serve to further illustrate various embodiments and to explain various principles and advantages all in accordance with the present invention.
Skilled artisans will appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help to improve understanding of embodiments of the present invention.
Before describing in detail embodiments that are in accordance with the present invention, it should be observed that the embodiments reside primarily in combinations of method steps and apparatus components related to reduce display image size on the block level to save memory size and bandwidth. Accordingly, the apparatus components and method steps have been represented where appropriate by conventional symbols in the drawings, showing only those specific details that are pertinent to understanding the embodiments of the present invention so as not to obscure the disclosure with details that will be readily apparent to those of ordinary skill in the art having the benefit of the description herein.
In this document, relational terms such as first and second, top and bottom, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. The terms “comprises,” “comprising,” or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. An element proceeded by “comprises . . . a” does not, without more constraints, preclude the existence of additional identical elements in the process, method, article, or apparatus that comprises the element.
It will be appreciated that embodiments of the invention described herein may be comprised of one or more conventional processors and unique stored program instructions that control the one or more processors to implement, in conjunction with certain non-processor circuits, some, most, or all of the functions of reduce display image size on the block level to save memory size and bandwidth described herein. The non-processor circuits may include, but are not limited to, a radio receiver, a radio transmitter, signal drivers, clock circuits, power source circuits, and user input devices. As such, these functions may be interpreted as steps of a method to perform reduce display image size on the block level to save memory size and bandwidth. Alternatively, some or all functions could be implemented by a state machine that has no stored program instructions, or in one or more application specific integrated circuits (ASICs), in which each function or some combinations of certain of the functions are implemented as custom logic. Of course, a combination of the two approaches could be used. Thus, methods and means for these functions have been described herein. Further, it is expected that one of ordinary skill, notwithstanding possibly significant effort and many design choices motivated by, for example, available time, current technology, and economic considerations, when guided by the concepts and principles disclosed herein will be readily capable of generating such software instructions and programs and ICs with minimal experimentation.
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MPEG or MPEG-like video systems use the MB (Macro-Block) data structure. Since MPEG or MPEG-like video compression algorithms make use or take advantage of MB (Macro-Block) data structure, the down-scaling and up-scaling operations are difficult to be performed over the whole scanning line either in horizontal direction, or between the MBs in the vertical direction. Furthermore, the smooth scaling must be perform during decoding period of the session but not in the final display stage as usually referred as de-blocking filter. A typical de-blocking filter, such as defined in the H.264 algorithm, will increase the memory bandwidth and therefore are not suitable for this application. Therefore, after the original, non-connected MB is selected, a novel method or device is required such that both memory bandwidth is reduced and block effect reduced to an acceptable level.
the new method called “Over lapped Recursive 2-D Scaling” 40 is devised to overcome the scaling difficulties without increasing the memory bandwidth. In method 40, if the I (Intra) picture is the current picture, the data is sent back to SDRAM for further processing like MC 18 for the other pictures and final display. An OLRS (Over Lapped Recursive Scaling) method 40 is used to scale the data into smaller MB before the data being sent to SDRAM Interface 22. If P or B pictures are being decoded, the reference picture data like I or P picture data, in smaller MB format, are fetched from SDRAM 24. They are scaled up to the original resolutions using OLRS methods 40. The MC (Motion Compensation) 18 operation is performed together with the result of IDCT 16 in the original resolutions. The resultant data is scaled down using OLRS 40, similar to the I picture data, and sent back to SDRAM 24 for display 26.
The detailed descriptions of Over Lapped Recursive 2-D Scaling (OLRS) Operations 40 are shown as follows:
Referring to
The present invention contemplates applications in a TDS-OFDM system or receiver. U.S. patent application entitled “Receiver Structure for an LDPC-Based TDS-OFDM Communication System” Ser. No. 11/740,712, filed Apr. 26, 2007, Attorney Docket No. LSC-P016 is hereby incorporated herein by reference.
In the foregoing specification, specific embodiments of the present invention have been described. However, one of ordinary skill in the art appreciates that various modifications and changes can be made without departing from the scope of the present invention as set forth in the claims below. Accordingly, the specification and figures are to be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of present invention. The benefits, advantages, solutions to problems, and any element(s) that may cause any benefit, advantage, or solution to occur or become more pronounced are not to be construed as a critical, required, or essential features or elements of any or all the claims. The invention is defined solely by the appended claims including any amendments made during the pendency of this application and all equivalents of those claims as issued.
Terms and phrases used in this document, and variations thereof, unless otherwise expressly stated, should be construed as open ended as opposed to limiting. As examples of the foregoing: the term “including” should be read as mean “including, without limitation” or the like; the term “example” is used to provide exemplary instances of the item in discussion, not an exhaustive or limiting list thereof; and adjectives such as “conventional,” “traditional,” “normal,” “standard,” and terms of similar meaning should not be construed as limiting the item described to a given time period or to an item available as of a given time, but instead should be read to encompass conventional, traditional, normal, or standard technologies that may be available now or at any time in the future. Likewise, a group of items linked with the conjunction “and” should not be read as requiring that each and every one of those items be present in the grouping, but rather should be read as “and/or” unless expressly stated otherwise. Similarly, a group of items linked with the conjunction “or” should not be read as requiring mutual exclusivity among that group, but rather should also be read as “and/or” unless expressly stated otherwise.
The following applications of common assignee are related to the present application, and are herein incorporated by reference in their entireties: “METHOD AND APPARATUS FOR REDUCED MEMORY DECODING OF VIDEO SIGNALS” Ser. No. ______, filed [date herein], Attorney Docket No. LSFFT-078.
