Patent Application
20160087653
Various embodiments of the present inventions provide apparatuses and methods for targeted symbol flipping recovery of miscorrected codewords in a decoder.
Various data transfer systems have been developed including storage systems, cellular telephone systems, and radio transmission systems. In such systems data is transferred from a sender to a receiver via some medium. For example, in a storage system, data is sent from a sender (i.e., a write function) to a receiver (i.e., a read function) via a storage medium. In some cases, the data processing function receives data sets and applies a data decode algorithm to the data sets to recover an originally written data set. When data fails to converge in a decoder, an error recovery operation can be initiated to change decoder input values before again applying the data decode algorithm. However, such an error recovery operation increases latency and can produce multiple copies of the same results.
An apparatus for decoding data is disclosed including a decoder circuit operable to apply a decoding algorithm to a decoder input to yield a codeword, a convergence detection circuit operable to determine whether parity checks are satisfied by the decoder input and to identify unsatisfied parity checks in the decoder circuit, and a symbol flipping controller operable to change values of at least one symbol in the decoder input based on information about the unsatisfied parity checks. The decoder circuit is restarted to process the decoder input with the changed values. The information about the unsatisfied parity checks is obtained at each of a number of local decoding iterations in the decoder circuit.
This summary provides only a general outline of some embodiments of the invention. Additional embodiments are disclosed in the following detailed description, the appended claims and the accompanying drawings.
A further understanding of the various embodiments of the present invention may be realized by reference to the figures which are described in remaining portions of the specification. In the figures, like reference numerals may be used throughout several drawings to refer to similar components.
A decoder with targeted symbol flipping recovery of miscorrected codewords is disclosed herein which uses supplementary unsatisfied parity check information to initiate early targeted symbol flipping operations and which uses hashing to prevent duplicate output codewords. The targeted symbol flipping recovery of miscorrected codewords can be applied in any suitable data decoder, such as, but not limited to, a low density parity check (LDPC) decoder. Decoder technology is applicable to transmission of information over virtually any channel or storage of information on virtually any media. Transmission applications include, but are not limited to, optical fiber, radio frequency channels, wired or wireless local area networks, digital subscriber line technologies, wireless cellular, Ethernet over any medium such as copper or optical fiber, cable channels such as cable television, and Earth-satellite communications. Storage applications include, but are not limited to, hard disk drives, compact disks, digital video disks, magnetic tapes and memory devices such as dynamic random-access memory, negated-AND flash, negated-OR flash, other non-volatile memories and solid state drives.
A decoder decodes blocks of data, such as a data sector read from a magnetic hard disk drive, generating codewords and yielding hard decisions for the codewords as a decoded output when parity checks are satisfied for the codewords. Targeted symbol flipping is initiated when normal decoding fails, for example when the data in the decoder fails to converge on values that satisfy all parity checks or other error correction code constraints. Targeted symbol flipping is also initiated when the data converges on values that satisfy all parity checks but which are not fully correct, a condition that can be detected using cyclic redundancy checks (CRCs) or other additional tests.
During targeted symbol flipping, the input values to the decoder for selected bits or symbols are changed and decoding is repeated in an attempt to cause the decoder to converge. The term “symbol flipping” is used herein to refer to changing the values of symbols during a decoding operation in an attempt to cause the codewords to converge on values which satisfy parity checks. The symbols may each include one or more bits. In a non-binary decoder, a symbol may be flipped by changing the hard decision and/or log-likelihood ratio (LLR) input value to a different element of the Galois Field associated with the decoder. For example, in a GF(4) decoder, the symbol can be flipped by adding 1, 2 or 3 to the hard decision. The symbol flipping can be performed in any manner suitable to the particular decoder and the format of its input. For example, the input to the decoder can consist of a hard decision identifying one of the Galois Field elements as the most likely real value along with a log likelihood ratio value for each of the other Galois Field elements, indicating the likelihood that the real value corresponds to each of the other Galois Field elements. In this case, the symbol can be flipped by selecting another of the Galois Field elements as the hard decision.
In some embodiments, the codeword generated by the decoder corresponds to an entire data sector of a storage device. In some embodiments, the codeword is subdivided into portions referred to as component codewords. For example, in some embodiments the codeword is divided into four component codewords which are independently decoded, with convergence being checked in the decoder for a component codeword at the end of a local decoding iteration and/or at intermediate stages during a local decoding iteration based on supplementary information about unsatisfied parity checks, also referred to herein as intermediate information about unsatisfied parity checks.
The supplementary information about unsatisfied parity checks can include a count and list of unsatisfied parity checks generated at the end of each local decoding iteration, and in some embodiments, generated during local decoding iterations as the list of unsatisfied parity checks is updated while the local decoding iteration is performed. Furthermore, after a local decoding iteration with a larger number of unsatisfied parity checks than can typically be resolved with targeted symbol flipping, rather than simply terminating the decoding operation or attempting a different recovery option, additional local decoding iterations can be performed to determine whether the number of unsatisfied parity checks continues to decline. Where the number of unsatisfied parity checks continues to decline with additional local decoding iterations, the decoding process is continued and when the number of unsatisfied parity checks falls below a threshold, the local decoding iterations are stopped and a targeted symbol flipping operation is initiated. Intermediate information about unsatisfied parity checks helps miscorrection recovery by providing information from each local iteration, allowing the decoder to arrive at a state in which targeted symbol flipping can be successful, rather than simply giving up when an iteration results in an overwhelmingly large number of unsatisfied checks.
Turning now to
Analog to digital converter circuit 110 converts processed analog signal 106 into a corresponding series of digital samples 112. Analog to digital converter circuit 110 may be any circuit known in the art that is capable of producing digital samples corresponding to an analog input signal. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of analog to digital converter circuits that may be used in relation to different embodiments of the present invention. Digital samples 112 are provided to an equalizer circuit 114. Equalizer circuit 114 applies an equalization algorithm to digital samples 112 to yield an equalized output 116. In some embodiments of the present inventions, equalizer circuit 114 is a digital finite impulse response (DFIR) filter circuit as are known in the art. Equalized output 116 is stored in a memory or Y buffer 118. In some cases, equalized output 116 is received directly from a storage device in, for example, a solid state storage system. In such cases, analog front end circuit 102, analog to digital converter circuit 110 and equalizer circuit 114 can be eliminated where the data is received as a digital data input.
Equalized data 106 is provided to a data detector circuit 120, which is operable to apply a data detection algorithm to a received codeword or data set, and in some cases data detector circuit 120 can process two or more codewords in parallel. In some embodiments of the present invention, data detector circuit 120 is a Viterbi algorithm data detector circuit as is known in the art. In other embodiments of the present inventions, data detector circuit 120 is a maximum a posteriori data detector circuit as is known in the art. Of note, the general phrases “Viterbi data detection algorithm” or “Viterbi algorithm data detector circuit” are used in their broadest sense to mean any Viterbi detection algorithm or Viterbi algorithm detector circuit or variations thereof including, but not limited to, bi-direction Viterbi detection algorithm or bi-direction Viterbi algorithm detector circuit. Also, the general phrases “maximum a posteriori data detection algorithm” or “maximum a posteriori data detector circuit” are used in their broadest sense to mean any maximum a posteriori detection algorithm or detector circuit or variations thereof including, but not limited to, simplified maximum a posteriori data detection algorithm and a max-log maximum a posteriori data detection algorithm, or corresponding detector circuits. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of data detector circuits that may be used in relation to different embodiments of the present inventions. Data detector circuit 120 is started based upon availability of a data set from Y buffer 118 or from a central memory circuit 130.
Upon completion, data detector circuit 120 provides detector output 122, or soft data. As used herein, the phrase “soft data” is used in its broadest sense to mean reliability data with each instance of the reliability data indicating a likelihood that a corresponding bit position or group of bit positions has been correctly detected. In some embodiments of the present inventions, the soft data or reliability data is log likelihood ratio data as is known in the art. Detected output 122 is provided to a local interleaver circuit 124. Local interleaver circuit 124 is operable to shuffle sub-portions (i.e., local chunks) of the data set included as detected output 122 and provides an interleaved codeword 126 that is stored to central memory circuit 130. Interleaver circuit 124 may be any circuit known in the art that is capable of shuffling data sets to yield a re-arranged data set. Interleaved codeword 126 is stored to central memory circuit 130. The interleaved codeword 126 is accessed from central memory circuit 130 as a stored codeword 132 and globally interleaved by a global interleaver/de-interleaver circuit 134. Global interleaver/De-interleaver circuit 134 may be any circuit known in the art that is capable of globally rearranging codewords. Global interleaver/De-interleaver circuit 134 provides a decoder input 136 to a low density parity check decoder 140 with targeted symbol flipping recovery of miscorrected codewords. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize other decode algorithms that may be used in relation to different embodiments of the present invention, in association with the targeted symbol flipping recovery of miscorrected codewords disclosed herein. The decoder 140 applies a data decode algorithm to decoder input 136 in a variable number of local iterations.
Where the decoder 140 fails to converge (i.e., fails to yield the originally written data set) and a number of local iterations through LDPC decoder 140 exceeds a threshold, the resulting decoded output can be provided as a decoded output 142 back to central memory circuit 130 where it is stored awaiting another global iteration through data detector circuit 120 and decoder 140. Multiple sectors may be processed simultaneously in the data processing system 100, with additional sectors being admitted to the data detector 120 as other sectors converge in the decoder 140 and are output and cleared from the Y buffer 118 and central memory circuit 130.
Prior to storage of decoded output 142 to central memory circuit 130, decoded output 142 is globally de-interleaved to yield a globally de-interleaved output 144 that is stored to central memory circuit 130. The global de-interleaving reverses the global interleaving earlier applied to stored codeword 132 to yield decoder input 136. Once data detector circuit 120 is available, a previously stored de-interleaved output 144 is accessed from central memory circuit 130 and locally de-interleaved by a de-interleaver circuit 146. De-interleaver circuit 146 re-arranges stored decoder output 150 to reverse the shuffling originally performed by interleaver circuit 124. A resulting de-interleaved output 152 is provided to data detector circuit 120 where it is used to guide subsequent detection of a corresponding data set received as equalized output 116.
Alternatively, where the decoded output converges (i.e., yields the originally written data set) in the decoder 140, the resulting decoded output is provided as an output codeword 160 to a hard decision deinterleaver 162, which rearranges the data to reverse both the global and local interleaving applied to the data to yield a de-interleaved output 164. De-interleaved output 164 is stored in a hard decision memory 166 and is then provided to a read interface 172, which can perform additional error checking such as cyclic redundancy checks (CRC) on the de-interleaved output 164. Data 174 can then be forwarded to a hard disk controller 176 or other destination, either automatically or as instructed by the decoder 140.
When the decoder input 136 fails to converge in the decoder 140, or converges on incorrect codewords, one or more symbols at a time can be flipped in the decoder 140, based on a list of check nodes in the decoder 140 which fail parity checks. Supplemental or intermediate information about the unsatisfied parity checks can be used to trigger targeted symbol flipping in the decoder 140, in some cases even if the number of unsatisfied parity checks is initially larger than can normally be resolved with targeted symbol flipping, and in some cases by monitoring information about unsatisfied parity checks that is updated as while decoding is ongoing, during a local decoding iteration.
Turning to
A convergence detector and hash calculation circuit 224 determines whether data has converged in the decoder 200 by determining whether the syndrome s=cHT is all zero. A low density parity check code is defined by a sparse parity check matrix H of size m×n, where m<n. A codeword c of length n satisfies all the m parity check equations defined by H, i.e., cHT=0, where 0 is a zero vector. The syndrome is a vector of length m, with each bit corresponding to a parity check in the parity check matrix or H matrix. A zero bit in a syndrome means the check is satisfied, while a non-zero bit in the syndrome is an unsatisfied check (USC). By definition, a codeword c, defined by the hard decisions 222 from the variable node processor 212, has syndrome s=0. A non-codeword has a non-zero syndrome. The syndrome is calculated in the convergence detector and hash calculation circuit 224 as the dot product of the codeword c and the parity check matrix H.
The convergence detector and hash calculation circuit 224 also calculates a hash value for the codeword c or for component codewords that combine to form codeword c. As codewords are generated in the decoder 200, they can be stored in codeword buffer 230, forming a pool or candidate codewords, some of which may be miscorrected codewords that satisfy the parity checks but which are not identical to the original data. The convergence detector and hash calculation circuit 224 includes a comparator that compares the newly calculated hash value for the current codeword or component codeword with previously calculated hash values 232 corresponding to codewords or component codewords stored in a codeword buffer 230, generated by previous decoding iterations for the same data sector. If the newly calculated hash value for the current codeword or component codeword is different from the previously calculated hash values 232, it is assumed that the current codeword or component codeword is unique and not identical to any stored in codeword buffer 230, and the codeword or component codeword and its hash value 226 are stored in codeword buffer 230. After storing a number of codewords in codeword buffer 230, one of them is selected as the output codeword and the corresponding hard decisions 234 are output. The selection of the output codeword can be performed in any suitable manner, for example using a cyclic redundancy check to identify the correct codeword. The selection of the output codeword can be triggered in one more manners, such as when the codeword buffer 230 is full, or after a particular number of local and/or global decoding iterations has been performed, or when a read interface has requested that another data sector be read and the data processing system is needed for other tasks, etc. The convergence detector and hash calculation circuit 224 can be implemented as independent circuits or as a combined circuit containing syndrome and hash calculation circuits.
A scheduler and targeted symbol flipping controller 240 controls both normal decoding and retry operations in the decoder 200. The scheduler and targeted symbol flipping controller 240 provides decoding instructions 244, 246 to the variable node processor and check node processor 216 about circulants to be processed, etc. During a symbol flipping operation, the scheduler and targeted symbol flipping controller 240 also includes symbols flipping information in instructions 244, and receives unsatisfied check information 236 and symbol values 242 enabling it to determine which symbols to flip and which values can be tried.
Turning to
In some embodiments, the contents of the codeword memory 308 are updated each time a component codeword is available, or a portion of a codeword, and in these cases, the hash calculation, storage and comparison can be done on a component codeword basis.
Completion of a symbol flipping operation can be based on any suitable conditions, such as, but not limited to, the codeword memory 308 becoming full, or a limit on processing time for a sector being reached, or a read request for other data requiring the decoder to move on, etc. Any suitable technique can be used to select one of the codewords 350 stored in codeword memory being selected as output 354 by a codeword selector 352. For example, in some embodiments the codeword selector 352 applies cyclic redundancy checks to candidate codewords in codeword memory 308 to select the correct codeword.
Depending on the complexity of the hash algorithm applied by hash calculator and comparison circuit 304, it is possible that some duplication of codewords may remain. However, the goal of avoiding duplicate codewords can be balanced against the need for efficient hash calculations and for compact and low power hardware. A simpler hash algorithm can be faster and require less power and complex circuitry, at the greater risk of duplicate codewords. A more complex hash algorithm can provide better protection against duplicate codewords, at the possible costs of higher memory requirements to store hash values, greater latency in calculating hash values and more complex hash calculation circuits.
Turning to
Targeted symbol flipping can be initiated at various times during decoding when the number of unsatisfied parity checks falls below a threshold, and not just at the end of the first local decoding iteration. Turning to
However, in some embodiments, when the number of unsatisfied parity checks 504 is greater than the threshold 506, for example at the end of the first local decoding iteration of a particular global decoding iteration, local decoding iterations can be continued while the number of unsatisfied parity checks 504 decreases, in the hope that it will fall below the threshold 506 and targeted symbol flipping can be initiated. For example, Table 1 below gives the number of unsatisfied parity checks for two component codewords as they are processed in parallel in a low density parity check decoder:
At the end of the first local decoding iteration, the number of unsatisfied parity checks for a first component codeword CCW0 is 146, and for a second component codeword CCW1 is 180. If at most 7 unsatisfied parity checks can be expected to be corrected by targeted symbol flipping in an acceptable manner, the threshold is set at 7 (for a less than or equal to comparison) or 8 (for a less than comparison). Notably, although the number of unsatisfied parity checks is unacceptably high for targeted symbol flipping initially, additional local decoding iterations can be performed until the number of unsatisfied parity checks falls. In this case, targeted symbol flipping can be initiated for the first component codeword CCW0 after local decoding iteration 3, when the number of unsatisfied parity checks has fallen to 7. In some embodiments which process multiple circulants in parallel, the number of unsatisfied parity checks is examined for circulant pairs that are being processed in parallel, and targeted symbol flipping is initiated at the first convergence check for the circulant pair that satisfies the threshold.
In some embodiments, the targeted symbol flipping is performed on the initial decoder input. In some other embodiments, the targeted symbol flipping is performed on the later results of one or more local decoding iterations, effectively rolling back the state of the data to a point where targeted symbol flipping can be productive.
Turning to
Although the targeted symbol flipping recovery of miscorrected codewords disclosed herein is not limited to any particular application, several examples of applications are presented in
In a typical read operation, read/write head assembly 720 is accurately positioned by motor controller 712 over a desired data track on disk platter 716. Motor controller 712 both positions read/write head assembly 720 in relation to disk platter 716 and drives spindle motor 714 by moving read/write head assembly 720 to the proper data track on disk platter 716 under the direction of hard disk controller 710. Spindle motor 714 spins disk platter 716 at a determined spin rate (RPMs). Once read/write head assembly 720 is positioned adjacent the proper data track, magnetic signals representing data on disk platter 716 are sensed by read/write head assembly 720 as disk platter 716 is rotated by spindle motor 714. The sensed magnetic signals are provided as a continuous, minute analog signal representative of the magnetic data on disk platter 716. This minute analog signal is transferred from read/write head assembly 720 to read channel circuit 702 via preamplifier 704. Preamplifier 704 is operable to amplify the minute analog signals accessed from disk platter 716. In turn, read channel circuit 702 decodes and digitizes the received analog signal to recreate the information originally written to disk platter 716. This data is provided as read data 722 to a receiving circuit. As part of decoding the received information, read channel circuit 702 applies targeted symbol flipping recovery of miscorrected codewords when decoding fails to converge normally. Such targeted symbol flipping recovery of miscorrected codewords can be implemented consistent with that disclosed above in relation to
It should be noted that storage system 700 may be integrated into a larger storage system such as, for example, a RAID (redundant array of inexpensive disks or redundant array of independent disks) based storage system. Such a RAID storage system increases stability and reliability through redundancy, combining multiple disks as a logical unit. Data may be spread across a number of disks included in the RAID storage system according to a variety of algorithms and accessed by an operating system as if it were a single disk. For example, data may be mirrored to multiple disks in the RAID storage system, or may be sliced and distributed across multiple disks in a number of techniques. If a small number of disks in the RAID storage system fail or become unavailable, error correction techniques may be used to recreate the missing data based on the remaining portions of the data from the other disks in the RAID storage system. The disks in the RAID storage system may be, but are not limited to, individual storage systems such storage system 700, and may be located in close proximity to each other or distributed more widely for increased security. In a write operation, write data is provided to a controller, which stores the write data across the disks, for example by mirroring or by striping the write data. In a read operation, the controller retrieves the data from the disks. The controller then yields the resulting read data as if the RAID storage system were a single disk.
Turning to
It should be noted that the various blocks discussed in the above application may be implemented in integrated circuits along with other functionality. Such integrated circuits may include all of the functions of a given block, system or circuit, or only a subset of the block, system or circuit. Further, elements of the blocks, systems or circuits may be implemented across multiple integrated circuits. Such integrated circuits may be any type of integrated circuit known in the art including, but are not limited to, a monolithic integrated circuit, a flip chip integrated circuit, a multichip module integrated circuit, and/or a mixed signal integrated circuit. It should also be noted that various functions of the blocks, systems or circuits discussed herein may be implemented in either software or firmware. In some such cases, the entire system, block or circuit may be implemented using its software or firmware equivalent. In other cases, the one part of a given system, block or circuit may be implemented in software or firmware, while other parts are implemented in hardware.
In conclusion, the present invention provides novel apparatuses and methods for low density parity check decoding with targeted symbol flipping recovery of miscorrected codewords. While detailed descriptions of one or more embodiments of the invention have been given above, various alternatives, modifications, and equivalents will be apparent to those skilled in the art without varying from the spirit of the invention. Therefore, the above description should not be taken as limiting the scope of the invention, which is defined by the appended claims.
