BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a block diagram of a decoding apparatus according to one embodiment of the present invention.
FIG. 2 is a block diagram of a post filter unit in FIG. 1.
FIG. 3 is a block diagram of a de-ringing filter in FIG. 2.
FIG. 4 is a block diagram of non-linear operation unit in FIG. 3.
FIG. 5 is a schematic diagram to explain processing of the de-ringing filter.
FIG. 6 is a block diagram of a first filter adaptive control unit in FIG. 2.
FIG. 7 is a graph of edge intensity versus second Q-value.
FIG. 8 is a flow chart of processing of a de-block filter in FIG. 2.
FIG. 9 is a schematic diagram to explain classification by the de-block filter.
FIG. 10 is a schematic diagram to explain relationship between a block boundary and pixels for de-block filter processing.
FIGS. 11A and 11B are schematic diagrams to explain relationship between a macro block boundary and blocks for MPEG-2.
FIGS. 12A and 12B are schematic diagrams to explain a quantization matrix for MPEG-2.