Decoding device and decoding method

Abstract

The decoding device decoding coded data coded by a low density parity check code by using a plurality of parity check matrixes, comprises a pattern storing unit storing information about the parity check matrix and the segmentation pattern of the parity check matrix, which is formed by segmenting the parity check matrix into a plurality of row groups and into a plurality of column groups, and by allocating the parity check matrix so that there is one edge allocation area in the respective column groups within the respective row groups, a likelihood information storing unit storing likelihood information of respective code bits of the coded data divided into each memory cell with respect to the respective column groups, and a plurality of edge-by-edge arithmetic unit each connected to the memory cell storing the likelihood information about the column group, and updating the likelihood information based on the likelihood information stored in the connected memory cell.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagram showing an example of a circuit configuration of a decoding device in a first embodiment;

FIG. 2 is a diagram showing a coding specification in the first embodiment;

FIG. 3 is a diagram illustrating a parity check matrix in the first embodiment;

FIG. 4 is a diagram showing the connecting relationship between the arithmetic units and the memories at a coding rate ⅕ in the first embodiment;

FIG. 5 is a diagram showing the connecting relationship between the arithmetic units and the memories at a coding rate ⅘ in the first embodiment;

FIG. 6 is a flowchart showing an operational example of the decoding device in the first embodiment;

FIG. 7 is a diagram showing the parity check matrix in a second embodiment;

FIG. 8 is a diagram showing the parity check matrix in a third embodiment;

FIG. 9 is a diagram showing the parity check matrix in a fourth embodiment;

FIG. 10 is a diagram showing an example of a circuit configuration of the decoding device in a fifth embodiment;

FIG. 11 is a diagram showing the parity check matrix;

FIG. 12 is a diagram showing a configuration of a conventional decoder;

FIG. 13 is a diagram showing a correspondence coding specification;

FIG. 14 is a diagram showing a configuration of the decoder corresponding to a plurality of coding rates when operating at the coding rate ⅕;

FIG. 15 is a diagram showing a configuration of the decoder corresponding to the plurality of coding rates when operating at the coding rate ⅘; and

FIG. 16 is a diagram showing a configuration of the decoder corresponding to the plurality of coding rates.

Claims

1. A decoding device decoding coded data coded by a low density parity check code in a way that uses a plurality of parity check matrixes corresponding to a plurality of coding rates and having a uniform row weight, comprising: a pattern storing unit storing information about a parity check matrix, in the plurality of parity check matrixes, corresponding to the coding rate of the coded data and the segmentation pattern of the parity check matrix, the segmentation pattern being formed by segmenting each of the plurality of parity check matrixes into a plurality of row groups and into a plurality of column groups of which the number is the same throughout the plurality of parity check matrixes, and by allocating each of the plurality of parity check matrixes so that there is one edge allocation area, being a unit area of a plurality of segmented unit areas and having edge, in each of the plurality of column groups within each of the plurality of row groups;a likelihood information storing unit dividing likelihood information of respective code bits of the coded data into each memory cell with respect to each of the plurality of column groups based on the stored segmentation pattern and storing the divided likelihood information; anda plurality of edge-by-edge arithmetic unit each connected, corresponding to any one of the edge allocation areas, to the memory cell storing the likelihood information about the column group to which the corresponding edge allocation area belongs, and updating the likelihood information of the code bit corresponding to an edge within the corresponding edge allocation area based on the likelihood information stored in the connected memory cell.

2. A decoding device according to claim 1, wherein said pattern storing unit storing a position of the edge allocation area and a position of the edge within the edge allocation area, as information about the parity check matrix, and each of said plurality of edge-by-edge arithmetic unit determines an address of the should-be-updated likelihood information within the connected memory cell based on the stored position of the edge with respect to the corresponding edge allocation area of processing target.

3. A decoding device according to claim 1, wherein each of the plurality of row groups is an aggregation of rows performed a decoding process at one processing cycle, and said plurality of edge-by-edge arithmetic unit are provided, of which the number corresponds to at least a numerical value obtained by multiplying the number of the rows performed the decoding process at one processing cycle by the row weight of the parity check matrix, and updates the likelihood information for one row group at one processing cycle.

4. A decoding device according to claim 1, wherein each of the plurality of parity check matrixes and the segmentation pattern have such allocation that each of the plurality of segmented unit areas is formed of at least one matrix, any one of the matrixes contained in the edge allocation area becomes an edge allocation matrix where the edge is allocated, and other matrixes become zero matrixes, said pattern storing unit storing, as the information about the parity check matrix, a position of the edge allocation area, a position of the edge allocation matrix in the edge allocation area and a position of the edge within the edge allocation matrix, andeach of said plurality of edge-by-edge arithmetic unit determines the address of the should-be-updated likelihood information within the connected memory cell based on the position of the edge allocation matrix related to the corresponding edge allocation area of processing target and the position of the edge within the edge allocation matrix.

5. A decoding device according to claim 4, wherein the matrix contained in each of the plurality of segmented unit area is a square matrix.

6. A decoding device according to claim 1, wherein each of the plurality of segmented unit area is one matrix, and the edge is allocated in the respective rows in the edge allocation area, said pattern storing unit storing, as information about the parity check matrix, a position of the edge allocation area, a shape of the matrix in the edge allocation area, and a position of the edge within the edge allocation area, andeach of said plurality of edge-by-edge arithmetic unit determines the address of the should-be-updated likelihood information within the connected memory cell based on the shape of the matrix in the edge allocation area related to the corresponding edge allocation area of processing target and the position of the edge in the edge allocation area.

7. A decoding device according to claim 1, wherein each of the plurality of parity check matrixes is a parity check matrix in which to rearrange the columns and/or the rows of the real parity check matrix corresponding to the coded data, and said likelihood information storing unit rearranges, based on rearrangement information from the real parity check matrix into the stored parity check matrix, the likelihood information of the respective code bits of the coded data in accordance with the stored parity check matrix, thereafter divides the likelihood information into each memory cell with respect to each of the plurality of column groups based on the stored segmentation pattern, and storing the divided likelihood information.

8. A decoding method of decoding coded data coded by a low density parity check code in a way that uses a plurality of parity check matrixes corresponding to a plurality of coding rates and having a uniform row weight, comprising: a pattern storing step of storing information about a parity check matrix, in the plurality of parity check matrixes, corresponding to the coding rate of the coded data and the segmentation pattern of the parity check matrix, the segmentation pattern being formed by segmenting each of the plurality of parity check matrixes into a plurality of row groups and into a plurality of column groups of which the number is the same throughout the plurality of parity check matrixes, and by allocating each of the plurality of parity check matrixes so that there is one edge allocation area, being a unit area of a plurality of segmented unit areas and having edge, in each of the plurality of column groups within each of the plurality of row groups;a likelihood information storing step of dividing likelihood information of respective code bits of the coded data into each memory cell with respect to each of the plurality of column groups based on the stored segmentation pattern and storing the divided likelihood information; anda edge-by-edge arithmetic step of accessing, corresponding to any one of the edge allocation areas, the memory cell storing the likelihood information about the column group to which the corresponding edge allocation area belongs, and updating the likelihood information of the code bit corresponding to an edge within the corresponding edge allocation area based on the likelihood information stored in the memory cell.