The present invention relates generally to decoding systems. More specifically, the present invention relates to an improved decoding scheme and implementation for correcting both erasures and errors of Reed-Solomon codes in a digital communication system.
It is known that Reed-Solomon codes can be used for correcting both erasures and errors such that signal to noise ratio are reduced. An article by T_K Truong, et al entitled “A NEW DECODING ALGORITHM FOR CORRECTING BOTH ERASURES AND ERROR OF REED-SOLOMON CODES” which is hereby incorporated herein by reference (IEEE Transaction on Communications. VOL. 51, No. 3, March 2003) discloses a decoding algorithm that computes the errata locator polynomial and the errata evaluator polynomial simultaeously without performing polynomial divisions.
To fit a specific code length into a communication systems such as advanced television systems committee (ATSC) system, improved devices are required.
An improved decoding scheme for correcting both erasures and errors of Reed-Solomon codes in a digital communication system having a Novel iterative method including the initial condition settings is provided.
An improved decoding scheme for correcting both erasures and errors of Reed-Solomon codes in a digital communication system having a scheme having shortened the code parameters 2m−1 to fit ATSC standard is provided.
An improved decoding scheme for correcting both erasures and errors of Reed-Solomon codes in a digital communication system having a Reducing logic or circuit complexity by 4xCLK is provided.
A method for correcting both erasures and errors of Reed-Solomon codes in a digital communication system is provided. The method comprises the steps of: calculating a syndrome; calculating a set of erasure locations; replacing errata evaluator polynomial by a function having a difference value; and replacing errata locator polynomial by a function having the difference value.
The accompanying figures, where like reference numerals refer to identical or functionally similar elements throughout the separate views and which together with the detailed description below are incorporated in and form part of the specification, serve to further illustrate various embodiments and to explain various principles and advantages all in accordance with the present invention.
Skilled artisans will appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help to improve understanding of embodiments of the present invention.
Before describing in detail embodiments that are in accordance with the present invention, it should be observed that the embodiments reside primarily in combinations of method steps and apparatus components related to a novel iterative method including the initial condition settings to accommodate a Shortening of the code parameters to fit ATSC standard, as well as having a Reduced logic or circuit complexity. Accordingly, the apparatus components and method steps have been represented where appropriate by conventional symbols in the drawings, showing only those specific details that are pertinent to understanding the embodiments of the present invention so as not to obscure the disclosure with details that will be readily apparent to those of ordinary skill in the art having the benefit of the description herein.
In this document, relational terms such as first and second, top and bottom, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. The terms “comprises,” “comprising,” or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. An element proceeded by “comprises . . . a” does not, without more constraints, preclude the existence of additional identical elements in the process, method, article, or apparatus that comprises the element.
It will be appreciated that embodiments of the invention described herein may be comprised of one or more conventional processors and unique stored program instructions that control the one or more processors to implement, in conjunction with certain non-processor circuits, some, most, or all of the functions of relating to novel iterative method including the initial condition settings to accommodate a Shortening of the code parameters to fit ATSC standard, as well as having a Reduced logic or circuit complexity. In the exemplified embodiments, it is noted that the processors include Finite State Machines, which are used in the preferred embodiment. The non-processor circuits may include, but are not limited to, a radio receiver, a radio transmitter, signal drivers, clock circuits, power source circuits, and user input devices. As such, these functions may be interpreted as steps of a method with novel iterative method including the initial condition settings to accommodate a Shortening of the code parameters to fit ATSC standard, as well as having a reduced logic or circuit complexity. Alternatively, some or all functions could be implemented by a state machine that has no stored program instructions, or in one or more application specific integrated circuits (ASICs), in which each function or some combinations of certain of the functions are implemented as custom logic. Of course, a combination of the two approaches could be used. Thus, methods and means for these functions have been described herein. Further, it is expected that one of ordinary skill, notwithstanding possibly significant effort and many design choices motivated by, for example, available time, current technology, and economic considerations, when guided by the concepts and principles disclosed herein will be readily capable of generating such software instructions and programs and ICs with minimal experimentation.
For Reed-Solomon cyclic code, a generator polynomial g(X) with symbols from GF(2m) has α, α2, . . . , α2t, αi is all its roots. Because a is an element of GF(2m), its minimal polynomial is simply φi(X)=X−αi, we have:
g(X)=g0+g1X+g2X2+ . . . , +g2t−1X2t−1+X2t Eq. 1
g(X) generates a 2m array cyclic code of length n=q−1 with exactly 2t parity check symbols. Further, the Reed-Solomon cyclic code satisfies the following conditions:
block length: n=2m−1,
number of parity check symbols: n−k=2t,
dimension: k=2m−1−2t,
minimum distance: dmin=2t+1.
In order to fit the Reed-Solomon cyclic code into our scheme, we have to shorten (255, 235) to (207, 187). we have:
255−48=207
235−48=187
n−k=20=2t, then,
t=10. Note that t denotes the maximum number of error that can be corrected in the system. As can be seen, the present scheme do not satisfy the 2m requirement in GF(2m), where m=8. Therefore, an adjustment is required. It is noted that (255, 235) can be generalized to other suitable numeral pairs in a Reed-Solomon cyclic code system.
Referring to
Referring to
Then the syndrome polynomial is:
S(x)=S0+S1X+S2X2+ . . . +S2t−1X2t−1 Eq. 3
Z0=1,
Zj is the jth erasure location for 1≦j≦s (where s is the erasure number) and Zj=0 for s+1≦j≦2t.
Third, a novel decoding scheme is provided herein including setting the following initial conditions (Step 46). For detailed description of the novel decoding scheme, refer to
Ω(a)(x)=0, Λ(a)(x)=0, Ω(b))(x)=S(x), Λ(b))(x)=1 (Step 70).
Ω(b)(x)←xΩ(b))(x), and
Λ(b))(x)←xΛ(b))(x) (Step 72).
δ=Ωd(b) γ=Ωd(a)
else, δ=1, γ=Zs+1−k(Step 74).
Ω(c)(x)=δΩ(a)(x)+γΩ(b)(x)
Λ(c)(x)=δΛ(a)(x)+γΛ(b)(x) (Step 76).
Then Ω(a)(x)=Ω(b)(x); Λ(a)(x)=Λ(b)(x); and 1=k−s−1;
Else if k=s, then Ω(a)(x)=Xd;
Else if s is non-zero and k<s, then
Ω(a)(x)=Ω(c)(x) note that only zero bits are copied to n−k; and
Λ(a)(x)=Λ(c)(x) only zero bits are copied to n−k−1 (Step 78).
4. Replace Ω1 by Ω1α48 . . . , Ω2t−1 by Ω2t−1α48(2t−1) in the errata evaluator polynomial; and similarly replace a difference value. Λ1 by Λ1α48, Λ2 by Λ2α48x2 . . . , Λ2t by Λ2tα48(2t) in the errata locator polynomial (Step 48). Forty-eight happens to be the difference value in the instant case. Other difference values different than the number 48 are also contemplated in the present invention.
We denote the above as Ω1←Ω1α48, Ω2←Ω2α48x2 . . . , Ω2t−1←Ω2t−1α48(2t−1) and
Λ1←Λ1α48, Λ2 Λ2α48x2 . . . , Λ2t←Λ2t48(2t). This adjustment is required because the present scheme do not satisfy the 2m requirement in GF(2m).
5. Find the roots of errata locator polynomial Λ(c)(x) by Chien's search method(Step 50). Then the errata locations are the inverse of the roots.
6. Find or calculate the errata magnitude by
For 1≦l≦s+1. Where each {circumflex over (Z)}l is the erasure location among a plurality of locations, Ŵl is the erasure amplitude, and Λ′{circumflex over (Z)}l−1 is the derivative of Λ (Step 52).
7. The corrected codeword is obtained by subtracting the errata vector from the received vector (Step 54).
Referring to
Referring to
In the foregoing specification, specific embodiments of the present invention have been described. However, one of ordinary skill in the art appreciates that various modifications and changes can be made without departing from the scope of the present invention as set forth in the claims below. Accordingly, the specification and figures are to be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of present invention. The benefits, advantages, solutions to problems, and any element(s) that may cause any benefit, advantage, or solution to occur or become more pronounced are not to be construed as a critical, required, or essential features or elements of any or all the claims. The invention is defined solely by the appended claims including any amendments made during the pendency of this application and all equivalents of those claims as issued.