The present disclosure generally relates to quantum computing, and more particularly, to decomposition of arbitrary two-qubit gates into other gates.
Quantum computing can address classically intractable computational problems. However, existing quantum computational devices are limited by various sources of error and imprecision. In particular, two-qubit gate operations constitute a major source of complex errors in existing quantum computational devices. Realization of an improved two-qubit gate may improve the performance of quantum computing algorithms and advance the goal of fault-tolerant quantum computation for complex quantum-computational tasks.
The disclosed systems and methods relate to implementation of two-qubit gates in a quantum calculation using an AshN dynamic decoupling drive gate (or SWAP gate) and single-qubit gates (if necessary).
The disclosed embodiments include a method for performing a quantum computation. The method can include generating a gate sequence implementing a quantum computational task. The gate sequence can be generated by a classical computing system. Generation of the gate sequence can include identifying, in the gate sequence, a two-qubit gate to be applied to two qubits of a quantum computing system. The two-qubit gate can be associated with Weyl coordinates x, y, and z. Generation of the gate sequence can include determining a dynamic decoupling drive gate locally equivalent to the two-qubit gate. Determination of the dynamic decoupling drive gate can include determining a gate time for the dynamic decoupling drive gate and determining a first amplitude of a first dynamic decoupling drive associated with a first one of the two qubits. The first amplitude of a first dynamic decoupling drive can be determined using the gate time; a sum of the y and z coordinates; and a difference of the y and z coordinates. Generation of the gate sequence can include including the dynamic decoupling drive gate in the gate sequence at least partially in place of the two-qubit gate. The method can include providing commands applying the gate sequence to the quantum computing system and obtaining an output from the quantum computing system.
The disclosed embodiments further include a system configured to perform the above method and computer-readable media containing instructions for configuring a system to perform the above method.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosed embodiments, as claimed.
The accompanying drawings, which comprise a part of this specification, illustrate several embodiments and, together with the description, serve to explain the principles and features of the disclosed embodiments. In the drawings:
Reference will now be made in detail to exemplary embodiments, discussed with regards to the accompanying drawings. In some instances, the same reference numbers will be used throughout the drawings and the following description to refer to the same or like parts. Unless otherwise defined, technical or scientific terms have the meaning commonly understood by one of ordinary skill in the art. The disclosed embodiments are described in sufficient detail to enable those skilled in the art to practice the disclosed embodiments. It is to be understood that other embodiments may be utilized and that changes may be made without departing from the scope of the disclosed embodiments. Thus, the materials, methods, and examples are illustrative only and are not intended to be necessarily limiting.
Quantum algorithms can be expressed in terms sequences of one or more quantum gates. An arbitrary quantum gate can be implemented using a sequence of other quantum gates. The particular quantum gates used to implement the arbitrary quantum gate can depend on the physical implementation of the quantum device (e.g., a particular physical implementation can be associated with one or more “native” quantum gates). The performance of the arbitrary quantum gate can depend on the performance of the native quantum gates used to implement the arbitrary quantum gate.
As described above, two-qubit gate operations constitute a major source of complex errors in existing quantum computational devices. The disclosed embodiments concern implementation of arbitrary two-quantum gates using a type of decoupling drive gate, the AshN gate, in combination with other single-qubit quantum gates.
As disclosed herein, general quantum circuits can be implemented using AshN gates (and any necessary single-qubit gates). In some embodiments, an arbitrary two-qubit gate (excepting a SWAP gates) can be implemented into an AshN gate. The parameters of the AshN gate can be determined on a classical computational device, and the compiled sequence can be readily run on an arbitrary quantum computational device supporting a native implementation of the AshN gate. In some embodiments, an AshN gate can be implemented using two transversally coupled qubits in resonance while each qubit is also under the influence of a microwave drive. As may be appreciated, other implementations are also possible. As an example, two transmon qubits can be capacitively coupled, each with its own microwave drive. In some embodiments, the microwave drives can be sinusoidal with fixed frequency and amplitude. As an additional example, an AshN gate can also be implemented using a flux drive configured to obtain a similar Hamiltonian.
A general two-qubit gate can be mathematically formulated as an element of the special unitary group SU(4). The KAK decomposition and Weyl chamber provide mathematical tools to characterize two-qubit gates up to single qubit gates.
single qubit rotations A0, A1, B0, B1 ∈ SU(2) and a global phase g ∈ {1, i} such that U=g·(A1⊗A2) exp {i{right arrow over (η)}·{right arrow over (Σ)}}(B1⊗B2), where {right arrow over (Σ)}= [σX⊗σX, σY⊗σY, σZ⊗σZ]. The tuple (g, {right arrow over (η)}, A0, A1, B0, B1) is called the KAK decomposition of the unitary U. The equivalence class of a unitary U under local unitaries, denoted as Ū, is characterized by the interaction coefficients η(U), which lives in a 3-dimensional tetrahedron called the Weyl chamber:
Two unitaries U, V ∈ SU(4) are locally equivalent, or U˜V, if η(U)=η(V). Let L(x, y, z)≡exp (i[x, y, z]·{right arrow over (Σ)}) be the canonical element of the equivalence class. Then U˜L (η(U)) for all U ∈ SU(4).
Consistent with disclosed embodiments, adjusting the parameters of a dynamic decoupling drive gate can result in different two-bit gates. Given two qubits, at resonance and with one dynamic decoupling drive on the second qubit, the Hamiltonian can be formulated as:
In this example, g is the transverse coupling strength between the qubits and Ω is the drive amplitude. The matrix exponential of the Hamiltonian can be taken as:
In this example, the parameters g, t, and Ω can be chosen to achieve the dynamic drive CZ gate (equivalent to the MS gate):
For example, selecting:
causes B (g, t, Ω)=C (g, t, Ω)=0. Thus:
which in turn implies
The appropriate coefficients can be obtained as follows:
and then
so to obtain the smallest positive solutions for the drive amplitude Ω and the time t, j=0, and
which is the DDCZ gate up to a global phase.
A more complicated Hamiltonian can be used, which includes a ZZ error. In some such embodiments, a dynamic decoupling drive can be applied to each qubit:
The matrix exponentiation of this Hamiltonian (exp [−it/2*H (Ω1, Ω2)]) can be obtained.
The (00,01) entry of this matrix exponential can be set to zero when Ω1 and Ω2 satisfy the relation:
Then setting t=π/2g the appropriate amplitudes can be obtained as:
The values of k and j can be selected (e.g., in this case as k=j=1):
These equations place boundaries on the values of g and h. When |g−h|, |g+h|≤4g, or h ∈ [−3g, 3g], there exists a real solution. For such values of g and h, the exponentiated Hamiltonian is the DDCZ gate up to a global phase.
In some embodiments, a DDCZ can incur the same kind of single qubit phase errors as an fSim gate. Such errors may be expressed in a rotating frame of reference as:
These errors can be dealt with by absorbing them into the adjoining single-qubit gates or by using customized compilation schemes for specific circuits like syndrome extraction.
Adding a phase shift to the single DD pulse in the simplified model for DDCZ implements the following Hamiltonian:
The corresponding unitary can be expressed as:
using the excitation number conserving property of iSWAP family gates:
and therefore:
Therefore, when t=π/2g and Ω=√{square root over (15g)}, the implemented unitary can be:
As a further step in this derivation, a phase shift can be added to each dynamic decoupling drive pulse in the case in which there are ZZ errors. The Hamiltonian then becomes:
When the phase shifts of the dynamic decoupling drive are equal, the effect can be the same as in the single dynamic decoupling drive pulse case.
For ϕ1≠ϕ2, setting t=π/2g and using the amplitude relationships given above, the unitary obtained is in general not locally equivalent to the DDCZ gate. Values of t, Ω1, and Ω2 for obtaining the DDCZ gate may be dependent on ϕ1, and ϕ2.
Depending on values of g and h, different locally inequivalent gates can be obtained.
Consistent with disclosed embodiments, the AshN gate can be defined as
As shown above, the iSWAP and DDCZ gates can be realized using certain gate drive (Ω) and time value (t) s:
By varying the gate drive (Ω) on the interval [0, √{square root over (15)}g], two-qubit gates in the Weyl chamber between the iSWAP and DDCZ gates can be realized.
In particular, as depicted in
Consistent with disclosed embodiments, suitable values of the parameters t and Ω can be calculated directly. The Makhlin invariants can be calculated as:
The matrix exponential for the gate AshN (t, Ω) can be plugged into the formula for the Makhlin invariants to obtain:
G1 is real for all g, t, Ω and therefore one of the Cartan interaction coefficients is zero. By projecting to the Weyl chamber defined by:
it can be seen that z=0 for all g, t, Ω.
The Makhlin invariants can be related to the Cartan interaction coefficients as follows:
By setting z=0, these relationships can be simplified to:
These equations can be mapped to the Makhlin invariants formula when:
As described above, x,
Therefore cos (2x), cos (2y)≥0. Because these functions are positive:
and therefore x=½gt and
These relationships can be used to generate the entire xy plane of the Weyl chamber. For example, take t ∈ [0, π/2g] to obtain all x ∈ [0, π/4]. When t=0 then taking Ω=0 obtains the point (0,0). For fixed t>0, take Ω=0 to obtain y=x. Then take
to obtain y=0. Since y is a continuous function of Ω, all values of y∈[0, x] can be obtained by varying Ω. Consistent with disclosed embodiments, the DDCZ gate can be obtained by setting t=π/2g (so that x=π/4). Then:
To obtain the B gate, the above relationships can be solved for x=π/4, y=π/8. In a first step, t can be selected to be:
while the relation:
where
This equation can be solved numerically to obtain ζ0≈5.00712. Thus to obtain the B gate, an AshN gate can be applied with t=π/2g and Ω=√{square root over (ζ0)}g.
As described herein, the Hamiltonian for the two drive dynamically driven two-qubit gate can be:
Taking advantage of mutually commutative terms, the Hamiltonian can be locally conjugated as X→Z, Y→X, Z→−Y to get
The modified Hamiltonian H′ has invariant subspaces {|00, |11
}, {|10
, |01
} and the corresponding unitary U(t, Ω1, Ω2):=exp{−itH′ (Ω1, Ω2)} has the same spaces and non-zero entries. In some embodiments, U(t, Ω1, Ω2)=e−igtV0+eigtV1, where V0 and V1 are two SU(2) rotations acting on subspaces spanned by {|00
, |11
} and {|10
, |01
}, respectively. As the two subspaces are also invariant under RZ(α)⊗RZ(β), it follows that:
Therefore, in terms of local equivalence, the gate can be determined by the relative phase differences between the two blocks gt, and
In the context of the canonical Weyl chamber elements:
The canonical elements also have invariant subspaces spanned by {|00, |11
} and {|10
, |01
} with the corresponding three characteristics being c, sin (a+b), and sin (a−b). The Weyl chamber can be defined as
where 1≥sin (a+b)≥sin (a−b)≥0. The first equality is satisfied only for the SWAP gate. Otherwise, there exists a U (t, Ω1, Ω2) that generates a local equivalent. Let t=(2kπ+c)/g for some k∈. Then given:
we have |f(θ)|≤1, but any number in the interval (−1,1) can be achieved using the appropriate selection of k. Therefore both sin (a+b) and sin (a−b), can be achieved using an appropriate selection of k, and θ1 and θ2 that result in desired selections of Ω1 and Ω2. However, the SWAP gate cannot be achieved using such a construction, as the SWAP gate requires
and f(θ)=1, which cannot be simultaneously achieved.
The classical component 310 can be configured to control the quantum device 320. The classical component can include a compilation module 311. Compilation module 311 can be configured to obtain a description of a quantum computation task (a unitary, a quantum circuit, etc.) and determine an implementation of the quantum computation task. The implementation can be a gate sequence. The gate sequence can include AshN gates (and SWAP gates, if necessary) and single-qubit gates.
In some embodiments, gate module 313 (which may be implemented as a submodule of compilation module 311) can be configured to determine parameters of an AshN gate locally equivalent to a given two-qubit gate. In some embodiments, gate module 313 can also determine single qubit gates such that composition of the single qubit gates and AshN gate equal the given two-qubit gate, up to a global phase. Gate decomposition module 313 can obtain a two-qubit gate from compilation module 311. In response, gate decomposition module 313 can determine and provide to compilation module 311 parameters of an AshN gate locally equivalent to the given two-qubit gate (and parameters for any single qubit gates necessary to implement the obtained two-qubits gate).
Quantum controller 315 can be configured to directly control quantum component 320. Quantum controller 315 can be a digital computing device (e.g., a computing device including a central processing unit, graphical processing unit, application specific integrated circuit, field-programmable gate array, or other suitable processor). Quantum controller 315 can configure quantum component 320 for computation, provide quantum gates to, and read state information out of quantum circuit 320.
Quantum controller 315 can include an Instruction Generation Module 316. Instruction Generation Module 316 can be configured to directly or indirectly provide bias drives to quantum circuit 320 to enable or disable interactions between qubits. Instruction Generation Module 316 can indirectly provide bias drives by providing instructions to a bias drive source (e.g., waveform generator or the like), causing the bias drive source to provide the bias drives to circuit 320. Instruction Generation Module 316 can apply quantum gates by providing one or more microwave pulses (or other gate drives) to qubits in quantum component 320. In various embodiments, Instruction Generation Module 316 can implement such gates by providing instructions to a computation drive source (e.g., a waveform generator or the like), causing the computational drive source to provide such microwave pulses (or other gate drives) to qubits in quantum component 320. The microwave pulses can be selected or configured to implement one or more quantum gates, as described herein. The microwave pulses can be provided to qubits using one or more coils coupled to the corresponding qubits. The coils can be external to quantum component 320 or on a chip implementing quantum component 320.
Quantum controller 315 can be configured to determine state information for quantum component 320. In some embodiments, quantum controller 315 can measure a state of one or more qubits of quantum component 320. The state can be measured upon completion of a sequence of one or more quantum operations. In some embodiments, instruction Generation Module 316 can provide a probe signal (e.g., a microwave probe tone) to a coupled resonator of quantum component 320, or provide instructions to a readout device (e.g., an arbitrary waveform generator) that provides the probe signal.
In various embodiments, quantum controller 315 can include a data processing module 317. Data processing module 317 can take the output signal (e.g. electrical/photonic), transforms it into discrete signals, and do data processing on it (e.g. averaging, post-processing) to obtain a computational result. In some embodiments, data processing module 317 can include, or be configured to receive information from, a detector configured to determine an amplitude and phase of an output signal received from the coupled resonator in response to provision of the microwave probe tone. The amplitude and phase of the output signal can be used to determine the state of the probed qubit(s). The disclosed embodiment are not limited to any particular method of measuring the state of the qubits.
Quantum component 320 can be configured to receive commands (e.g., bias drives, quantum gates, probe signal, or the like) from the classical component 310. In some embodiments, quantum component 320 can be implemented using a superconducting quantum circuit coupled to quantum controller 315 using at least one microwave drive line. The superconducting quantum circuit can implement multiple qubits (e.g., transmon qubits, fluxonium qubits, or any other suitable type of qubit), consistent with disclosed embodiments. In some embodiments, the superconducting quantum circuit can be realized using one or more chips containing the qubits, each of the chip(s) including at least a portion of the microwave drive line(s) coupling the qubit(s) to quantum controller 315.
In step 410, the conventional computing device (e.g., classical component 310) can obtain a description of a quantum computational task. Consistent with disclosed embodiments, the description of the quantum computational task can include a sequence of quantum gates applied to a set of two or more qubits, a unitary matrix acting on the set of two or more qubits, a function call for a quantum algorithm, or another suitable description. The conventional computing device can receive or retrieve the description of the quantum computational task from another system or a user of the conventional computing device. For example, a user can interact with an interface provided by the conventional computing device to generate the description of the quantum computational task.
In step 420, the conventional computing device can create a sequence of AshN gates and single-qubit gates implementing the quantum computational task. If necessary, the sequence can include SWAP gates. In some embodiments, the conventional computing device can create a first implementation of the quantum computational task as a sequence of arbitrary two-qubit gates. Consistent with disclosed embodiments, each two-qubit gate can then be implemented using AshN gates and (and optionally single qubit gates).
For example, when the description of the quantum computational task includes a unitary, the unitary can be decomposed into a sequence of gates. The sequence of gates can include two qubit gates. The disclosed embodiments are not limited to any particular method of decomposing the unitary into a sequence of gates. Similarly, when the description of the quantum computational task includes a function call, the conventional computing device can get a sequence of gates implementing the function call. The disclosed embodiments are not limited to any particular method of generating such a sequence of gates.
Consistent with disclosed embodiments, the conventional computing device can be configured to convert one or more gates in a sequence of gates (e.g., received or retrieve by the conventional computing device, or generated by the conventional computing device) into an AshN gate locally equivalent to the one or more gates. The conventional computing device can further be configured to generate one or more single-qubit gates to apply together with the AshN gate to yield the one or more gates. For example, the conventional computing device can convert the sequence of gates into a corresponding sequence of AshN gates (and additionally SWAP and/or single-qubit gates).
In some embodiments, as part of converting the sequence of gates, the conventional computing device can identify a two-qubit gate. As described herein, in some embodiments a SWAP gate cannot be implemented using an AshN gate. Accordingly, the conventional computing device can be configured to determine whether the two-qubit gate is a SWAP gate. The conventional computing device can determine an AshN implementation of the two-qubit gate in response to a determination that the two-qubit gate is not a SWAP gate. Accordingly, the converted sequence of gates may include both SWAP gates and AshN gates.
The conventional computing device can determine Weyl coordinates x, y, and z for the identified two-qubit gate. For example, the conventional computing device can perform a KAK decomposition to determine the interaction coefficients for the two-qubit gate. The conventional computing device can then determine the values of the drive time and drive amplitudes for each of the qubits. In a first step, the conventional computing device can determine the gate time using an interaction strength of the two qubits and the identified x coordinate of the two-qubit gate. The conventional computing device can determine a gate time such that the product of the interaction strength and the gate time (e.g., gt) is equivalent to the x coordinate. This equivalence can be determined by an equivalency condition. For example, gt can be equivalent to x when f1(gt)=f2(x). As an additional example, gt can be equivalent to x when |sin (gt)|=sin(x)).
In some embodiments, the conventional computing device can determine a set of candidate gate times that satisfy the equivalency condition (e.g., given an interaction strength). For example, when the equivalency condition is |sin (gt)|=sin(x)), such candidate gate times can include t0=x/g, t1=π/2−x/g, etc.
In some embodiments, the conventional computing device can select from the set of candidate gate times a gate time. In some instances, the selected gate time can be the minimum gate time. In some instances, the gate time can be selected using the sum of the y interaction coordinate and the magnitude of the z interaction coordinate. In some embodiments, the following function can be defined:
This function is closely related to solutions to tan θ=θ. Denote θk the kth smallest positive solution to tan θ=θ. Then
where k is the smallest integer such that θk≥α. Given a set of candidate solutions {tl: |sin(tl)|=sin(x)} and the smallest l such that ζ(gt1)≥sin (y+|z|), then tl will be the optimal driving time.
In some embodiments, the conventional computing device can determine dynamic decoupling gate drive amplitudes for the two qubits. The sum of the two gate drive amplitudes can depend on the sum of the y and z interaction coordinates. The difference of the two gate drive amplitudes can depend on the difference of the y and z interaction coordinates.
For example, in some embodiments, the two gate drive amplitudes can depend on two intermediate values ω1, ω2≥gtl. In such embodiments, the conventional computing device can find ω1 such that |sin (ω1)/ω1|*gt1=sin (y+z) and can find |sin (ω2)/ω2|*gtl=sin (y−z). The existence of these solutions is guaranteed by the continuity of |sin (ω)/ω|*gtl. In turn, the sum of the two gate drives can be selected as Ω1+Ω2=√{square root over (ω12−(gt1)2)}, while the difference of the two gate drives can be selected as Ω1−Ω2=√{square root over (ω22−(gt1)2)}.
In some embodiments, in addition to determining an implementation of the AshN gate locally equivalent to the identified two-qubit gate, the conventional computing device can determine one or more single-qubit gates. The single qubit gates can be corrections that cause the locally equivalent AshN gate to implement the original two-qubit gate.
In some instances, the AshN gate implementation may need to accommodate ZZ coupling between the qubits. In such instances, in terms of local equivalence, the characteristics |0|V0|1
| and |
0|V1|1
| given above can be expressed as:
Appropriate values for the gate time and drive amplitudes can be obtained using these characteristics as described herein.
In step 430, the conventional computing device can provide commands to the quantum computing device (e.g., quantum component 320) to apply the gate sequence to the appropriate arrangement of qubits. The commands can specify parameters for the microwave drives (e.g., amplitude, phase, frequency, duration, or the like) to implement the AshN (or SWAP, or single-qubit) gates in the appropriate sequence. The quantum computing device can implement the quantum computational task by applying the gate sequence to the qubits.
In step 440, the conventional computing device can provide commands to the quantum computing device to readout the results of the quantum computational task. The disclosed embodiments are not limited to any particular method of reading out the results of the task.
The disclosed embodiments are not limited to embodiments including a quantum computing device. In some embodiments, application of the gate sequence to the appropriate arrangement of qubits can be simulated by the original conventional computing device or another, separate conventional computing device. For example, the gate sequence could be generated on a laptop and application of the gate sequence could be stimulated using a cloud-computing platform. Upon completion of the simulation, the simulation results could be provided to the original conventional computing device.
In some embodiments, a non-transitory computer-readable storage medium including instructions is also provided, and the instructions may be executed by a device (such as the disclosed encoder and decoder), for performing the above-described methods. Common forms of non-transitory media include, for example, a floppy disk, a flexible disk, hard disk, solid state drive, magnetic tape, or any other magnetic data storage medium, a CD-ROM, any other optical data storage medium, any physical medium with patterns of holes, a RAM, a PROM, and EPROM, a FLASH-EPROM or any other flash memory, NVRAM, a cache, a register, any other memory chip or cartridge, and networked versions of the same. The device may include one or more processors (CPUs), an input/output interface, a network interface, and/or a memory.
The foregoing descriptions have been presented for purposes of illustration. They are not exhaustive and are not limited to precise forms or embodiments disclosed. Modifications and adaptations of the embodiments will be apparent from consideration of the specification and practice of the disclosed embodiments. For example, the described implementations include hardware, but systems and methods consistent with the present disclosure can be implemented with hardware and software. In addition, while certain components have been described as being coupled to one another, such components may be integrated with one another or distributed in any suitable fashion.
Moreover, while illustrative embodiments have been described herein, the scope includes any and all embodiments having equivalent elements, modifications, omissions, combinations (e.g., of aspects across various embodiments), adaptations or alterations based on the present disclosure. The elements in the claims are to be interpreted broadly based on the language employed in the claims and not limited to examples described in the present specification or during the prosecution of the application, which examples are to be construed as nonexclusive. Further, the steps of the disclosed methods can be modified in any manner, including reordering steps or inserting or deleting steps.
It should be noted that, the relational terms herein such as “first” and “second” are used only to differentiate an entity or operation from another entity or operation, and do not require or imply any actual relationship or sequence between these entities or operations. Moreover, the words “comprising,” “having,” “containing,” and “including,” and other similar forms are intended to be equivalent in meaning and be open ended in that an item or items following any one of these words is not meant to be an exhaustive listing of such item or items, or meant to be limited to only the listed item or items.
The features and advantages of the disclosure are apparent from the detailed specification, and thus, it is intended that the appended claims cover all systems and methods falling within the true spirit and scope of the disclosure. As used herein, the indefinite articles “a” and “an” mean “one or more.” Similarly, the use of a plural term does not necessarily denote a plurality unless it is unambiguous in the given context. Further, since numerous modifications and variations will readily occur from studying the present disclosure, it is not desired to limit the disclosure to the exact construction and operation illustrated and described, and accordingly, all suitable modifications and equivalents may be resorted to, falling within the scope of the disclosure.
As used herein, unless specifically stated otherwise, the term “or” encompasses all possible combinations, except where infeasible. For example, if it is stated that a database may include A or B, then, unless specifically stated otherwise or infeasible, the database may include A, or B, or A and B. As a second example, if it is stated that a database may include A, B, or C, then, unless specifically stated otherwise or infeasible, the database may include A, or B, or C, or A and B, or A and C, or B and C, or A and B and C.
It is appreciated that the above-described embodiments can be implemented by hardware, or software (program codes), or a combination of hardware and software. If implemented by software, it may be stored in the above-described computer-readable media. The software, when executed by the processor can perform the disclosed methods. The computing units and other functional units described in this disclosure can be implemented by hardware, or software, or a combination of hardware and software. One of ordinary skill in the art will also understand that multiple ones of the above-described modules/units may be combined as one module/unit, and each of the above-described modules/units may be further divided into a plurality of sub-modules/sub-units.
In the foregoing specification, embodiments have been described with reference to numerous specific details that can vary from implementation to implementation. Certain adaptations and modifications of the described embodiments can be made. Other embodiments can be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the invention being indicated by the following claims. It is also intended that the sequence of steps shown in figures are only for illustrative purposes and are not intended to be limited to any particular sequence of steps. As such, those skilled in the art can appreciate that these steps can be performed in a different order while implementing the same method.
The embodiments may further be described using the following clauses:
In the drawings and specification, there have been disclosed exemplary embodiments. However, many variations and modifications can be made to these embodiments. Accordingly, although specific terms are employed, they are used in a generic and descriptive sense only and not for purposes of limitation or restriction of the scope of the embodiments, the scope being defined by the following claims.
This application claims the benefit of U.S. Provisional Application No. 63/493,299, filed Mar. 30, 2023, which is incorporated herein by reference in its entirety.
Number | Date | Country | |
---|---|---|---|
63493299 | Mar 2023 | US |