Claims
- 1. A method of making an integrated circuit capacitor comprising the steps of:a) providing a P− substrate; b) forming a N isolation band in a portion of said P− substrate; c) forming a N+ type trench storage node extending through said N isolation band and into said P− substrate, and wherein an inversion region is formed in said P− substrate proximate said N+ type trench storage node with carriers supplied from said N isolation band, said inversion region comprising a counter electrode for said integrated circuit capacitor.
- 2. The method of claim 1 wherein said storage node comprises N+ type material doped greater than 5×1019 ions/cm3 and wherein said lightly doped substrate comprises P− type material doped between 1×1014 and 1×1017 ions/cm3 and wherein the step of forming said N type isolation band comprises providing a doping dose between 1×1013 and 20×1013 ions/cm2.
- 3. The method of claim 1 wherein said storage node comprises N+ type material doped greater than 1×1020 ions/cm3 and wherein said lightly doped substrate comprises P− type material doped between 1×1015 and 5×1015 ions/cm3 and wherein the step of forming said N type isolation band comprises providing a doping dose of about 5×1013 ions/cm2.
- 4. A method of making an integrated circuit capacitor comprising the steps of:a) providing a N− substrate; b) forming a P isolation band in a portion of said N− substrate; c) forming a P+ type trench storage node extending through said P isolation band and into said N− substrate, and wherein an inversion region is formed in said N− substrate proximate said P+ type trench storage node with carriers supplied from said P isolation band, said inversion region comprising a counter electrode for said integrated circuit capacitor.
- 5. The method of claim 4 wherein said storage node comprises P+ type material doped greater than 5×1019 ions/cm3 and wherein said lightly doped substrate comprises N− type material doped between 1×1014 and 1×1017 ions/cm3 and wherein the step of forming said P type isolation band comprises providing a doping dose between 1×1013 and 20×1013 ions/cm2.
- 6. The method of claim 4 wherein said storage node comprises P+ type material doped greater than 1×1020 ions/cm3 and wherein said lightly doped substrate comprises N− type material doped between 1×1015 and 5×1015 ions/cm3 and wherein the step of forming said P type isolation band comprises providing a doping dose of about 5×1013 ions/cm2.
- 7. A method for making an integrated circuit capacitor comprising the steps of:a) providing a substrate; b) forming a storage node extending into said substrate; c) forming a dielectric between said storage node and said substrate; and d) forming an inversion region in said substrate surrounding said storage node, said inversion region forming a counter electrode for said capacitor.
- 8. The method of claim 7 wherein the step of forming an inversion region comprises forming said inversion region without applying a bias to said storage node.
- 9. The method of claim 7 further comprising the step of forming an isolation layer in said substrate, and wherein said isolation layer supplies charge carriers for said inversion layer.
- 10. The method of claim 9 wherein the step of forming an isolation layer forms a connection to said counter electrode, wherein said connection to said counter electrode is used to determine the potential of said counter electrode.
- 11. The method of claim 9 wherein the step of forming said isolation layer comprises forming an N type material with a doping dose between 1×1013 and 20×1013 ions/cm2 and wherein said charge carriers supplied to said inversion layer comprises electrons.
- 12. The method of claim 9 wherein the step of forming said isolation layer comprises forming an N type material with a doping dose of about 5×1013 ions/cm2 and wherein said charge carriers supplied to said inversion layer comprises electrons.
- 13. The method of claim 9 wherein the step of forming said isolation layer comprises forming a P type material with a doping dose between 1×1013 and 20×1013 ions/cm2 and wherein said charge carriers supplied to said inversion layer comprise holes.
- 14. The method of claim 9 wherein the step of forming said isolation layer comprises forming a P type material with a doping dose of about 5×1013 ions/cm2 and wherein said charge carriers supplied to said inversion layer comprise holes.
- 15. The method of claim 7 wherein the step of forming said storage node comprises doping semiconductor material in said storage node greater than 5×1019 ions/cm3 and wherein the step of providing said lightly doped substrate comprises providing a substrate doped between 1×1014 and 1×1017 ions/cm3.
- 16. The method of claim 7 wherein the step of forming said storage node comprises doping semiconductor material in said storage node greater than 1×1020 ions/cm3 and wherein the step of providing said lightly doped substrate comprises providing a substrate doped between 1×1015 and 5×1015 ions/cm3.
- 17. The method of claim 7 wherein the step of forming said counter electrode comprises forming a common counter electrode.
- 18. The method of claim 7 wherein the step of providing a substrate comprises providing a lightly doped substrate.
RELATED APPLICATIONS
This application is a divisional of a U.S. Patent Application entitled “Deep Trench Cell Capacitor with Inverting Counter Electrode”, Ser. No. 08/688,345, filed on Jul. 30, 1996, now U.S. Pat. 5,793,075 which is incorporated herein by reference.
US Referenced Citations (25)
Non-Patent Literature Citations (1)
Entry |
Streetman, Ben G., Solid State Electronic Devices, Third Edition, Chapter 9, “Integrated Circuits”, 1990, pp. 354-356. |