BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a plan view showing a layout of a pixel part of a first embodiment of a semiconductor device according to the present invention;
FIG. 2 is a circuit diagram showing an important part of the first embodiment of the semiconductor device according to the present invention;
FIG. 3 is a flow chart for explaining a test of the pixel part of the semiconductor device;
FIG. 4 is a plan view showing a layout of a pixel part of a second embodiment of the semiconductor device according to the present invention; and
FIG. 5 is a circuit diagram showing an important part of the second embodiment of the semiconductor device according to the present invention.