Deflection circuit with a retrace capacitive transformation

Description

BACKGROUND

A typical horizontal deflection circuit for a CRT includes a horizontal deflection winding of a deflection yoke coupled in parallel with a retrace capacitance provided by, for example, a retrace capacitor. A horizontal output or switching transistor operating at a horizontal deflection frequency is coupled across the retrace capacitor. A supply voltage is coupled to the switching transistor and to the retrace capacitor via a supply inductance.

For a given deflection winding inductance and a supply voltage magnitude, the effective retrace capacitance required to produce the same deflection current amplitude would have to be smaller when a higher deflection frequency is utilized than when a lower deflection frequency is utilized. Therefore, the flyback pulse voltage developed across a horizontal output transistor would have to be higher at the higher deflection frequency. For a given switching transistor breakdown voltage characteristic, the maximum flyback pulse voltage that is permitted to develop across a horizontal output transistor limits the allowable, maximum horizontal frequency that can be utilized. Therefore, it may be desirable to reduce the effective retrace capacitance without substantially increasing the flyback pulse voltage developed across the horizontal output transistor.

A horizontal deflection circuit, embodying an inventive feature, includes switched, first and second retrace capacitors coupled in series with a deflection winding. First and second switching transistors are coupled across the first and second retrace capacitors, respectively. A supply voltage is coupled via a supply inductance to a junction terminal between the retrace capacitors. The switching transistors are switched off, during retrace, to produce a first retrace pulse voltage across the first retrace capacitance and a second retrace pulse voltage across the second retrace capacitance. The retrace pulse voltage across the deflection winding is equal to the sum of a first retrace pulse voltage and the second retrace pulse voltage and is larger than each. The retrace pulse voltage across the deflection winding is proportional to a ratio of the capacitances of the first and second capacitances. Thereby, capacitive transformation is obtained. Similarly, a voltage across an S-shaping capacitor that is coupled in series with the deflection winding is also proportional to a ratio of the capacitances of the first and second capacitances.

Advantageously, the peak voltage developed across each of the switching transistors is substantially smaller than the sum retrace pulse voltage developed across the deflection winding. The result is that, for a given switching transistor breakdown voltage characteristic, the maximum scan frequency that can be employed is, advantageously, higher than in a deflection circuit in which the entire retrace pulse voltage across the deflection winding is developed across a single switching transistor.

A horizontal deflection circuit, embodying an inventive feature, includes an East-West raster distortion correction circuit for correcting pincushion raster distortion. Switched, first and second retrace capacitors are provided for providing the aforementioned capacitive transformation. Throughout a given vertical trace interval, the retrace switching timing of each one of the switching transistors remains the same relative to that of the other one of the switching transistors. Thereby, advantageously, East-West raster distortion correction is obtained in a manner that avoids producing retrace time modulation.

SUMMARY OF THE INVENTION

A video display deflection apparatus, embodying an inventive feature, includes a first retrace capacitance and a second retrace capacitance. A deflection winding is coupled to the first and second retrace capacitances to form a resonant circuit with the first and second retrace capacitances, during retrace. A first switching transistor is coupled to the first retrace capacitance for generating a first retrace pulse voltage in the resonant circuit. A second switching transistor is coupled to the second retrace capacitance for generating a second retrace pulse voltage in the second retrace capacitance. The first and second retrace pulse voltage are applied to the deflection winding in a manner to provide for retrace capacitance transformation. The second switching transistor is responsive to the first retrace pulse voltage for controlling, in accordance with the first retrace pulse voltage, when a switching operation occurs in the second switching transistor.

BRIEF DESCRIPTION OF THE DRAWING

FIGS. 1

a

and

1

b

illustrate a combined deflection circuit, embodying a first inventive feature;

FIGS. 1

a

and

1

c

illustrate a combined deflection circuit, embodying a second inventive feature; and

FIGS. 2

a,

2

b,

2

c

and

2

d

illustrate waveforms useful for explaining the operation of the combined circuit of

FIGS. 1

a

and

1

b.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

A deflection circuit

100

of

FIG. 1

a,

when combined with an arrangement

100

b

of

FIG. 1

b,

operates at a horizontal frequency of 3 times fH and a period one third of H. The term fH denotes the horizontal frequency in a television standard such as 15,525 KHz. Similarly, the term H denotes the horizontal period in the television standard.

Deflection circuit

100

of

FIG. 1

a

includes a primary winding W

1

coupled to a source of a constant value supply voltage B+. Winding W

1

of a conventional flyback transformer T is also coupled to a horizontal output or switching transistor Q

1

controlled by a horizontal drive signal

50

having approximately 50% duty cycle. An emitter voltage of transistor Q

1

is at a common conductor potential, or ground. A junction terminal

51

of winding W

1

and a collector of transistor Q

1

is coupled to a retrace capacitor C

1

a.

A retrace capacitor Cb is coupled to terminal

51

and in parallel with transistor Q

1

. A terminal

52

of capacitor C

1

a

is coupled to a retrace capacitor C

1

b.

A conventional damper diode D

1

a

is coupled in parallel with capacitor C

1

a.

A conventional damper diode D

1

b

is coupled in parallel with capacitor C

1

b.

Junction terminal

52

is coupled to a conventional East-West modulation inductor Lew. Inductor Lew has a terminal

53

that is coupled to a collector of a conventional East-West modulation and to a conventional filter capacitor Cew to form a diode modulator. Transistor QEW is controlled in a conventional manner by a vertical rate East-West modulation signal E/W-DRIVE having a period V. Period V denotes the vertical period in the television standard such as 16.6 milisecond. A feedback resistor transistor Rew is coupled between the collector and base of transistor QEW to provide operation in class A mode of operation. A vertical rate modulation voltage Vm is developed at terminal

53

, in a conventional manner. A conventional S-shaping capacitor Cs is coupled between terminal

52

and a terminal

54

.

A deflection winding Ly of

FIG. 1

b

is coupled to a switched, retrace capacitor C

2

to form a series arrangement between terminals

51

and

54

. A switching transistor Q

2

is coupled in parallel with capacitor C

2

for switching capacitor C

2

. A return recovery current in transistor Q

2

is performed by the operation of an integrally formed damper diode, not shown, formed with transistor Q

2

in the same integrated circuit.

FIGS. 2

a

-

2

d

illustrate waveforms useful for explaining the operation of the circuit of

FIGS. 1

a

and

1

b.

Each waveform is applicable to a corresponding horizontal period H/3. Similar symbols and numerals in

FIGS. 1

a,

1

b

and

2

a

-

2

d

indicate similar items or functions.

Transistor Q

1

of

FIG. 1

a

is turned off to form a retrace resonant circuit that includes deflection winding Ly of

FIG. 1

b

and capacitor C

1

a

of

FIG. 1

a,

during retrace. A resonant retrace pulse voltage V

1

having a period H/3 is developed at terminal

51

of winding Ly. As shown in

FIG. 2

c,

Voltage V

1

is generated when a collector current iQ

1

of

FIG. 2

a

of transistor Q

1

of

FIG. 1

a

abruptly drops to zero. Pulse voltage V

1

of

FIG. 2

c

is coupled to transformer T of

FIG. 1

a

for producing an ultor voltage U.

In carrying out an inventive feature, pulse voltage V

1

developed at terminal

51

is applied to a current path formed by a power supply filter capacitor C

101

, a capacitor C

3

, a resistor R

2

, a resistor R

1

and an internal gate-source capacitance, not shown, of transistor Q

2

. A supply voltage V+12 of 12V is developed in capacitor C

101

. As a result of pulse voltage V

1

, a positive voltage is produced at a terminal

62

of resistor R

2

relative to that at a terminal

61

of resistor R

2

. Resistor R

2

is coupled between an emitter of transistor Q

3

and terminal

61

. Terminal

62

forms a junction terminal for the emitter of a transistor Q

3

, resistor R

1

and resistor R

2

. The voltage produced at terminal

61

of resistor R

2

is coupled to the base of transistor Q

3

via a diode D

4

when diode D

4

is forward biased to turn on transistor Q

3

.

When transistor Q

3

is turned on, a positive charged, gate-source capacitance, not shown, of transistor Q

2

that maintains transistor Q

2

conductive is quickly discharged via a current path formed by transistor Q

3

and resistor R

1

. Then, transistor Q

2

turns off and remains in the turned-off state for the entire remainder of a retrace interval TRET of

FIGS. 2

a

-

2

d.

Thereby, a retrace pulse voltage V

2

of

FIG. 1

b

is generated in capacitor C

2

. Voltage V

2

of

FIG. 2

c

is generated when a collector current iQ

2

of

FIG. 2

b

of transistor Q

2

of

FIG. 1

b

abruptly drops to zero.

A combined retrace pulse voltage VLy, developed across deflection winding Ly of

FIG. 1

a,

is equal to the sum of retrace pulse voltage V

1

a

of

FIG. 1

a,

developed in retrace capacitor C

1

a,

and retrace pulse voltage V

2

of

FIG. 1

b,

developed in retrace capacitor C

2

. Pulse voltage VLy is larger than each of pulse voltage V

2

and pulse voltage V

1

a

of

FIG. 1

a.

Thereby, advantageously, the peak of pulse voltages V

1

, developed across switching transistor Q

1

, is substantially smaller than voltage VLy. Therefore, for a given inductance of winding Ly of

FIG. 1

b

and a breakdown voltage of switching transistor Q

1

of

FIG. 1

a,

the scan frequency that can be employed is advantageously higher. The scan frequency that can be employed is higher than if retrace pulse voltage VLy of

FIG. 1

b

were developed entirely across switching transistor Q

1

of

FIG. 1

a.

The result is that retrace capacitor transformation is obtained.

Circuit

100

of

FIG. 1

a

that is coupled to circuit

100

b

of

FIG. 1

b

provides capacitive transformation that is, advantageously, constant throughout vertical trace. For simplification purposes assume that the inductance of winding W

1

is large or infinite. Thus, an average voltage VCs across capacitor Cs of

FIG. 1

a

can be expressed as follows:

average of voltage VCs = (the difference between voltages B, + VmAv) x \cdot (1 + \frac{the value of capacitor C1a}{the value of c apacitor C2} .

The term VmAv represents the average value of voltage Vm. The term

(1 + \frac{the value of capacitor C1a}{the value of c apacitor C2})

represents the capacitive transformation factor.

Thus, because of retrace capacitor transformation, measured by the aforementioned capacitive transformation factor, voltage VCs is larger for a given difference between voltage B+ and the average value of voltage Vm. The increased average value of voltage VCs enables the generation of a given amplitude of deflection current iy at a higher deflection frequency. Also, because of retrace capacitor transformation, the effective retrace capacitance is smaller. Smaller retrace capacitance results in a shorter retrace interval TRET of

FIGS. 2

a

-

2

d.

During the first half of trace, diodes D

1

a

and D

1

b

are conductive in a conventional manner. Additionally, the integrally formed damper diode, not shown, of transistor Q

2

of

FIG. 1

b

is also conductive. During the second half of trace, transistor Q

1

of

FIG. 1

a

is turned on, in a conventional manner.

As soon as damper diodes D

1

a

and D

1

b

of

FIG. 1

a

and the integrally formed diode, not shown, of transistor Q

2

of

FIG. 1

b

become conductive, terminal

51

of

FIG. 1

a

is clamped to ground potential. Voltage V+12 is applied via a diode D

3

of

FIG. 1

b

coupled in parallel with capacitor C

3

. Consequently, diode D

3

becomes forward biased, transistor Q

3

turns off and a current, not shown, charges the gate-source capacitance, not shown, of transistor Q

2

via resistors R

2

and R

1

. Diode D

4

prevents transistor Q

3

from conducting via reverse base-emitter voltage.

After a short delay time determined by the gate-source capacitance, not shown, of transistor Q

2

, transistor Q

2

is turned on to form a low drain-source resistance. This low resistance is placed in parallel with the integrally formed, forward biased damper diode, not shown, of transistor Q

2

for a portion of the trace interval similar to the turn on interval in transistor Q

1

of

FIG. 1

a.

Diode D

5

of

FIG. 1

b

protects transistor Q

2

from excessive gate voltage.

In carrying out another inventive feature, a phase between retrace voltage V

1

of

FIG. 2

c

and retrace voltage V

2

remains the same in each horizontal deflection cycle, throughout vertical interval V. The result is that retrace interval TRET has the same width, throughout vertical interval V. Thereby, advantageously, retrace time modulation is avoided.

In a second alternative, deflection circuit

100

of

FIG. 1

a

is coupled to the arrangement of a booster circuit

100

c

of

FIG. 1

c,

instead of circuit

100

b

in

FIG. 1

b.

Similar symbols and numerals in

FIG. 1

c,

except for the prime symbol (′), and in

FIGS. 1

a,

1

b

and

2

a

-

2

d

indicate similar items or functions.

Deflection winding Ly′ of

FIG. 1

c

is interposed between a capacitor C

2

′ and capacitor C

1

a

of

FIG. 1

a.

Advantageously, circuit

100

c

of

FIG. 1

c

divides a retrace pulse voltage VLy′, across winding Ly′, into a positive voltage with respect to ground, at terminal

51

, and a symmetrical, negative voltage with respect to ground, at terminal

54

. Thus, a symmetrically driven arrangement is provided. The peak of each retrace pulse voltage at terminals

51

and

54

with respect to ground is smaller than the peak of their sum. Therefore, advantageously, less demanding electrical isolation is required than in the combined arrangement of

FIGS. 1

a

and

1

b

that provides a non-symmetrically driven arrangement.

A capacitor C

3

′ of

FIG. 1

c

is used for sensing an occurrence of retrace pulse voltage V

1

at terminal

51

, similarly to the way done in

FIG. 1

b.

A forward biased diode D

4

′ of

FIG. 1

c

coupled in series with capacitor C

3

′ and a capacitor C

4

′ causes a transistor Q

3

′ to conduct by charging capacitor C

4

′. Consequently, a positive charged gate-source capacitance, not shown, of a transistor Q

2

′ is quickly discharged via a resistor R

1

′ and transistor Q

3

′. Transistor Q

2

′ turns off and remains turned off for the entire remainder of retrace. During a second half of horizontal retrace, when voltage V

1

of

FIG. 2

c

decreases from its peak magnitude, capacitor C

3

′

FIG. 1

c

discharges via a diode D

3

′, resistor R

1

′, a forward biased D

5

′ and deflection winding Ly′. Diode D

3

is coupled in an anti-parralel manner with respect to diode D

4

′. Because capacitor C

4

′ is not included in the retrace discharge current path of capacitor C

3

′, the energy in capacitor C

4

′ is maintained stored, during retrace. Transistor Q

3

′ remains non-conductive because no base current is produced, during the second half of retrace.

As soon as capacitor C

3

′ is discharged completely, indicating the end of retrace, capacitor C

4

′ starts discharging. A diode D

6

′ that is coupled between the base of transistor Q

3

′ and winding Ly′ is forward biased. Capacitor C

4

′, now a voltage source, charges the gate-source capacitance, not shown, of transistor Q

2

′ via a resistor R

2

′. Transistor Q

2

′ turns on after a delay time similar to that in

FIG. 1

b.

A diode D

5

′ also performs similar protection function to that described with respect to diode D

5

in

FIG. 1

b.

Claims

1. A video display deflection apparatus, comprising:a first retrace capacitance; a second retrace capacitance; a deflection winding coupled to said first and second retrace capacitances to form a resonant circuit with said first and second retrace capacitances, during retrace; a first switching transistor coupled to said first retrace capacitance for generating a first retrace pulse voltage in said resonant circuit; and a second switching transistor coupled to said second retrace capacitance for generating a second retrace pulse voltage in said second retrace capacitance, said first and second retrace pulse voltages being applied to said deflection winding in a manner to provide for retrace capacitance transformation, said second switching transistor being responsive to a timing signal produced by said first switching transistor for controlling, in accordance with said timing signal, a switching of frequencies of said second switching transistor.
2. A video display deflection apparatus according to claim 1, further comprising an East-West modulator responsive to a periodic, control signal having a frequency related to a vertical deflection frequency for modulating a deflection current in said deflection winding, wherein a phase difference between said first and second retrace pulse voltages remains substantially the same, during a vertical trace interval.
3. A video display deflection apparatus according to claim 2, wherein said East-West modulator includes a diode modulator.
4. A video display deflection apparatus according to claim 1, wherein said first and second retrace capacitances are coupled in series to form a circuit branch that is coupled in parallel with said deflection winding.
5. A video display deflection apparatus according to claim 1, wherein said first retrace pulse voltage is developed in said first retrace capacitance.
6. A video display deflection apparatus, comprising:a first retrace capacitance; a second retrace capacitance; a deflection winding coupled to said first and second retrace capacitances to form a resonant circuit with said first and second retrace capacitances, during retrace; a first switching transistor responsive to an input signal at a frequency related to a first deflection frequency and coupled to said first retrace capacitance for generating a resonant, first retrace pulse voltage in said first retrace capacitance; a second switching transistor responsive to said input signal and coupled to said second retrace capacitance for generating a second retrace pulse voltage in said second retrace capacitance, said second and first retrace pulse voltages being coupled to said deflection winding to produce a deflection current in said deflection winding in a manner to provide for retrace capacitance transformation; and a modulator responsive to a periodic control signal having a frequency related to a second deflection frequency for modulating a deflection current in said deflection winding to provide for raster distortion correction without varying a phase difference between said first and second retrace pulse voltages, during a period of said control signal.
7. A video display deflection apparatus according to claim 6, wherein said modulator provides for East-West raster distortion correction.
8. A video display deflection apparatus according to claim 6, wherein said second switching transistor is responsive to said first retrace pulse voltage for controlling, in accordance with said first retrace pulse voltage, when a switching operation occurs in said second switching transistor.
9. A video display deflection apparatus according to claim 6, wherein said first and second retrace capacitances are coupled in series to form a circuit branch that is coupled in parallel with said deflection winding.

CROSS REFERENCE TO RELATED APPLICATIONS

This application claims priority of U.S. provisional application No. 60/228,231 filed Aug. 25, 2000. The invention relates to a deflection circuit of a cathode ray tube (CRT).

US Referenced Citations (12)

Number	Name	Date	Kind
4104567	Peer et al.	Aug 1978	A
4147964	Luz et al.	Apr 1979	A
4206388	Ishigaki et al.	Jun 1980	A
4242714	Yoshida et al.	Dec 1980	A
4513228	Teuling	Apr 1985	A
4540933	Teuling	Sep 1985	A
4733141	Watanuki	Mar 1988	A
4837457	Bergstrom et al.	Jun 1989	A
4864197	Fitzgerald	Sep 1989	A
5416389	Merlo et al.	May 1995	A
5714849	Lee	Feb 1998	A
6124686	Kikuchi et al.	Sep 2000	A

Foreign Referenced Citations (1)

Number	Date	Country
10-108034	Apr 1998	JP

Non-Patent Literature Citations (1)

Entry
Schematic Diagram 1999 of Sony AE-5 Television Receiver Chassis Model KV-2PFX65.

Provisional Applications (1)

	Number	Date	Country
	60/228231	Aug 2000	US

Deflection circuit with a retrace capacitive transformation

Information

Patent Number

Date Filed

Date Issued

Inventors

Original Assignees

Examiners

Agents

CPC

US Classifications

Field of Search

US

International Classifications