Deformable micromirror device

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a spatial light modulator using a micromirror, which is applied to a display device, etc., and more particularly, to a technology related to an optimum wiring pattern for deformable micromirror device.

2. Description of the Related Art

After the dominance of CRT technology in the display industry over 100 years, Flat Panel Display (noted as “FPD” hereinafter) and Projection Display have obtained popularity because of the smaller form-factor and larger size of screen. Among several types of projection displays, the ones using micro-Spatial Light Modulators (SLMs) are gaining recognition by consumers because of high performance of picture quality as well as lower cost than FPDs. There are two types of a micro-SLM used for projection displays in the market. One is micro-Liquid Crystal Display (LCD) and the other is micromirror technology. Because a micromirror device uses un-polarized light, a micromirror device has an advantage on brightness over micro-LCD, which uses polarized light.

Even though there have been significant advances of the technologies implementing an electromechanical micromirror device as an SLM in recent years, there are still limitations and difficulties when it is employed to provide a high quality image. Specifically, when the images are digitally controlled, the image quality is adversely affected due to the fact that the images are not displayed with a sufficient number of gray scales.

An electromechanical micromirror device is drawing a considerable interest as an SLM. The electromechanical micromirror device consists of “a mirror array” arraying a large number of mirror elements. In general, the mirror elements ranging from 60,000 to several millions are arrayed on a surface of a substrate in an electromechanical micromirror device. Referring to FIG. 1A for an image display system 1 including a screen 2 is disclosed in a reference U.S. Pat. No. 5,214,420. A light source 10 is used for generating light energy for illuminating the screen 2. The generated light 9 is further collimated and directed toward a lens 12 by a mirror 11. Lenses 12, 13 and 14 form a beam columnator operative to columnate light 9 into a column of light 8. A spatial light modulator (SLM) 15 is controlled on the basis of data input by a computer 19 via a bus 18 and selectively redirects the portions of light from a path 7 toward an enlarger lens 5 and onto screen 2. The SLM 15 has a mirror array includes switchable reflective elements 17, 27, 37, and 47 each comprising a mirror 33 connected by a hinge 30 and supported on a surface 16 of a substrate in the electromechanical mirror device as shown in FIG. 1B. When the element 17 is in one position, a portion of the light from the path 7 is redirected along a path 6 to lens 5 where it is enlarged or spread along the path 4 to impinge on the screen 2 so as to form an illuminated pixel 3. When the element 17 is in another position, the light is redirected away from the display screen 2 and hence the pixel 3 is dark.

Most of the conventional image display devices such as the devices disclosed in U.S. Pat. No. 5,214,420 are implemented with a dual-state mirror control that controls the mirrors to operate at a state of either ON or OFF. The quality of an image display is limited due to the limited number of gray scales. Specifically, in a conventional control circuit that applies a PWM (Pulse Width Modulation), the quality of the image is limited by the LSB (least significant bit) or the least pulse width as control related to the ON or OFF state. Since the mirror is controlled to operate in an either ON or OFF state, the conventional image display apparatuses have no way to provide a pulse width to control the mirror that is shorter than the control duration allowable according to the LSB. The least quantity of light, which determines the least amount of adjustable brightness for adjusting the gray scale, is the light reflected during the time duration according to the least pulse width. The limited gray scale due to the LSB limitation leads to a degradation of the quality of the display image.

Specifically, FIG. 1C exemplifies a control circuit for controlling a mirror element according to the disclosure in the U.S. Pat. No. 5,285,407. The control circuit includes a memory cell 32. Various transistors are referred to as “M*” where “*” designates a transistor number and each transistor is an insulated gate field effect transistor. Transistors M5 and M7 are p-channel transistors; while transistors M6, M8, and M9 are n-channel transistors. The capacitances C1 and C2 represent the capacitive loads in the memory cell 32. The memory cell 32 includes an access switch transistor M9 and a latch 32a, which is based on a Static Random Access switch Memory (SRAM) design. The transistor M9 connected to a Row-line receives a DATA signal via a Bit-line. The memory cell 32—written data is accessed when the transistor M9 that has received the ROW signal on a Word-line is turned on. The latch 32a consists of two cross-coupled inverters, i.e., M5/M6 and M7/M8, which permit two stable states, that is, a state 1 is Node A high and Node B low, and a state 2 is Node A low and Node B high.

The control circuit as illustrated in FIG. 1C controls the mirrors to switch between two states and the control circuit drives the mirror to oscillate to either an ON or OFF deflected angle (or position) as shown in FIG. 1A. The minimum quantity of light controllable to reflect from each mirror element for image display, i.e., the resolution of gray scale of image display for a digitally controlled image display apparatus, is determined by the least length of time that the mirror is controllable to hold at the ON position. The length of time that each mirror is controlled to hold at an ON position is in turn controlled by multiple bit words.

FIG. 1D shows the “binary time durations” in the case of controlling SLM by four-bit words. As shown in FIG. 1D, the time durations have relative values of 1, 2, 4, and 8 that in turn determine the relative quantity of light of each of the four bits, where the “1” is least significant bit (LSB) and the “8” is the most significant bit. According to the PWM control mechanism, the minimum quantity of light that determines the resolution of the gray scale is a brightness controlled by using the “least significant bit” for holding the mirror at an ON position during a shortest controllable length of time.

In a simple example with n bits word for controlling the gray scale, one frame time is divided into (2ⁿ−1) equal time slices. If one frame time is 16.7 msec., each time slice is 16.7/(2ⁿ−1) msec.

Having set these time lengths for each pixel in each frame of the image, the quantity of light in a pixel which is quantified as 0 time slices is black (no the quantity of light), 1 time slice is the quantity of light represented by the LSB, and 15 time slices (in the case of n=4) is the quantity of light represented by the maximum brightness. Based on quantity of light being quantified, the time of mirror holding at the ON position during one frame duration is determined by each pixel. Thus, each pixel with a quantified value which is more than 0 time slices is displayed by the mirror holding at an ON position with the number of time slices corresponding to its quantity of light during one frame duration. The viewer's eye integrates brightness of each pixel so that the image is displayed as if the image were generated with analog levels of light.

For controlling deflectable micromirror devices, the PWM calls for the data to be formatted into “bit-planes”, where each bit-plane corresponds to a bit weight of the quantity of light. Thus, when the brightness of each pixel is represented by an n-bit value, each frame of data has the n-bit-planes. Then, each bit-plane has a 0 or 1 value for each mirror element. In the PWM described in the preceding paragraphs, each bit-plane is independently loaded and the mirror elements are controlled according to bit-plane values corresponding to them during one frame. For example, the bit-plane representing the LSB of each pixel is displayed as 1 time slice.

SUMMARY OF THE INVENTION

A micromirror device according to one preferred embodiment of the present invention is a micromirror device for making an image display with digital image data, and comprises pixel elements, each of which makes pulse width modulation (PWM) for incident light depending on the deflection state of light and which are arranged in the form of a matrix. Each of the pixel elements has a mirror, at least one memory cell comprising a transistor and a capacitor, and an electrode connected to each transistor. Memory cells arranged successively in a ROW direction are connected by a ROW line. The image data is loaded at a time interval during which the voltage of the electrode can hold the deflection state of a pixel element.

A micromirror device according to another preferred embodiment of the present invention is a micromirror device for making an image display with digital image data, and comprises pixel elements, each of which makes pulse width modulation (PWM) for incident light depending on the deflection state of light and which are arranged in the form of a matrix. The array of the pixel elements is composed of B subsets each including pixel elements of M_s(COLUMNs)×N_s(ROWs) (M_s, N_sand B are natural numbers). Each of the pixel elements has a mirror, at least one memory cell comprising a transistor and a capacitor, and an electrode connected to each transistor. Memory cells arranged successively in a ROW direction in each of the subsets are connected by an independent ROW line. The image data is loaded at a time interval during which the voltage of the electrode can hold the deflection state of a pixel element.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A is a schematic showing a conventional two-dimensional digital video system using a deformable micromirror device;

FIG. 1B is a schematic showing part of the deformable micromirror device shown in FIG. 1A;

FIG. 1C is a diagram showing a conventional control circuit of a micromirror;

FIG. 1D is a schematic showing binary time intervals when a control is performed with 4-bit words;

FIG. 2 is a schematic showing a simplified configuration of a micromirror device according to a first preferred embodiment;

FIG. 3 is a schematic showing a simplified configuration of each pixel element of the micromirror device according to the first preferred embodiment;

FIG. 4 is a schematic explaining simplified configurations of digital video systems (display devices) using different numbers of micromirror devices according to the first preferred embodiment;

FIG. 5 is a schematic explaining a minimum display duration equivalent to the least significant bit of 10 bits for each color according to the number of micromirror devices used in the digital video system shown in FIG. 4, when an RGB color display of 10 bits is made in the micromirror device according to the first preferred embodiment;

FIG. 6 is a schematic explaining a propagation delay time in a delay equivalent circuit of memory cells in 1 ROW line;

FIG. 7 is a schematic showing a simplified configuration of a micromirror device according to a second preferred embodiment;

FIG. 9A is a schematic showing an ON state of a mirror in a pixel element;

FIG. 9B is a schematic showing the state of a change in the quantity of reflection light to projection optics when a mirror is controlled to be ON;

FIG. 10A is a schematic showing an OFF state of a mirror in a pixel element;

FIG. 10B is a schematic showing the state of a change in the quantity of reflection light to the projection optics when the mirror is controlled to be OFF;

FIG. 11A is a first schematic showing the oscillation state of a mirror in a pixel element;

FIG. 11B is a first schematic showing the state of a change in the quantity of reflection light to the projection optics when the oscillation of the mirror is controlled;

FIG. 12A is a second schematic showing the oscillation state of a mirror in a pixel element; and

FIG. 12B is a second schematic showing the state of a change in the quantity of reflection light to the projection optics when the oscillation of the mirror is controlled.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Preferred embodiments according to the present invention are described below with reference to the drawings.

First Preferred Embodiment

FIG. 2 is a schematic showing a simplified configuration of a micromirror device that is a spatial light modulator (SLM) using a micromirror according to the first preferred embodiment of the present invention. FIG. 3 is a schematic showing a simplified configuration of each pixel element of the micromirror device according to this preferred embodiment. FIG. 4 is a schematic explaining simplified configurations of digital video systems (display devices) using different numbers of micromirror devices according to this preferred embodiment. FIG. 5 is a schematic explaining a minimum display duration equivalent to the least significant bit of 10 bits for each color according to the number of micromirror devices used in the digital video systems shown in FIG. 4, when an RGB color display of 10 bits is made in the micromirror device according to this preferred embodiment. FIG. 6 is a schematic explaining a propagation delay time in a delay equivalent circuit of memory cells in 1 ROW line of the micromirror device according to this preferred embodiment.

As shown in FIG. 2, the micromirror device 1001 according to this preferred embodiment comprises a timing controller (timing control circuit) 1002, a selector (data selection circuit) 1003, a ROW line decoder 1004, a plurality of COLUMN drivers (column line driving circuits) 1005, a pixel element array 1006 where a plurality of pixel elements are arranged in the form of an array, and other constituent elements. The pixel element array 1006 has a memory array where a plurality of memory cells 1007 are arranged in the form of an array of M (COLUMNs)×N (ROWs). In this figure, only the upper left memory cell is denoted with a reference numeral (1007) as a representative.

The timing controller 1002 controls the selector 1003 and the ROW line decoder 1004 according to a digital control signal from an external control circuit not shown.

The selector 1003 transfers an n-bit digital data signal, which is transferred from the external control circuit not shown via an n-bit data bus line, to at least one COLUMN driver 1005 according to a control of the timing controller 1002.

The COLUMN driver 1005 drives COLUMN lines 1008 by outputting the n-bit digital image data signal, which is transferred from the selector 1003, to the connected COLUMN lines 1008 of the pixel element array 1006. In this figure, only the leftmost COLUMN line is denoted with a reference numeral (1008) as a representative.

The ROW line decoder 1004 drives an arbitrary ROW line 1009 of the pixel element array 1006 according to a control of the timing controller 1002. In this figure, only the topmost ROW line is denoted with a reference numeral (1009) as a representative.

In the micromirror device 1001 configured in this way, display data corresponding to a desired display duration is transferred from the external control circuit not shown via the n-bit data bus line in this preferred embodiment. The n-bit data is sequentially transferred to desired COLUMN drivers 1005 via the selector 1003. Upon completion of the transfer of new data to all of COLUMN drivers 1005, the ROW line decoder 1004 drives a desired ROW line 1009 according to an instruction of the timing controller 1002.

As shown in FIG. 3, a mirror 1102, a hinge 1103 for holding the mirror 1102, electrodes (1 and 2) 1104, and memory cells (1 and 2) 1007 for controlling the mirror 1002 to be a desired deflection state are arranged in each of the pixel elements 1101 of the pixel element array 1006. Each of the memory cells 1007 has a DRAM (Dynamic Random Access Memory) structure comprising an FET transistor (FET) 1105, and a capacitor (Cap) 1106. The structure of each of the memory cells is not limited to this one. Each of the memory cells 1007 can have a memory structure such as an SRAM (Static Random Access Memory) structure, etc. Each of the memory cells 1007 is connected to an electrode 1004, a COLUMN line 1008, and a ROW line 1009. With such a configuration, each of the pixel elements 1101 modulates incident light depending on the deflection state of the mirror 1102 according to data held in each of the memory cells 1007.

A ROW line 1009 driven by the ROW line decoder 1004 turns on FET transistors 1105, which are arranged in memory cells 1007, according to a connection order depending on need. As a result, data is held in each of the memory cells 1007 according to the value of each data transferred to the COLUMN driver 1005, and a voltage according to each data is applied to the electrode 1004 connected to each of the memory cells 1007. The deflection state of the mirror 1102 is held by holding a desired voltage until data held in each of the memory cells 1007 is newly updated. To drive a different ROW line 1009 next, similar operations are repeated for the desired ROW line 1009 after all of FET transistors 1005 in the driven ROW line 1009 are turned off.

This series of operations is performed for all the ROW lines 1009 shown in FIG. 2, whereby a display according to image data is made by the micromirror device 1001.

The above described FIG. 1C discloses the SRAM structure using the inverter circuits of the plurality of transistors (M5, M6, M7, and M8). If the above described DRAM structure is used, there is no need to drive the inverter circuits. Therefore, it is necessary to arrange a transistor that can perform a switching operation, which makes the switching (ON/OFF) time of each transistor 1105 arranged in each memory cell 1007 faster than at least an allowed time for driving a memory cell 1007 arranged in each ROW line 1009 according to a minimum display duration to be described below, even if a wiring design is optimized as will be described later.

Each of the memory cells 1007 of the above described DRAM stores data by connecting one capacitor 1006 to one transistor 1105 as described above, and by storing an electric charge in the capacitor 1106. The electric charge decreases with time due to a leak current (dark current) of the connected transistor 1105. For this reason, the electric charge is lost and a malfunction of the mirror 1102 occurs unless the electric charge is periodically refilled (refreshed). Accordingly, a self-refresh must be made with a self-refresh circuit that automatically makes a refresh at optimum time intervals, if an access is not made to the DRAM for a long time. A normal DRAM does not require a self-refresh until its voltage drops to a level at which data stored in the memory is misrecognized. In the micromirror device using a micromirror like the present invention, however, a voltage must be prevented from dropping to a voltage at which the mirror cannot be held to be a desired state.

If the refresh interval is extended, or if the self-refresh is not made in a normal display duration, power consumed at the time of the self-refresh, and the scale of circuitry can be reduced. The capacitance of the DRAM is so set as to make its refresh interval longer than the longest display duration of the micromirror device, such as a display duration corresponding to MSB (Most Significant Bit) in a gray scale, whereby a display operation that does not require the self-refresh can be performed as in the preferred embodiment as will be described below.

Assuming that the micromirror device 1001 according to this preferred embodiment is implemented as a micromirror device having the resolution of XGA, pixel elements 1101 are arranged as an array of 1024 (COLUMNs)×768 (ROWs).

In recent display devices, the demand for a high resolution such as full high-definition (1920×1080 pixels: hereinafter referred to as “Full HD”) has been rising, and progress has been made toward a higher resolution.

If the micromirror device 1001 according to this preferred embodiment is implemented as a micromirror device having the resolution of Full HD, 3840(=1920*2) FET transistors 1105 must be turned on/off in the driving of 1 ROW line 1009 as is known from the structure of the pixel element 1101 shown in FIG. 3. Accordingly, data of all the memory cells 1007 in the micromirror device 10001 must be updated to display one sub-frame according to image data, namely, FET transistors 1005 of 3840 (COLUMNs)×1080 (ROWs) must be turned on/off.

In the meantime, also the demand for a higher gray scale of a display has been increasing as well as the demand for a higher resolution of a display device. There has been also an increasing demand for a higher gray scale. For example, a new I/F standard for an image display device, such as HDMI (High-Definition Multimedia Interface) 1.3, or the like was standardized to meet these demands. With HDMI 1.3, image data of 12-bit gray scale of each color can be transferred in an RGB color display.

If an RGB color display of 10 bits for each color is made with the image data by applying the micromirror device 1001 according to this preferred embodiment, for example, to a system, which is shown in the upper stage of FIG. 4, for making an RGB color display by using one micromirror device, and by switching an RGB image display in time series, the minimum display duration equivalent to the LSB (Least Significant Bit) of 10 bits for each color results in 5.43(≈1/60*1/3*1/1023) [μsec] as shown in the upper stage of FIG. 5 (based on the assumption that the display duration of one frame, and the display duration of each color are 1/60 [sec], and 1/180 [sec] respectively).

Or, if the RGB color display of 10 bits for each color is made with the image data by applying the micromirror device 1001 according to this preferred embodiment, for example, to a system, which is shown in the lower stage of FIG. 4, for making an RGB color display by using 3 micromirror devices respectively for the RGB colors, the minimum display duration equivalent to the LSB of 10 bits for each color results in 16.3(≈1/60*1/1023) [μsec] as shown in the lower stage of FIG. 5 (based on the assumption that the display duration of one frame is 1/60 [sec]).

The system shown in the upper stage of FIG. 4 is a so-called single-panel projection display system. In this system, light emitted from a light source 1201 is incident to a color filter 1203 via a condenser lens (condenser lens-1) 1202. The color filter 1203 is partitioned into 3 colors of RGB as shown in FIG. 4. The color filter of R, G or B is inserted in an optical path with the rotation of the color filter 1203, and transmits light having a wavelength according to the color filter of an inserted color. The light that passed through the color filter 1203 is incident to a TIR prism 1206 via a rod integrator 1204 and a condenser lens (condenser lens-2) 1205, and the light reflected thereby is incident to a micromirror device 1001. The light selectively reflected by the micromirror device 1001 is incident to the TIR prism 1206. The light that passed through the TIR prism 1206 is projected on a screen 1208 by a projection lens 1207. In the system having such a configuration, a duration (one frame) during which one image is displayed is divided into sub-frames, in each of which light of any of RGB is illuminated onto the micromirror device 1001, and the micromirror device 1001 sequentially displays an image corresponding to each of the colors in synchronization with the illuminated light.

In contrast, the system shown in the lower stage of FIG. 4 is a so-called multi-panel projection display system having 3 micromirror devices. In this system, light emitted from a light source 1301 is split into light rays of RGB colors by 2 dichroic mirrors 1303 and 1304 after passing through a condenser lens 1302, and incident to micromirror devices 1001 (a red light SLM 1001, a green light SLM 1001, and a blue light SLM 1001), which respectively correspond to the RGB colors. The light of B is reflected on a mirror 1305 and incident to the blue light SLM 1001. The light selectively reflected by each of the micromirror devices 1001 is projected on a screen 1307 by projection optics 1306. In the system having such a configuration, the light rays of RGB colors are respectively illuminated onto the micromirror devices 1001 during one frame period, and the micromirror devices 1001 sequentially display an image corresponding to each of the colors.

If an image display of Full HD resolution of 10 bits is made with the method for driving the pixel elements 1101, which is described with reference to FIGS. 2 and 3, for example, in the system shown in the upper stage of FIG. 4, 1080 ROW lines 1009 must be driven in the aforementioned duration of 5.43 [μsec]. Therefore, 1 ROW line 1009 must be driven in 5.03(≈5.43*10⁻⁶/1080) [nsec].

To drive the above described 3840 FET transistors 1105 in such a small time, their property significantly depends on the wiring resistance R_row[Ω] and the wiring capacity C_row[F] of each ROW line 1009, which connects FET transistors 1105, in addition to the switching properties, such as an input gate capacity (C_t), etc., of an FET transistor 1105. Therefore, it is difficult to make the image display without setting these properties in detail.

In light of these situations, this preferred embodiment proposes a method for setting the input gate capacity C_t[F] of an FET transistor 1105, and the wiring resistance R[Ω] and the wiring capacity C[F] of each memory cell 1007 in each ROW line 1009 to property values, with which a display in the minimum display duration can be made, according to the minimum display duration determined by a resolution and a gray scale in order to achieve a good balance between the resolution and the gray scale of the micromirror device 1001.

Here, the method for setting the input gate capacity C_t[F] of an FET transistor 1105, and the wiring resistance R[Ω] and the wiring capacity C[F] of each memory cell 1007 in each ROW line 1009 in order to achieve the minimum display duration τ[sec] is described.

A conceptual schematic of 1 ROW line 1009 when a memory cell 1007 has the DRAM structure shown in FIG. 3 is depicted in the upper stage of FIG. 6. When this ROW line 1009 is driven, all of FET transistors 1105, which are arranged in the ROW line 1009 in the above described way, must be driven (turned on) from the leftmost FET-1 to FET-M in FIG. 6, and voltage values according to the image data of the COLUMN lines 1008 must be sequentially charged to Cap-1 to Cap-M. The driving circuit of the ROW line 1009, which is represented as a simple equivalent circuit, is a distribution constant circuit of R_cand C_cshown in the lower stage of FIG. 6. A propagation delay time in the delay equivalent circuit is approximated with the above R_cand C_cby the following expression.

Delay time=R_c*C_c*M*(M+1)/2 [sec]

The properties of the constants R_cand C_care almost determined according to the following property values of each memory cell 1007, and M is the number of memory cells 1007 per ROW line 1009.

R_c≈R: Pattern resistance per a memory cell

C
_c≈(C+C_t)

C: Pattern capacity per a memory cell

C_t: FET Input gate capacity of a memory cell

Accordingly, the above described Delay time can be replaced with the following approximate expression.

Delay time=R*(C_t+C)*M*(M+1)/2 [sec]

As described above, in the driving of 1 ROW line 1009, image data is loaded into a new ROW line 1009 after all of FET transistors 1105 arranged in 1 ROW line are turned on, desired image data is loaded into memory cells 1007, and all the FET transistors 1105 are turned off. All of these operations are performed for all the ROW lines 1009. Accordingly, a time (1 ROW Line Data Load time) required to load data into all the memory cells 1007 in 1 ROW line 1009 is approximated as follows.

1ROW Line Data Load time=R*(C_t+C)*M*(M+1)[sec]

Accordingly, a time (All ROW Line Data Load time) required to load desired image data into all of N ROW lines 1009 is approximated as follows.

All ROW Line Data Load time=R*(C_t+C)*M*(M+1)*N[sec]

Based on the above approximate expression, the wiring resistance R[Ω] and the wiring capacity C[F] of a ROW line 1009 wired to each memory cell 1007, and the input gate capacity C_t[F] of an FET transistor 1105, which are used to achieve the minimum display duration μ[sec] equivalent to the LSB, etc. of the desired gray scale, are determined by the following relational expression (1).

τ>[R*(C_t+C)*M*(M+1)*N][sec] (1)

Accordingly, the wiring resistance R[Ω] and the wiring capacity C[F] of the ROW line 1009, and the input gate capacity C_t[F] of the FET transistor 1105 are so set as to satisfy the above relational expression (1) in the wiring design of each memory cell 1007 and ROW line 1009 in the micromirror device 1001 according to this preferred embodiment, whereby a desired gray scale can be achieved in the micromirror device 1001 having a desired resolution.

The wiring resistance R[Ω] and the wiring capacity C[F] of the ROW line 1009 have the following relationship in the semiconductor structure of each memory cell 1007. Therefore, the properties can be controlled by optimizing the following electrical resistivity [Ωm] of ROW line wiring, and relative permittivity of an inter-layer dielectric film of the ROW line wiring.

A relationship between the electrical resistivity [Ωm] and the resistance value R[Ω] of a wire having a length of L[m] and a cross-sectional area of S[m²] is as follows.

R=*(L/S)[Ωm] (2)

A relationship between the capacitance C[F] of a parallel plate, an area A[m²] of an electrode plate, and an interval 1 [m] of the electrode plate is as follows.

C=∈*(A/1)[F] (3)

where a proportional constant ∈ (epsilon) is called the permittivity of an insulator, and its unit is [F/m]. Accordingly, E varies by substance. Assuming that a vacuum permittivity is ∈₀, ∈₀=8.85*10⁻¹²[F/m] is obtained, and a relationship of ∈=∈₀*∈_rexists, in which ∈_ris the relative permittivity of a corresponding substance.

In the micromirror device 1001 according to this preferred embodiment, a material having a low electrical resistivity [Ωm] is desired to be used as a wiring material of a ROW line 1009. Normally, the electrical resistivity [Ωm] is represented with a volume resistivity ₂₀at a room temperature of 20° C. A material of Al the electrical resistivity [Ωm] of which is on the order of 2.65*10⁻⁸[Ωm], Cu, Au or Ag the electrical resistivity [Ωm] of which is low, or an alloy containing these materials is desired to be used as the wiring material of a ROW line 1009.

Additionally, in the micromirror device 1001 according to this preferred embodiment, a material having a low relative permittivity ∈_r[F/m] is preferably used as the inter-layer dielectric film of the ROW line 1009. SiO₂or SiC, the relative permittivity of which is 3.8 [F/m], can be cited as candidates of the inter-layer dielectric film. The relative permittivity can be further reduced by doping an additive. SiOF which is doped with fluorine and the relative permittivity of which is on the order of 3.6 [F/m], and SiOC which is doped with carbon and the relative permittivity of which is on the order of 2.8 [F/m] can be cited.

In the micromirror device 1001 according to this preferred embodiment shown in FIG. 2, the following wiring resistance R[Ω] and wiring capacity C[F] of a ROW line 1009, and the input gate capacity C_t[F] of an FET transistor 1105 must be set based on the above relational expression (1) in order to achieve the gray scale of 10 bits.

R*(C_t+C)<1.63*10⁻⁵/[C₀*M*N*(M+1)][ΩF] (4)

where C₀is the number of display colors of the micromirror device 1001 for making a display of the largest number of colors (for example, C₀=3 in the system shown in the upper stage of FIG. 4, and C₀=1 in the system shown in the lower stage of FIG. 4).

To achieve the resolution of Full HD by applying the micromirror device 1001 according to this preferred embodiment to the digital video system using one micromirror device shown in FIG. 1A, the above described parameters are represented by the following relational expression.

R*(C_t+C)<3.41*10⁻¹⁶[ΩF] (5)

(in the case of τ=5.43*10⁻⁶[sec], M=2*1920, N=1080)

At this time, the input gate capacity of an FET transistor of a 180-nm process is normally on the order of ten-odd [fF], and the wiring resistance of Al wiring in the same process is on the order of several tens [mΩ/m²]. Additionally, the wiring capacity is less than 1 [fF], and sufficiently smaller than the input gate capacity of the FET transistor. Moreover, the input gate capacity of the FET transistor is restricted by a wiring process.

Due to these design restrictions, it can be easily understood that the settings of the length and the cross-sectional area of a wiring pattern, which determine the wiring resistance of the wiring pattern of a ROW line 1009, are important to implement a desired property. Furthermore, since the length of the wiring pattern significantly depends on the size of a pixel element of the micromirror device 1001, namely, a mirror size, the setting of the cross-sectional area of the wiring pattern is especially important.

Accordingly, the cross-sectional area of the ROW line wiring pattern of the micromirror device of a 5 μm-square mirror size in the newest process for achieving the high resolution of the micromirror device is roughly estimated as follows (in the case where the input gate capacity of the FET transistor is 1.0 [fF]).

For Al wiring: cross-sectional area S>3.9*10⁻¹³[m²]

For Cu wiring: cross-sectional area S>2.5*10⁻³[m²]

(in the case of the electrical resistivity of Cu wiring =1.68*10⁻⁸[m]).

Additionally, the input gate capacity of the FET transistor is restricted by a wiring process as described above. Since the gate length of the FET transistor is restricted by the wiring process, the input gate capacity of the FET transistor decreases due to the fining of the wiring process, and the operating voltage of the FET transistor drops similar to the power supply voltage of a semiconductor device. Semiconductor devices manufactured with wiring processes to be described below allow the following power supply voltages. Therefore, to achieve the high resolution/high gray scale of the micromirror device 1001 according to this preferred embodiment by using the wiring process of 0.25 [m] or smaller, naturally required is a pixel element 1101 where the size of a mirror is reduced and the mirror 1102 can be driven at a voltage applied to an electrode 1104, which is equal to or lower than the operating voltage of the FET transistor 1105, when the operating voltage of the FET transistor is implemented to be equal to or lower than 3.3[V] as in the following table.

0.25
0.18
0.13
90
65

Wiring process
[um]
[um]
[um]
[nm]
[nm]

Power supply
3.3
3.3
3.3/2.5
3.3/2.5/1.8
3.3/2.5/1.8

voltage: Vd [V]

FET operating
≦Vd

voltage: Vo [V]

Furthermore, in an actual design, the tolerance voltage of the FET transistor 1105 must be determined according to the driving voltage of the mirror 1102, and an FET transistor 1105 that can be mounted within the mirror size and satisfies the required tolerance voltage must be determined. It is necessary to select an FET transistor, the tolerance voltage of which is of a voltage value that can drive and hold the mirror 1102, at a terminatory FET transistor in consideration of a voltage drop caused by the wiring resistance R[Ω] and the gate current of the FET transistor 1105. Namely, the tolerance voltage (a voltage between a drain and a source) of the FET transistor 1105 must be higher than the voltage at which the mirror is driven, and the threshold voltage (gate threshold voltage) of the FET transistor 1105 must be lower than the voltage at which the mirror is held. By way of example, for a micromirror device 1001 where the driving voltage of the mirror 1102 is 10[V], and the voltage at which the mirror 1102 is held is 5[V], an FET transistor the tolerance voltage of which is 12[V] or higher, and the threshold voltage of which is 5[V] or lower must be selected as the FET transistor 1105 to be mounted if a voltage drop of 2.0[V] is caused by the wiring resistance.

Second Preferred Embodiment

The first preferred embodiment refers to the example where all the ROW lines are sequentially driven one by one. This preferred embodiment refers to an example where a pixel element array is partitioned into subsets (groups), and data is concurrently loaded into the subsets.

FIG. 7 is a schematic showing a simplified configuration of a micromirror device according to the second preferred embodiment of the present invention.

The micromirror device 2001 shown in this figure differs from the micromirror device 1001 shown in FIG. 2 in a point that the pixel element array is partitioned into a plurality of subsets 2002 as indicated by dotted lines in FIG. 7, and in a point that 1 ROW line decoder 2003 and a plurality of COLUMN drivers 2004 are provided for each of the subsets. Each of the subsets 2002 has a memory array where a plurality of memory cells are arranged in the form of an array of Ms (COLUMNs)×Ns (ROWs).

With such a configuration, data can be concurrently loaded into the subsets 2002 by simultaneously driving 1 ROW line of each of the subsets 2002 after the data is transferred to all the COLUMN drivers 2004. Operations performed in each of the subsets 2002 are similar to those described in the aforementioned first preferred embodiment. Or, 1 ROW line of a subset 2002 may be driven at timing different from those of the other subsets 2002 by using the timing controller 1002 shown in FIG. 7. As described above, data may be simply loaded into data-loadable subsets 2002 in a sequential manner according to an image data transfer to the micromirror device 2001 as a method for driving at least one subset 2002 at different timing. Or, the loading order of data bits of the image data for each subset 2002 may be changed for each subset 2002 as a different method. If the loading order of data bits is changed, a data loading interval varies by subset 2002. Therefore, a rate required to transfer image data to the micromirror device 2001 is averaged, and a rate required to transfer the image data in a load on peripheral circuits, can be reduced. Additionally, for a projection display system to which this micromirror device 2001 is applied, there is an expectation for the effect of improving image quality for a dynamic false contour, etc., which is problematic in a boundary between subsets 2002 of the display screen of the projection display system in all of the above described methods.

As a result, the number of ROW lines to be driven in the minimum display duration (τ) described in the first preferred embodiment decreases according to the number of subsets, whereby a driving time required per ROW line can be moderated.

In the micromirror device 2001 according to this preferred embodiment, a pixel element array is partitioned into a plurality of subsets 2002, and processed. Therefore, the relational expression (4), which is described in the first preferred embodiment, is transformed into the following relational expression (6).

R*(C_t+C)<(1.63*10⁻⁵*B)/[C₀*M_s*N_s*(M_s+1)] (6)

where B is the number of subsets. For ease of explanation, this preferred embodiment assumes that the subsets 2002 include an equal number of pixel elements. However, the number of pixel elements is not limited to this one, and the subsets 2002 may include different numbers of pixel elements.

If the resolution of Full HD is achieved by applying a micromirror device, in which a pixel element array is equally partitioned into four subsets in the ROW direction, as the micromirror device 2001 according to this preferred embodiment to the digital video system using one micromirror device shown in FIG. 1A, the above described parameters are represented by the following relational expression (7).

R*(C_t+C)<2.18*10⁻¹⁴[ΩF] (7)

(in the case of τ=5.43*10⁻⁶[sec], B=4, M_s=2*1920/4, N_s=1080)

In this case, similar to the relational expression (5) described in the first preferred embodiment, the cross-sectional area of the ROW line wiring pattern of the micromirror device of a 5-μm square mirror size in the newest process for achieving the high resolution of the micromirror device is roughly estimated as follows according to the above relational expression (7) (when the input gate capacity of FET is 1.0[ff]).

For Al wiring: cross-sectional area S>6.1*10⁻¹⁵[m²]

For Cu wiring: cross-sectional area S>3.9*10⁻¹⁵[m²]

(in the case of the electrical resistivity of Cu wiring =1.68*10⁻⁸[Ωm])

In this preferred embodiment, a plurality of subsets 2002 may be obtained by partitioning a pixel element array either in the COLUMN direction or in the ROW direction, or partitioned in the COLUMN and the ROW directions respectively.

Additionally, if each ROW line of a subset 2002 is driven at timing different from those of other subsets 2002 as described above in this preferred embodiment, the timing controller 1102 shown in FIG. 7 performs a timing control for loading image data at independent timing for each subset 2002. In this case, the timing controller 1002 shown in FIG. 7 can also perform a timing control for loading image data into memory cells of adjacent pixel elements of subsets 2002 at different timings. Moreover, in this case, the selector 1003 shown in FIG. 7 distributes the bit data of image data to the subsets 2002 in different order. Or, the selector 1003 shown in FIG. 7 distributes 2 data blocks to the subsets 2002 in different order if image data has a data block that includes an oscillation state, and a data block that does not include the oscillation state.

Furthermore, if each ROW line of a subset 2002 is driven at timing different from those of other subsets 2002 as described above, in this preferred embodiment, the micromirror device 2001 can be also configured so that at least two of the subsets 2002 are driven at the same timing. In this case, for example, the subsets 2002 driven at the same timing are not adjacent in the ROW direction. Or, the micromirror device 2001 can be also configured so that at least two of the subsets 2002 are driven at different timings. In this case, for example, at least two of the subsets 2002 driven at the different timings are adjacent in the ROW direction.

The above described preferred embodiment states that the number of ROW lines to be driven in the minimum display duration (τ) is reduced by partitioning the pixel element array of the micromirror device 2001 into a plurality of subsets and by controlling the subsets, and a time required to drive each ROW line of each of the subsets 2002 is moderated. Means for moderating the minimum display duration (τ) with a method for controlling the micromirror device is described next aside from the above method.

The above described preferred embodiments refer to the embodiments where an image display is made by using a micromirror device having 2 deflection states of ON and OFF exemplified in FIG. 8 to be described later. However, also available is a micromirror device having the oscillation state of a mirror exemplified in FIGS. 11A and 11B to be described later as a deflection state of the mirror in addition to the deflection states of the mirror in two positions of ON exemplified in FIGS. 9A and 9B to be described later, and OFF exemplified in FIGS. 10A and 10B to be described later. If the micromirror device having these deflection states is used, the quantity of reflection light deflected to the projection optics per unit time becomes smaller in the oscillation state of the mirror than that in the ON state of the mirror. Therefore, the minimum display duration (τ) when the same gray scale display is made by using the oscillation state of the mirror increases according to the proportion of the quantity of reflection light in the ON state of the mirror, whereby the time required to drive each ROW line can be moderated. Accordingly, if the oscillation state, which corresponds to the minimum display duration (τ) equal to that in the ON state, is applied to the micromirror device according to each of the above described preferred embodiments, a higher gray scale display can be achieved as a matter of course.

The micromirror device according to each of the above described preferred embodiments has a structure where each pixel element comprises a mirror 3003, which is supported to be freely tiltable on a substrate 3001 via a hinge 3002, as exemplified in FIG. 8.

An OFF electrode 3004, an OFF stopper 3005, an ON electrode 3006, and an ON stopper 3007 are arranged in positions symmetrical with respect to the hinge 3002 on the substrate 3001.

The OFF electrode 3004 sucks the mirror 3003 with coulomb force by being applied with a predetermined potential, and tilts the mirror 3003 to a position at which the mirror touches the OFF stopper 3005. As a result, light incident to the mirror 3003 is reflected to the optical path of an OFF position that deviates from the optical axis of the projection optics.

In contrast, the ON electrode 3006 sucks the mirror 3003 with coulomb force by being applied with a predetermined potential, and tilts the mirror 3003 to a position at which the mirror touches the ON stopper 3007. As a result, light incident to the mirror 3003 is reflected to the optical path of an ON position, which matches the optical axis of the projection optics.

The OFF capacitor (Cap-1, 1106) exemplified in FIG. 3 is connected to the OFF electrode 3004, and further connected to COLUMN and ROW lines via a transistor. In the meantime, the ON capacitor (Cap-2, 1106) also exemplified in FIG. 3 is connected to the ON electrode 3006, and further connected to COLUMN and ROW lines via a transistor.

Here, ON/OFF of a transistor is controlled by a ROW line.

Namely, the deflection state (ON/OFF state) of the mirror of each pixel element in a ROW line is individually controlled by simultaneously selecting a series of pixel elements in an arbitrary ROW line, and by controlling an electric charge/discharge to/from the OFF and the ON capacitors by COLUMN and ROW lines.

In the meantime, in the above described oscillation state, an electric charge stored in the ON and the OFF capacitors is discharged from a pixel element deflected to the ON or the OFF state in the pixel element structure shown in FIG. 3. As a result, coulomb force that occurs between the mirror 3003 and the electrode 3006 or 3004 disappears, and the mirror 3003 starts moving toward the opposing ON stopper 3007 or OFF stopper 3005 with spring force stored in the hinge 3002, and reaches the opposing stopper. Thereafter, since a predetermined potential (V_a) is not applied also to the opposing electrode 3004 or 3006, the mirror 3003 repeats the above described operations to perform oscillation operations exemplified in FIGS. 11A and 11B to be described later.

To terminate the oscillation state, the above described control for the ON or the OFF state may be performed.

Furthermore, the micromirror device according to each of the above described preferred embodiments may be configured so that each pixel element has a structure where an electrode itself servers as a stopper as exemplified in FIGS. 9A, 10A, 11A, and 12A, and this micromirror device can be applied to a projection display device. In this pixel element, a hinge electrode 4002, and two address electrodes 4003 and 4004 are provided on the top of a substrate 4001, and each of the electrodes is covered with a dielectric layer 4005. An elastic hinge 4006 penetrates through the dielectric layer 4005 and is connected to the hinge electrode 4002, and a mirror 4007 is supported to be freely tiltable via the elastic hinge 4006. Note that the hinge electrode 4002 is grounded.

Similar to the above described pixel element exemplified in FIG. 8, the ON capacitor (Cap-2) exemplified in FIG. 3 is connected to the address electrode 4003, the OFF capacitor (Cap-1) also exemplified in FIG. 3 is connected to the address electrode 4004, and the address electrodes are respectively connected to COLUMN and ROW lines via transistors. The deflection state of the mirror of each pixel element is individually controlled as described above.

To control the mirror 4007 to be ON in the pixel element having such a configuration, a signal (0,1) is applied to the pixel element. Then, a voltage of V_a[V] is applied to the address electrode 4003, and a voltage of 0[V] is applied to the address electrode 4004 as exemplified in FIG. 9A. As a result, the mirror 4007 is sucked with coulomb force in the direction of the address electrode 4003 to which the voltage of V_a[V] is applied, and tilts to a position at which the mirror touches the dielectric layer 4005 of the address electrode 4003. As a result, incident light is reflected (deflected) toward the projection optical path by the mirror 4007. FIG. 9B shows the state of a change in the quantity of reflection light to the projection optics when the mirror 4007 is controlled to be ON in this way.

To control the mirror 4007 to be OFF, a signal (1,0) is applied to the pixel element. Then, the voltage of V_a[V] is applied to the address electrode 4004, and the voltage of 0[V] is applied to the address electrode 4003 as exemplified in FIG. 10A. As a result, the mirror 4007 is sucked with coulomb force in the direction of the address electrode 4004 to which the voltage of V_a[V] is applied, and tilts to a position at which the mirror touches the dielectric layer 4005 of the address electrode 4004. As a result, incident light is reflected (deflected) to a direction different from the projection optical path by the mirror 4007. FIG. 10B shows the state of a change in the quantity of reflection light to the projection optics when the mirror 4007 is controlled to be OFF in this way.

To control the oscillation of the mirror 4007, a signal (0,0) is applied to the pixel element when the mirror 4007 is in the OFF state. Then, the voltage of 0[V] is applied to both of the address electrodes 4004 and 4003 as exemplified in FIG. 11A. As a result, coulomb force that occurs between the mirror 4007 and the address electrode 4004 disappears, and the mirror 4007 starts oscillating freely according to the property of the elastic hinge 4006. As a result, incident light is reflected (deflected) by the mirror 4007 while traveling between the projection optical path and a direction different from the projection optical path. Additionally, the oscillation of the mirror 4007 can be controlled also by performing a similar operation when the mirror 4007 in the ON state. FIG. 11B shows the state of a change in the quantity of reflection light to the projection optics when the oscillation of the mirror 4007 is controlled during a predetermined duration from the OFF state. It can be easily understood from this state that the quantity of reflection light to the projection optics per unit time decreases.

FIG. 12A shows the operating state of the mirror 4007 when the voltage applied to the address electrode 4004 is set not to 0[V] but to V_b[V] in the oscillation state described with reference to FIGS. 11A and 11B. Note that, however, V_b[V] is a voltage lower than V_a[V], and is of a voltage value that cannot hold the mirror 4007 to be the OFF state. Therefore, the mirror 4007 does not deflect to the angle of the ON state, and performs the oscillation operation in an angular range according to the applied voltage V_b[V]. FIG. 12 shows the state of a change in the quantity of reflection light to the projection optics when the oscillation operation of the mirror 4007 is performed in this way. With such a control method, the quantity of reflection light to the projection optics can be arbitrarily changed in the oscillation state per unit time.

The above described control using the oscillation state of the pixel element can be performed only by applying the aforementioned oscillation control to a pixel element structure similar to the pixel element having the two deflection states such as the ON and the OFF states. Or, both pulse width modulation using the ON and the OFF states, and the control using the oscillation state can be utilized together.

Additionally, in the above described preferred embodiments, the relational expressions (4) and (6) are effective also when a gray scale display of 10 [bits] or more for each color is made with a color sequential display of C₀colors.

Furthermore, in the above described preferred embodiments, the micromirror device can be also configured to comprise pixel elements of 1920×1080 [pixels] or more. In this case, the cross-sectional area of a ROW line may be equal to or larger than 6.1*10⁻¹⁵[m²]. Moreover, in this case, the electrical resistivity () of the material of a ROW line may be equal to or smaller than 2.65*10⁻⁸[Ωm].

Still further, in the above described preferred embodiments, the micromirror device can be also configured so that the pitch or the size of a mirror is equal to or larger than 4 [m] and equal to or smaller than 10 [m]. In this case, the cross-sectional area of a ROW line may be equal to or larger than 3.9*10⁻¹⁵[m²]. Moreover, in this case, the electrical resistivity (Q) of the material of a ROW line may be equal to or smaller than 1.68*10⁻⁸[m].

Still further, in the above described preferred embodiments, the micromirror device can be also configured so that the relative permittivity (∈_r) of the inter-layer dielectric film of a ROW line is equal to or smaller than 3.8 [F/m].

Still further, in the above described preferred embodiments, the relational expressions (4) and (6) can be also represented as the following relational expression (8) if a gray scale display of G_s[bits] for each color is made with a color sequential display of C₀colors. Note that B is the number of subsets. For example, the relational expression (4) can be represented as the relational expression (8) in the case of B=1.

R*(C_t+C)<B*[60*C₀*(2^Gs−1)*M_s*N_s*(M_s+1)]⁻¹ (8)

Still further, the relational expression (1) described in the first preferred embodiment can be also represented as the following relational expression (9) in the second preferred embodiment.

τ>[R*(C_t+C)*M_s*(M_s+1)*N_s] (9)

Still further, the relational expression (1) described in the first preferred embodiment also represents that the total value of the propagation delay time of a ROW line 1009, which connects all of FET transistors 1105 of memory cells 1007 arranged successively in the ROW direction, and the switching time of each FET transistor 1105 is smaller than the driving interval of the ROW line 1009 driven in the minimum display duration τ of the micromirror device 1001. In this case, the switching time of an FET transistor 1105 is the total value of the turn-on time and the turn-off time of the FET transistor 1105. Moreover, the minimum display duration τ is a display duration corresponding to the LSB (Least Significant Bit) in the gray scale of the micromirror device 1001.

Still further, the relational expression (6) described in the second preferred embodiment also represents that the total value of the propagation delay time of a ROW line 1009, which connects all of FET transistors 1105 of memory cells 1007 arranged successively in the ROW direction, and the switching time of each FET transistor 1105 in each subset 2002 is smaller than the driving interval of the ROW line 1009 driven in the minimum display duration τ of the micromirror device 2001. In this case, the switching time of an FET transistor is the total value of the turn-on time and the turn-off time of the FET transistor. Moreover, the minimum display duration τ is a display duration corresponding to the LSB (Least Significant Bit) in the gray scale of the micromirror device 2001.

Still further, in the first preferred embodiment, a ROW line 1009 has a voltage drop property of applying a voltage, which is higher than the gate threshold voltage of an FET transistor 1105, to the gate terminals of all of FET transistors 1105 in the ROW line 1009. In contrast, a COLUMN line 1008 has a voltage drop property of applying a voltage, which is equal to or higher than the driving voltage of a mirror 1102, to the source nodes of all of FET transistors 1105 in the COLUMN line 1008.

Still further, in the first preferred embodiment, image data is loaded with a voltage at which a pixel element 1101 can hold a deflection state over the maximum display duration of the micromirror device 1001 in all of FET transistors connected to each ROW line 1009.

Still further, in the second preferred embodiment, image data is loaded with a voltage at which a pixel element can hold a desired deflection state over the maximum display duration of the micromirror device 2001 in all of FET transistors connected to each ROW line 1009 in each subset 2002.

Still further, in the first and the second preferred embodiments, image data is loaded at a time interval during which the voltage of an electrode connected to each FET transistor 1105 can hold the deflection state of a pixel element 1101. Here, the time interval during which the deflection state can be held is the display duration, which corresponds to the MSB (Most Significant Bit) in the gray scale of the micromirror device 1001, or longer. Moreover, the loading interval of image data is longer than the oscillation period when the oscillation of a mirror 1102 is controlled.

Up to this point, the present invention has been described in detail. The present invention is not limited to the above described preferred embodiments, and various improvements and modifications can be made within the scope that does not depart from the gist of the present invention as a matter of course.

As described above, according to the present invention, the wiring resistance and the wiring capacity of a ROW line, and the input gate capacity of an FET transistor are so set as to satisfy the above described relational expressions (1) and (4) in the wiring design of each memory cell and ROW line in a micromirror device, whereby a desired display gray scan can be achieved in the micromirror device having a desired resolution.

Additionally, according to the present invention, a micromirror device is configured so that a pixel element array is partitioned into a plurality of subsets, and data is concurrently loaded into the subsets, whereby a time required to drive each ROW line can be moderated.

Furthermore, according to the present invention, the control of an oscillation state is applied to a pixel element array, whereby a driving time required per ROW line can be moderated.

Deformable micromirror device

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CPC

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