DELAY ALIGNMENT IN A CLOSED LOOP TWO-POINT MODULATION ALL DIGITAL PHASE LOCKED LOOP

Abstract

A novel apparatus for and method of delay alignment in a closed loop two-point modulation all digital phase locked loop (ADPLL). The invention provides a fully digital delay alignment mechanism where better than nanosecond alignment is achieved by accounting for processing delays in the digital circuit modules of the transmitter and by the use of programmable delay elements spread across several clock domains. Tapped delay lines compensate for propagation and settling delays in analog elements such as the DCO, dividers, quad switch, buffers, level shifters and digital pre-power amplifier (DPA). A signal correlative mechanism is provided whereby data from the amplitude and phase/frequency modulation paths to be matched is first interpolated and then cross-correlated to achieve accuracy better than the clock domain of comparison. Within the ADPLL portion of the transmitter, precise alignment of reference and direct point injection points in the ADPLL is provided using multiple clock domains, tapped delay lines and clock adjustment circuits.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

The invention is herein described, by way of example only, with reference to the accompanying drawings, wherein:

FIG. 1 is a block diagram illustrating a prior art complex polar modulator with direct phase and amplitude modulation;

FIG. 2 is a block diagram illustrating a single chip polar transceiver radio incorporating an all-digital local oscillator based transmitter and receiver;

FIG. 3 is a block diagram illustrating a single chip polar transmitter based on a DCO and digitally controlled power amplifier (DPA) circuits;

FIG. 4 is a diagram illustrating spectral replicas of a modulating signal and associated filtering through a zero-order hold;

FIG. 5 is a block diagram illustrating the amplitude and phase modulation paths of the polar transmitter;

FIG. 6 is a graph illustrating the effect of misalignment between amplitude and phase on several points of the EDGE spectrum;

FIG. 7 is a graph illustrating the effect of misalignment between amplitude and phase on the EDGE spectrum for several different time mismatch delays;

FIG. 8 is a graph illustrating the degradation in EVM for WCDMA as a function of time mismatch between amplitude and phase modulation paths;

FIG. 9 is a graph illustrating the degradation in ACLR for WCDMA as a function of time mismatch between amplitude and phase modulation paths;

FIG. 10 is a graph illustrating the degradation in ACLR for WCDMA as a function of time mismatch between amplitude integer and fractional bits;

FIG. 11 is a graph illustrating the degradation in EVM for WCDMA as a function of time mismatch between amplitude integer and fractional bits;

FIG. 12 is a graph illustrating the degradation in EVM for WCDMA as a function of time mismatch between phase integer and fractional bits;

FIG. 13 is a graph illustrating the degradation in ACLR for WCDMA as a function of time mismatch between phase integer and fractional bits;

FIG. 14 is a graph illustrating TX spectral noise contribution degradation in the corresponding RX band for WCDMA as a function of time mismatch between phase integer and fractional bits;

FIG. 15 is a block diagram illustrating a digital delay adjustment block in accordance with the present invention for a signal propagating from a slow clock domain to a fast clock domain;

FIG. 16 is a block diagram illustrating a digital delay adjustment block in accordance with the present invention for a signal propagating from a fast clock domain to a slow clock domain;

FIGS. 17A and 17B are a block diagram illustrating a first embodiment of a WCDMA transmitter having precise delay alignment between amplitude and frequency modulation paths;

FIG. 18 is a block diagram illustrating a tapped delay line in accordance with the present invention;

FIGS. 19A and 19B are a block diagram illustrating a second embodiment of a WCDMA transmitter having precise delay alignment between frequency and amplitude modulation;

FIG. 20 is a block diagram illustrating a first generation ADPLL based DRP transmitter;

FIG. 21 is a block diagram illustrating the phase modulation path in a first generation ADPLL based DRP transmitter;

FIG. 22 is a block diagram illustrating the phase modulation path in a second generation ADPLL based DRP transmitter;

FIG. 23 is a block diagram illustrating the phase modulation path in a third generation ADPLL based DRP transmitter;

FIG. 24 is a block diagram illustrating an ADPLL with direct point injection and reference point injection rates of different clock domains;

FIG. 25A is a graph illustrating the use of multi-rate correlation determined using analytic clock alignment for the alignment of direct and reference point injections; and

FIG. 25B is a graph illustrating the use of multi-rate correlation determined using correlative measures to tune multiple clock domain delays for the alignment of direct and reference point injections.

Claims

1. A method of aligning two-point data modulation injection in a digital phase locked loop (DPLL), said method comprising the steps of: first utilizing a reference clock domain for reference point injection of modulation data into said loop;second utilizing a direct clock reference clock domain for direct point injection of said modulation data into said loop; andaligning said reference clock domain with and said direct clock domain in the reference clock domain utilizing interpolative correlation to precisely tune delay adjustments associated with said reference point injection and said direct point injection resulting in the alignment of both said reference clock domain and said direct clock domain.

2. The method according to claim 1, wherein said step of aligning comprises the step of third utilizing a delay adjustment module operative to use two different clock domains to control the delay in a reference point modulation data signal path.

3. The method according to claim 1, wherein said interpolative correlation comprises the steps of: computing the cross-correlation between with said reference point injection signal as start point and said direct point injection signal as end point to yield an absolute delay for each signal; anddelay matching the delays computed for each path to the time resolutions available within said DPLL.

4. The method according to claim 1, wherein said interpolative correlation comprises the steps of: computing the cross-correlation between with said reference point injection signal as start point and said direct point injection signal as end point to yield an absolute time delay for each signal; andconfiguring one or more delay elements in the coarse clock domain in accordance with said computed absolute time delays.

5. The method according to claim 4, wherein said cross-correlation is performed starting from the coarsest time delay and in steps up to the finest clock domain.

6. The method according to claim 1, wherein said interpolative correlation comprises the steps of: computing the cross-correlation between with said reference point injection signal as start point and said direct point injection signal as end point to yield an absolute time delay for each signal; andtruncating the results of said cross-correlation; anddelay matching each signal path to the time resolution available in a corresponding path in accordance with said computed absolute time delays.

7. An apparatus for delay alignment of two-point data modulation injection in an all-digital phase locked loop (ADPLL), comprising: direct injection means adapted to inject modulation data samples into said loop at a data clock rate derived from a digital controlled oscillator (DCO) output clock;a digital delay adjustment module adapted to generate adjusted modulation data samples at an intermediate clock rate higher than and derived from said data clock rate;a sample rate converter operative to generate reference modulation data samples at a reference clock rate from said adjusted modulation data samples;reference point injection means adapted to be clocked at said reference clock rate.

8. The apparatus according to claim, 7, wherein said digital delay adjustment module comprises means for using two different clock domains to control the delay in the modulation data signal path.

9. The apparatus according to claim 7, wherein said digital delay adjustment module comprises: a first plurality of delay elements clocked at a first clock domain;a second plurality of delay elements clocked at a second clock domain; anda second sample rate converter operative to convert between said first clock domain and said second clock domain.

10. The apparatus according to claim 9, wherein said second sample rate converter is operative to perform interpolation when said first clock domain is slower than said second clock domain.

11. The apparatus according to claim 9, wherein said second sample rate converter is operative to perform decimation when said first clock domain is faster than said second clock domain.

12. A apparatus for alignment of two-point data modulation injection in a digital phase locked loop (DPLL), comprising: a reference clock domain for reference point injection of modulation data into said loop;a direct clock reference clock domain for direct point injection of said modulation data into said loop; anddelay alignment means for aligning said reference clock domain with and said direct clock domain in the reference clock domain utilizing interpolative correlation means to precisely tune delay adjustments associated with said reference point injection and said direct point injection resulting in the alignment of both said reference clock domain and said direct clock domain.

13. The apparatus according to claim 12, wherein said delay alignment means comprises a delay adjustment means for controlling the delay in a reference point modulation data signal path utilizing a reference point injection clock domain and a direct point injection clock domain.

14. The apparatus according to claim 12, wherein said interpolative correlation means comprises: means for computing the cross-correlation between with said reference point injection signal as start point and said direct point injection signal as end point to yield an absolute delay for each signal; andmeans for delay matching the delays computed for each path to the time resolutions available within said DPLL.

15. The apparatus according to claim 12, wherein said interpolative correlation means comprises: means for computing the cross-correlation between with said reference point injection signal as start point and said direct point injection signal as end point to yield an absolute delay for each signal;means for truncating the results of said cross-correlation;means for configuring one or more delay elements in the coarse clock domain in accordance with said computed absolute delays.

16. A polar transmitter, comprising: means for splitting transmit data into amplitude modulation data and phase modulation data;an amplitude modulation circuit operative to generate an amplitude signal in accordance with said amplitude modulation data;a frequency synthesizer comprising a digital phase locked loop (DPLL), said DPLL comprising reference point modulation injection and a direct point modulation injection and operative to generate a carrier signal in accordance with said phase modulation data; andmeans for utilizing different signal sampling rates for said reference point modulation injection and said direct point modulation injection.