1. Technical Field
The present disclosure relates to an electronic device with a delay circuit.
2. Description of Related Art
A DVD player for playing disc provides a function for recording a position to replay the disc from the recording position. The DVD player includes a processor for executing different functions in response to different instructions. When receiving a power-off instruction, the processor delays executing the power-off instruction for a predetermined time and record the location or position the disc was last read, such that the DVD player can play the disc from the recorded position the next time the disc is being played. However, the delay function is executed by the processor, if a program error occur in the processor, thus the recorded position may be missed or never recorded.
Therefore, there is room for improvement in the art.
Many aspects of the embodiments can be better understood with reference to the following drawings. The components in the drawings are not necessarily drawn to scale, the emphasis instead being placed upon clearly illustrating the principles of the electronic device and energy efficiency indicating method thereof Moreover, in the drawings, like reference numerals designate corresponding parts throughout the several views.
In general, the word “module,” as used herein, refers to logic embodied in hardware or firmware, or to a collection of software instructions, written in a programming language, for example, Java, C, or assembly. One or more software instructions in the modules may be embedded in firmware, such as in an EPROM. Modules may comprise connected logic units, such as gates and flip-flops, and may comprise programmable units, such as programmable gate arrays or processors. The modules described herein may be implemented as either software and/or hardware modules and may be stored in any type of computer-readable medium or other computer storage system. Embodiments of the present disclosure will be described with reference to the drawings.
The electronic device 100 includes a processor 10, a delay circuit 20, a storage 60, and a display module 80.
The processor 10 connects between the delay circuit 20 and the storage 60. The processor 10 is capable of executing different functions.
The delay circuit 20 comprises an operation module 21, a delay module 23.
The operation module 21 is connected between the power supply 200 and the delay module 23. The operation module 21 establishes a connection between the power supply 200 and the delay module 23 if not receiving a power-off instruction, thus the voltage of the power supply 200 powers the processor 10. The operation module 21 further cuts off the connection between the power supply 200 and the delay module 23, and generates a record signal when receiving the power-off instruction. In the embodiment, the power-off instruction is generated by pressing a key.
The delay module 23 outputs a working voltage to the processor 10 when the operation unit 21 cuts off the connection between the power supply 200 and the delay module 23, and further stops outputting the working voltage after the predetermined interval.
The processor 10 is powered by the working voltage and executes a recording function for recording a current position of the playing video file in the storage 60 in response to the record signal, and further executes a power-off function if not receiving the voltage from the power supply 200 or the working voltage from the delay circuit 30.
The storage 60 stores the current position of the playing video file. In the embodiment, the storage 60 is an electrically erasable programmable read-only memory (EEPROM).
The display module 80 connects with the processor 10, and includes a number of parameters. In the embodiments, the parameters include brightness and resolution ratio of the playing video, for example.
The processor 10 further records the parameters of the display module 80 in the storage 60 in response to the record signal.
The delay circuit 20 further includes a triggering module 25. The triggering module 25 connects between the delay circuit 30 and the processor 10. The processor 10 further generates a triggering signal when the recording function is completed. The triggering module 25 controls the delay module 23 to stop outputting the working voltage in response to the triggering signal. In the embodiment, the triggering signal is a logic high level signal.
The triggering module 25 includes a transistor Q1, a third resistor R3, a fourth resistor R4, and a fifth resistor R5. A base of the transistor Q1 is connected to the processor 10 through the fourth resistor R4. An emitter of the transistor Q1 is grounded. A collector of the transistor Q1 is connected to the cathode of the first diode D1 through the third resistor R3. Opposite terminals of the fifth resistor are respectively connected to the base of the transistor Q1 and the ground. In the embodiment, the transistor is an npn type bipolar junction transistor.
The working principle of the electronic device 100 is described as below, if not receiving the power-off instruction, the operation module 21 outputs the voltage of power supply 200. The voltage provided by the power supply 200 charges the capacitor C1. The voltage provided by the power supply 200 powers the processor 10.
When receiving the power-off instruction, the operation module 21 outputs the record signal to the processor 10. The capacitor C1 discharges through the first resistor R1 and the second resistor R2 to output a working voltage to the processor 10. The predetermined interval is calculated by the following equation: T=C1*(R1+R2). The processor 10 is powered by the working voltage and records the current position of the playing video file to store in the storage 60. When the processor 10 finishes the storing process, the first pin P1 outputs a logic high level signal. The voltage difference between the base and the emitter of the transistor Q1 is more than 0V, the transistor Q1 turns on. The capacitor C1 discharges through the first resistor R1, the second resistor R2, and the third resistor R3 for speeding up the discharging process of the first capacitor C1.
In use, the electronic device 100 executes the delay function through hardware elements and generates a triggering signal to end the delay function before the predetermined time arrives. Therefore, the efficiency of the delay function of the electronic device 100 is improved.
While various exemplary embodiments have been described, the disclosure is not to be limited thereto. Various modifications and similar arrangements (as would be apparent to those skilled in the art) are also intended to be covered. Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.
Number | Date | Country | Kind |
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2013101305869 | Apr 2013 | CN | national |