Claims
- 1. A semiconductor integrated circuit for transmitting a signal from an input terminal to an output terminal providing a predetermined stable delay for one level transition of said input signal and no delay for the other level transition of said input signal, comprising:
- said input terminal for receiving said input signal and said output terminal for generating an output signal;
- a first inverter having an input terminal connected to said input terminal of said integrated circuit and having an output terminal;
- a second inverter having an input terminal connected to said output terminal of said first inverter means and having an output terminal;
- a first NAND gate having a first input terminal connected to said output terminal of said second inverter, a second input terminal connected to said input terminal of said integrated circuit, and an output terminal;
- a NOR gate having a first input terminal connected to said output terminal of said inverter, a second input terminal connected to said output terminal of said first NAND gate, and an output terminal; and
- a second NAND gate having a first input terminal connected to said input terminal of said integrated circuit, a second input terminal connected to said output terminal of said NOR gate, and an output terminal connected to said output terminal of said integrated circuit.
Priority Claims (1)
Number |
Date |
Country |
Kind |
61-233446 |
Oct 1986 |
JPX |
|
Parent Case Info
This is a continuation of now-abandoned application Ser. No. 07,102,647, filed Sept. 30, 1987.
US Referenced Citations (14)
Foreign Referenced Citations (7)
Number |
Date |
Country |
0220474 |
Mar 1985 |
DDX |
0114018 |
Sep 1980 |
JPX |
0011526 |
Jan 1982 |
JPX |
0111429 |
Jul 1983 |
JPX |
61-104397 |
May 1986 |
JPX |
0208919 |
Sep 1986 |
JPX |
0129863 |
Oct 1988 |
JPX |
Continuation in Parts (1)
|
Number |
Date |
Country |
Parent |
102647 |
Sep 1987 |
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