Patent Application
20180091127
The invention relates to a delay circuit, and more particularly, to a delay circuit for determining delay time according to a rising slope and a falling slope of a delay control signal.
A delay circuit is a circuit which is capable of delaying an input signal by a specific time to generate an output signal. Thus, after a signal is input to a delay circuit, there is a delay of a specific time between a delayed signal output from the delay circuit and the input signal. In recent years, with the improvement in manufacturing process techniques, the operation speed of system circuits has become higher, and the number of circuits integrated into one chip has increased. Thus, clock synchronization between circuits has become more important. Clock skew is a main factor for determining system performance, especially in a high-speed system. Delay circuits are widely applied for eliminating the clock skew. In current delay circuits, the expected delay time may be achieved by increasing the number of capacitive and resistive elements or the number of inverters. However, the increase in the number of elements in the delay circuit causes an increase in the area of the entire circuit.
An exemplary embodiment of a delay circuit is provided. The delay circuit comprises a voltage-generation circuit and a signal-generation circuit. The voltage-generation circuit receives an input signal and generates a first control voltage and a second control voltage. The signal-generation circuit is controlled by the first control voltage and a second control voltage to generate an output signal. A first delay time by which a falling edge of the output signal is delayed from a falling edge of the output signal is determined by the first control voltage. A second delay time by which a rising edge of the output signal is delayed from a rising edge of the output signal is determined by the second control voltage.
Another exemplary embodiment of a delay circuit is provided. The delay circuit comprises a first P type-transistor, a first N-type transistor, a second P-type transistor, a second N-type transistor, and an inverter. The first P type-transistor has a gate receiving a first low operation voltage, a source receiving an input signal, and a drain coupled to a first node. The first N-type transistor has a gate receiving a first high operation voltage, a drain receiving the input signal, and a source coupled to a second node. The second P-type transistor has a gate coupled to the first node, a source coupled to a second high operation voltage, and a drain coupled to a third node. The second N-type transistor has a gate coupled to the second node, a drain coupled to the third node, and a source coupled to a second low operation voltage. The inverter is coupled to the third node. The inverter generates an output signal delayed from the input signal. The first P-type transistor and the first N-type transistor are turned on simultaneously.
A detailed description is given in the following embodiments with reference to the accompanying drawings.
The invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein:
To better understand the technical aspects of the present invention, the following embodiments of the invention will be described in detail by referring to the drawings.
The voltage-generation circuit 10 receives the input signal IN of the delay circuit 1. The voltage-generation circuit 10 generates control voltages V10 and V11 and provides the control voltages V10 and V22 to the nodes N10 and N11 respectively. When the level of the input signal IN switches to the high level from the low level, the control voltage V10 generated by the voltage-generation circuit 10 turns off the PMOS transistor 110. At the same time, when the level of the input signal IN switches to the high level from the low level, the voltage-generation circuit 10 also generates the control voltage V11 to the node N11. In the embodiment, the control voltage V11 which is generated by the voltage-generation circuit 10 in this case has a high level, however the control voltage V11 cannot turn on the NMOS transistor 111 completely. Thus, a voltage level of a delay control signal S10 at the node N12 cannot drop to the level of the operation voltage VSS from the level of the operation voltage VDD immediately. In this case, the voltage level of the delay control signal S10 drops to the level of the operation voltage VSS from the level of the operation voltage VDD gradually by a falling slope. In the embodiment, the falling slope is determined by the control voltage V11. In detail, the falling slope is determined by the control voltage V11 which is generated by the voltage-generation circuit 10 when the level of the input signal IN switches to the high level from the low level. The inverter 112 is coupled to the node N12 to receive the delay control signal S12. As described above, the level of the delay control signal S12 drops gradually. Thus, when the level of the delay control signal S12 drops to a threshold level, the inverter 112 switches the output signal OUT to be the high level.
When the level of the input signal IN switches to the low level from the high level, the control voltage V11 generated by the voltage-generation circuit 10 turns off the NMOS transistor 111. At the same time, when the level of the input signal IN switches to the low level from the high level, the voltage-generation circuit 10 also generates the control voltage V10 to the node N10. In the embodiment, the control voltage V10 which is generated by the voltage-generation circuit 10 in this case has a low level, however the control voltage V10 cannot turn on the PMOS transistor 110 completely. Thus, the voltage level of the delay control signal S10 at the node N12 cannot rise to the level of the operation voltage VDD from the level of the operation voltage VSS immediately. In this case, the voltage level of the delay control signal S10 rises to the level of the operation voltage VDD from the level of the operation voltage VSS gradually by a rising slope. In the embodiment, the rising slope is determined by the control voltage V10. In detail, the rising slope is determined by the control voltage V10 which is generated by the voltage-generation circuit 10 when the level of the input signal IN switches to the low level from the high level. The inverter 112 is coupled to the node N12 to receive the delay control signal S12. As described above, the level of the delay control signal S12 rises gradually. Thus, when the level of the delay control signal S12 rises to a threshold level, the inverter 112 switches the output signal OUT to be the low level.
According to the above embodiment, the delay control signal S12 gradually drops/rises with the level switching of the input signal IN, so that the rising edge of the output signal OUT is delayed from the rising edge of the input signal IN, and the falling edge of the output signal OUT is delayed from the falling edge of the input signal IN. Moreover, the falling slope of the delay control signal S12 is determined by the control voltage V11, and the rising slope thereof is determined by the control signal V10. Thus, the rising delay time by which the rising edge of the output signal OUT is delayed from the rising edge of the input signal IN is determined by the control voltage V11, while the falling delay time by which the falling edge of the output signal OUT is delayed from the falling edge of the input signal IN is determined by the control voltage V10. Compared with conventional delay circuits, the delay circuit 1 of the embodiment achieves the target delay time without increasing the number of capacitive and resistive elements or the number of inverters. According to the operation of the delay circuit 1, the falling slope and the rising slope of the delay control signal S12 are changed only by adjusting the control voltages V10 and V11, thereby changing the rising delay time and the falling delay time between the output signal OUT and input signal IN. In an embodiment, the rising delay time is equal to the falling delay time.
In an embodiment, the boost element 100 comprises a PMOS transistor 20, while the buck element 101 comprises an NMOS transistor 21. The gate of the PMOS transistor 20 is coupled to the operation voltage VSS, the source thereof receives the input signal IN, and the drain thereof receives the node N10. The gate of the NMOS transistor 21 is coupled to the operation voltage VDD, the drain thereof receives the input signal IN, and the source thereof receives the node N11. Based on the structure of the boost element 100 and the buck element 101, the PMOS transistor 20 and the NMOS transistor 21 are continuously turned on when the delay circuit 1 is powered on. In other words, the PMOS transistor 20 and the NMOS transistor 21 are turned on simultaneously.
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According to the above embodiments, the delay control signal S12 gradually drops/rises with the level switching of the input signal IN, so that the rising edge of the output signal OUT is delayed from the rising edge of the input signal IN, and the falling edge of the output signal OUT is delayed from the falling edge of the input signal IN. Moreover, the falling slope of the delay control signal S12 is determined by the control voltage V11, and the rising slope thereof is determined by the control signal V10. Thus, the rising delay time DT30 (shown in
In an embodiment, the operation voltage coupled to the boost element 100 is different from the operation voltage VSS, and/or and the operation voltage coupled to the buck element 101 is different from the operation voltage VDD. Referring to
While the invention has been described by way of example and in terms of the preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.
