Patent Application
20110121797
This invention relates to power supplies and in particular to DC-DC converters for use in power supplies.
Much electrical equipment, and in particular the majority of modern electronic equipment, operates from a direct current (DC) power supply. However, at least as far as permanent electrical supplies are concerned, the vast majority of fixed power for use by at least domestic users is in the form of an alternating current (AC) supply which is delivered to the household or home at a nominal voltage, which, depending on geographical location, is typically at 110V, 220V, 240V. Thus there is a large demand for electrical power converters which can convert from an AC mains supply to a DC form of electrical power.
Moreover, for electrical or electronic equipment which is powered from a DC supply, it is becoming increasingly more frequent that the equipment utilises the variety of DC voltage levels. Thus, a personal computer may have a DC power supply at 24V, and yet include some systems or components which operate at 24V, 12v, or 5V. As further examples, personal mobile equipment such as PDAs or mobile telephones may operate from a battery supplying a fixed voltage of 4.8V, and yet include circuitry or integrated circuits (IC) which operates from different voltages such as 1.7V or 3.3V. A example personal computer chip Greenchip™, available from NXP Semiconductors, supplies each of 12V, 5V and 3.3V. Mobile Flash typically require between 3.5V to 4V. Hysteretic buck converter LED driver ICs such as the Coala TM chip also from NXP Semiconductors provides outputs ranging from 6V to 22V, from a 24V design input.
In order to deliver DC voltages which are different from the supplied DC voltage, DC-DC converters are commonly used.
An example of a DC-DC converter is the hysteretic converter. A hysteretic DC-DC converter typically has an input which is switchably connected to an inductor. The other side of the inductor may be connected to a capacitor and provides a regulated DC output. Using a pair of transistors or other switches, the input to the inductor is switched between the nominal supply voltage and nominal ground. The current through the inductor thus alternately increases and decreases. The average voltage at the output thus depends, to a first approximation, on the mark-space ratio of the input voltage: at one extreme, if the input voltage is always at nominal supply, the output voltage will also be at nominal supply; at the opposite extreme, if the input voltage is always at nominal ground, the output voltage will also be at nominal ground. For a typical mark-space ratio where the input to the inductor is high for 50% of the cycle time, the output voltage will be nominally 50% of the supply voltage. In general, for a buck converter, the output voltage (Vout) is equal to the input voltage (vVn), scaled by the dutycycle:
Vout=Vin·Dutycycle
In such a hysteretic converter, the current through the inductor typically has a saw-tooth profile. The current increases from a desired minimum or valley level, linearly, until it reaches a desired maximum or peak level. Once it reaches this maximum desired level, the input is switched to low, and the current falls, again linearly, from the peak level to the desired valley level. Once the current reaches the desired valley level, the input is again switched, this time to the high or supply voltage, and the current in the inductor starts to rise again. Thus the current has an approximately saw-tooth profile. The profile is typically not symmetrical: that is to say the current typically will rise at a different rate from that at which it falls.
In a practical device, this current cycle or current loop normally does not follow the idealised saw-tooth described above. One particular delay in the loop, or loop-delay, which causes inaccuracies, is the delay attributable to the comparator: in order to determine when to switch the input voltage, the inductor current is sensed (usually by means of a voltage across a sensing resistor); this voltage is compared to a reference level by means of a comparator; however, because of the time taken by the comparator to establish the comparison, the input voltage is not switched until a moment somewhat after the current passes the reference level. Thus, because of this delay, there is a current overshoot and/or undershoot beyond the intended peak or valley level.
In a hysteretic converter, the average current will be midway between the peak and valley levels. The expected average current will be midway between the internally set reference peak and valley levels. However, if there is a delay, Td, from the moment of the current crossing the reference level to the moment when the converter switches the other way, this will result in a current overshoot which is equal to Td×dI/dt_rise, where I is current through the inductor, the dI/dt is the rate of change of current, and dI/dt_rise refers to the current slope during the rise period. An equivalent undershoot would equal Td×dI/dt_fall.
This results in the following two effects: firstly, the ripple, which may be defined as the variation between the maximum and minimum current through the inductor, will be more than that intended, by the sum of the overshoots; secondly, if the rising and falling slopes, dI/dt_rise and dI/dt_fall, are different, which is usually the case, there will be a deviation between the actual average current, and the intended average current (which is the mean of the reference peak and valley levels).
US patent application publication US 2007/0103126 discloses a method to compensate for the DC offset attributable to the mismatch between undershoot and overshoot. Based on a measured overshoot, the fall period of the inductor current is extended such that the current falls below the reference value level. Since the current fall rate is generally lower than the current rise rate, the loop delay at the valley would normally result in less undershoot than the overshoot which is experienced at the peak. However, the undershoot period is deliberately extended in time such that the undershoot current is equivalent to the overshoot current: the effects therefore cancel out and the average current resulting is the mean of the reference peak and valley levels. Thus, this prior art compensates for the average current offset, but in fact increases the output ripple. Moreover, the method is calculation intensive and does not take into account variation in the loop delay Td due to process, voltage and temperature changes. These variations can be significant.
There thus remains an ongoing requirement for methods to compensate for the loop delay in DC-DC converters.
It is an object of the present invention to provide an improved method for compensating for loop delay in DC-DC converters.
According to the invention there is provided a method of controlling a DC-DC converter having a first state and a second state each of which is either a charging state or a discharging state, the DC-DC converter being arranged to change state from the first state to the second state in dependence on a predetermined limit value of a signal, and having a delay between a change instruction and a change of state from the first state to the second state, the method comprising the steps of:
Preferably the signal is a voltage, since this provides a particularly convenient signal to measure and manipulate.
Typically the overshoot is equal to the rate of change of voltage multiplied by the delay.
Beneficially, step (a) may comprise applying a copy of the voltage across a first capacitor to produce a resulting current, and step (c) may comprise charging a second capacitor with a mirror of the resulting current. These represent particularly convenient implementations of the above steps, which are easily and inexpensively put into practice using it analogue components. Alternatively these steps may be carried out through digital processing.
Advantageously, the overshoot may be determined in step (c) by means of determining the voltage across the second capacitor, at the end of a charging period corresponding to the delay signal.
The above advantageous but not limiting aspects of the invention are equally applicable to the transition between the discharging and charging state, mutatis mutandis.
Advantageously, the invention encompasses controlling the DC-DC converter during the charging-to-discharging transition as described above, and subsequently controlling the DC-DC converter from the discharging-to-charging transition as described above. Thus the invention encompasses full control of the inverter at both ends of the current loop.
In a particularly convenient implementation, the DC-DC converter is operable under hysteretic control. Alternatively or additionally the DC-DC converter may be operable under peak current control and/or valley current control.
These and other aspects of the invention will be apparent from, and elucidated with reference to, the embodiments described hereinafter.
Embodiments of the invention will be described, by way of example only, with reference to the drawings, in which
It should be noted that the Figures are diagrammatic and not drawn to scale. Relative dimensions and proportions of parts of these Figures have been shown exaggerated or reduced in size, for the sake of clarity and convenience in the drawings. The same reference signs are generally used to refer to corresponding or similar features in modified and different embodiments.
The output current from the inductor 5 is sensed by means of senses resistor 8, which is connected between load 9 and ground.
In this particular example the load 9 is shown as a string of lights emitting diodes (LEDs); however, the load is not limited to LEDs, and could be, for example, fluorescent lamps, battery which is being charged, PC circuitry, mobile device electronics and the like. In each case, the current sensing resistor has to be placed at the appropriate location to get the actual current: thus it may be located at the switch side of the inductor or between the switch and the supply, or between the switch and ground, as appropriate.
Within the control means 10, resides a differential amplifier and comparator 11.
As described up to this point, the hysteretic converter is the same as prior art hysteretic converters. In operation of such prior art converters, the current through the inductor, and load, is sensed by means of sense resistor 8. The voltage across the sense resistor 8 is input into the comparator and differential amplifier 11. This voltage is compared in the comparator 11 with a peak voltage (Vpeak)—not shown—for the peak comparison, and to a valley voltage (Vval)—not shown—of the respective valley comparison. The output from the comparator (shown at 13) is input to the control means 7 for driving the high side and low side switches 2 and 3 respectively.
In contrast, as shown in
An overview of the operation of this embodiment of the invention will now be given with reference to
The operation of this embodiment of the invention may easily be understood with reference to
A better understanding of this aspect of the embodiment may be obtained by comparison of
In this embodiment of the invention an analogous compensation method is applied, mutatis mutandis to the valley level of the sense voltage. That is to say, an undershoot rather than an overshoot is avoided, by increasing the predetermined valley level by an offset 222, to result in an adjusted valley level 221, 221′. The decision to switch the high side and low side switches, by the comparator, is taken at the moment the sense voltage 300 crosses the adjusted valley voltage 221. Because of the delay, however, the decision only takes effect at a later moment, at which time the sense voltage 300 has reached exactly the original predetermined valley level.
As shown in
Operation of this embodiment of the invention will now be described in more detail with reference to the wave forms of
I1 and I2 represent the current at the respective input and output of the directional current mirror 15 shown in
In order to accurately and repeatedly compensate for the delay, it is important to be able to accurately and repeatedly calculate the required offset to the voltage peak and voltage valley 34 and 44 respectively. This is done in this embodiment by using the timing information of trace 404. The timing information accurately replicates the actual delay Td. A voltage saw-tooth 405 is then constructed using two input elements: the repetition rate of the saw-tooth is directly determined from the timing information 404; the gradient of the saw-tooth is determined from the gradient of the sense voltage. In the particular implementation shown in
Once the switches have been switched and the current through the inductor, and thus sense voltage 401, is reducing, a new saw-tooth voltage is established, as shown at the second section of trace 405. The same timing information 404 is used such that the period Td of the saw-tooth is unchanged with respect to the first section of trace 405, however, the gradient of the saw-tooth now corresponds to the rate of fall of Vsense. Since in this instance Vsense falls more slowly than it had been rising, the gradient of the saw-tooth is lower than that in the first section. The peak value reached by the saw-tooth before being reset after period Td is thus lower than that in this first section. Thus in this example the offset to the valley voltage, 407, is smaller than the equivalent offset in the peak voltage, 406. (For clarity, and ease of understanding, it is noticed that this is the opposite relationship to that shown in the example of
Since at any one time the sense voltage 401 is either rising or falling, and not both, only one of offset 406 and 407 is required at any time, hence the same capacitor C3 can be used to store the offset information for both valley and peak.
The adjusted peak and valley voltages, 35 and 45 as shown on
A circuit diagram according to a second embodiment of the invention is shown in
In
The current mirror 515 mirrors the C501 charging current, through the source of transistor 517 which thus as a saw-tooth.
Thus, the drain of transistor 517, which corresponds to saw-tooth node Vsaw (551) is connected to ground via capacitor C502; the gate of transistor 517 is connected to the saw-tooth timing input 518. Saw-tooth timing node 518 is also connected as gate to a transistor 560 which is connected between the voltage saw-tooth node 551 and ground. Thus saw-tooth node 551 is the voltage across capacitor C502, and the saw-tooth is made by supplying the mirrored current for the exact duration as the T_delay. Thus input 508 is high for time T_delay, then low for some time, then high again for T_delay. During the low phase of 508, transistor 560 will discharge c502. This results in a saw-tooth, having alternate charging and discharging phases.
The voltage saw-tooth node 551 charges capacitor C503 via diode 541, to produce the Vpeak-offset, at node 550 (that is, at the high side of capacitor C503). The peak-offset node 550 is also connected to ground via reset transistor 561, the gate of which is connected to the comparator output comp_out.
Operationally, this circuit works as described above with regard to the schematic diagram of
The current mirror 715 mirrors the C701 charging current, through the source of transistor 717 which thus as a saw-tooth.
The low side connection to the voltage buffer 714 is connected to current mirror 715, the output from which is connected only indirectly to the source of transistor 717 which is acting as a saw-tooth. That is, unlike the circuit of
The drain of transistor 717, which corresponds to saw-tooth node Vsaw (551) is connected to ground via capacitor C702; the gate of transistor 717 is connected to the saw-tooth timing input 718. Saw-tooth timing node 718 is also connected as gate to a transistor 760 which is connected between the voltage saw-tooth node 751 and ground. Thus saw-tooth node 751 is the voltage across capacitor C702, and the saw-tooth is made by supplying the mirrored current for the exact duration as the T_delay. Thus input 708 is high for time T_delay, then low for some time, then high again for T_delay. During the low phase of 708, transistor 760 will discharge C702. This results in a saw-tooth, having alternate charging and discharging phases.
The voltage saw-tooth node 751 charges capacitor C703 via diode 541, to produce the Vvalley-offset, at node 750 (that is, at the high side of capacitor C703). The valley-offset node 750 is also connected to ground via reset transistor 761, the gate of which is connected to the comparator output comp_out.
The current mirrors described above with reference to
From the above description, and since the two phases are implemented by different circuits, it will be apparent that the signal I2 of
The invention has been described with respect to a hysteretic converter embodiment; however, it is equally applicable to other forms of current control such as peak current control or valley current control.
Furthermore the invention has been described with reference to an embodiment which is implemented entirely by using analogue components. It would be immediately apparent to the skilled person that equivalent functionality can be achieved by digital signal processing, and such embodiments are included within this scope of the invention.
From reading the present disclosure, other variations and modifications will be apparent to the skilled person. Such variations and modifications may involve equivalent and other features which are already known in the art of DC-DC converters and which may be used instead of, or in addition to, features already described herein.
Although the appended claims are directed to particular combinations of features, it should be understood that the scope of the disclosure of the present invention also includes any novel feature or any novel combination of features disclosed herein either explicitly or implicitly or any generalisation thereof, whether or not it relates to the same invention as presently claimed in any claim and whether or not it mitigates any or all of the same technical problems as does the present invention.
Features which are described in the context of separate embodiments may also be provided in combination in a single embodiment. Conversely, various features which are, for brevity, described in the context of a single embodiment, may also be provided separately or in any suitable sub-combination.
The applicant hereby gives notice that new claims may be formulated to such features and/or combinations of such features during the prosecution of the present application or of any further application derived therefrom.
For the sake of completeness it is also stated that the term “comprising” does not exclude other elements or steps, the term “a” or “an” does not exclude a plurality, a single processor or other unit may fulfil the functions of several means recited in the claims and reference signs in the claims shall not be construed as limiting the scope of the claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 08104896.9 | Jul 2008 | EP | regional |
| Filing Document | Filing Date | Country | Kind | 371c Date |
|---|---|---|---|---|
| PCT/IB2009/053275 | 7/28/2009 | WO | 00 | 1/25/2011 |
