Delay control circuit

Abstract

A first variable delay circuit delays an input signal, introduces a first delay into a first edge of the input signal, and generates a first delay signal. A second variable delay circuit delays the input signal, introduces a second delay into a second edge, and generates a second delay signal. A control circuit controls the first variable delay circuit and the second variable delay circuit such that the first delay and the second delay are identical. A generation circuit combines the first edge of the first delay signal and the second edge of the second delay signal, and generates a third delay signal.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a principle view of a delay control circuit according to the present invention;

FIG. 2 shows a configuration of a delay correction loop circuit;

FIG. 3 shows a timing chart for the delay correction loop circuit;

FIG. 4 shows a configuration of a first variable delay circuit;

FIG. 5 shows a configuration of a duty ratio correction circuit;

FIG. 6 shows a timing chart for the duty ratio correction circuit;

FIG. 7 shows a configuration of a phase generator;

FIG. 8 shows a timing chart for the phase generator;

FIG. 9 shows a configuration of a phase detector;

FIG. 10 shows a timing chart for the phase detector;

FIG. 11 shows a configuration of a first counter circuit;

FIG. 12 shows a configuration of a second variable delay circuit;

FIG. 13 shows a configuration of a second counter circuit; and

FIG. 14 shows a configuration of a third variable delay circuit.

Claims

1. A delay control circuit, comprising: a first variable delay circuit which delays an input signalto introduce a first delay into a first edge which is one of a rising edge and a falling edge of the input signal, thereby generates a first delay signal;a second variable delay circuit which delays the input signalto introduce a second delay into a second edge which is the other one of the rising edge and the falling edge of the input signal, thereby generates a second delay signal;a control circuit which generates a control signal for controlling the first variable delay circuit and the second variable delay circuit such that the first delay and the second delay are identical; anda generation circuit which combines the first edge of the first delay signal and the second edge of the second delay signal, thereby generates a third delay signal.

2. The delay control circuit according to claim 1, wherein: the second variable delay circuit has a configuration equivalent to that of the first variable delay circuit; andthe control circuit outputs a control signal which is common to the first variable delay circuit and the second variable delay circuit.

3. The delay control circuit according to claim 2, further comprising: an inverter circuit which inverts the input signal, and which outputs the inverted signal, wherein:the second variable delay circuit delays the inverted signal, and generates the second delay signal.

4. The delay control circuit according to claim 1, wherein: the generation circuit includes a selection circuit for selecting the first edge of the first delay signal or the second edge of the second delay signal, and a latch circuit for latching the input signal by using the selected edge, and for generating the third delay signal.

5. The delay control circuit according to claim 1, wherein: the first variable delay circuit delays the input signal, and generates a fourth delay signal; andthe control circuit includes a phase generation circuit for generating a phase comparison signal by using the fourth delay signal, and a phase detection circuit for detecting a phase difference by comparing phase relationships of the input signal and the phase comparison signal, and generates the control signal based on the detected phase difference.

6. The delay control circuit according to claim 5, wherein: the control circuit further includes a counter circuit for performing a count up operation or a count down operation based on the phase difference, and for outputting a count value, and generates the control signal from the count value.

7. The delay control circuit according to claim 5, wherein: the phase detection circuit includes a first comparison circuit for comparing the input signal and a threshold value signal by using an edge of the phase comparison signal, and a second comparison circuit for comparing the phase comparison signal and the threshold value signal by using an edge of the input signal.

8. The delay control circuit according to claim 1, wherein: the first variable delay circuit and the second variable delay circuit respectively include a plurality of capacitor circuits, and a plurality of switch circuits for connecting the plurality of capacitor circuits to a transmission path of the input signal; andthe control circuit adjusts the first delay and the second delay by switching the plurality of switch circuits with the control signal.

9. The delay control circuit according to claim 1, wherein: the first variable delay circuit and the second variable delay circuit respectively include a capacitor circuit connected to a transmission path of the input signal, a plurality of current source circuits, and a plurality of switch circuits connecting the plurality of current source circuits to the transmission path; andthe control circuit adjusts the first delay and the second delay by switching the plurality of switch circuits with the control signal.

10. The delay control circuit according to claim 1, wherein: the first variable delay circuit and the second variable delay circuit respectively include a capacitor circuit connected to a transmission path of the input signal, a current source circuit, a switch circuit for connecting the current source circuit to the transmission path; andthe control circuit adjusts the first delay and the second delay by switching the switch circuit with the control signal and adjusting a time during which the current source circuit is connected to the transmission path.

11. A method of controlling a delay, comprising: delaying an input signal to introduce a first delay into a first edge which is one of a rising edge and a falling edge of the input signal, thereby generating a first delay signal;delaying the input signal to introduce a second delay into a second edge which is the other one of the rising edge and the falling edge of the input signal, thereby generating a second delay signal;controlling the first delay and the second delay such that the first delay and the second delay are identical; andcombining the first edge of the first delay signal and the second edge of the second delay signal, thereby generating a third delay signal.